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Compal Confidential
2

PBL60 Schematics Document


AMD APU Zacate-FT1 + FCH Hudson-M1 + GPU Seymour XT-M2

2010-02-15

REV:1.0

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

P01-Cover Page
Size
B
Date:

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
E

of

47

Compal confidential
File Name : LA-7322P
AMD Seymour-XT
PCI-E GPP x4 GEN2

DDR3 VRAM
512M/1G
64*16/128*16 *4

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

AMD Brazos APU


FT1
BGA 413-Ball
19mm x 19mm

page 17 ~ 24

LVDS Conn.

LVDS(UMA & PX)

HDMI Conn.

HDMI(UMA & PX)

CRT Conn.

CRT(UMA & PX)

Single Channel

page 10

page 8,9

BANK 0, 1, 2, 3

1.5V DDRIII

page 11

page 10

page 5,6,7

UMI Gen.1 x4
2.5GT/s per lane

Port 0

SATA

SATA HDD Conn.

Port 1

page 29

SATA ODD Conn.

page 29

Hudson M1

PCI-E 2.0 x1

2Channel Speaker

BGA 605-Ball
23mm x 23mm
Port 1

page 26

AZALIA

Port 0

Audio Codec
ALC269

Audio Jacks X 2
(Headphone, MIC)

page 26

Mini Card-1 WLAN


(With Bluetooth)

LAN(GbE)
RTL8111E

page 28

DMIC

USB2.0

page 10

page 25

page 12 ~ 16

Port 0

Port 1

LPC BUS

RJ45

page 25

page 30

Touch Pad

SPI ROM

Int.KBD

page 31

page 30

page 31

USB Conn.
USB Conn.

Port 5

USB Conn.
(LS-7322P)

Port 2

Camera

ENE KB930

LS-7326P
Power BD

page 26

page 32

page 32

page 10

Port 3

Mini Card WLAN


(With Bluetooth)
page 28

Port 4

Card Reader
RTS5137 page

27

LS-7322P
Audio BD

Thermal Sensor
page 18

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

P02-Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
E

of

47

Voltage Rails

Power Plane

Description

S1

VIN

Adapter power supply (19V)

N/A

B+

AC or battery power rail for power circuit.

N/A

S5

FCH Hudson-M1
USB Port List

N/A

N/A

USB1.1

N/A

N/A

S3

+APU_CORE

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+APU_CORE_NB

1.0V switched power rail

ON

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDRIII

ON

ON

OFF

+0.75VS

0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VS

1.0V switched power rail for NB VDDC & VGA

ON

OFF

OFF

+1.1VS

1.1VS switched power rail

ON

OFF

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V_LAN

3.3V power rail for LAN

ON ON(WOL)

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

+1.1VALW

1.1V always on power rail

ON

ON

ON*

SMBUS Control Table

BATT

X
X

V
X

FCH
(+3VS)

FCH
(+3VALW)

EC_SMB_CK1
EC_SMB_DA1

KB930

EC_SMB_CK2
EC_SMB_DA2

KB930

FCH_SMCLK0
FCH_SMDAT0
FCH_SMCLK3
FCH_SMDAT3

APU

FCH

SODIMM

VRAM

X
V
X

X
V
X

X
X
V

X
V
X

PCIE0

Port0

NC

Port1

NC

PCIE1
PCIE2

GPU
PCIE x4

FCH Hudson-M1
SATA Port List
SATA0

HDD

SATA1

ODD

SATA2

NC

SATA3

NC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

MIINI1

Brazos
PCIE Port List

USB2.0

OFF

+5VS

SOURCE

APU

SCL0,
SCL1,
SCL2,
SCL3,
SCL4,

PCIE3

Port0

JUSB1

PCIE0

LAN

SATA4

NC

Port1

JUSB2

PCIE1

WLAN

SATA5

NC

Port2

Camera

PCIE2

NC

Port3

JMINI(WLAN)

PCIE3

NC

Port4

Card Reader

Port5

JUSB3

Port6

NC

Port7

NC

Port8

NC

Port9

NC

Port10

NC

Port11

NC

Port12

NC

Port13

NC

SDA0
SDA1
SDA2
SDA3
SDA4

FCH

(Primary SMBUS in the S0 domain)


(Secondary SMBUS supporting ASF)
(Primary SMBUS in the S5 domain)
(Primary low-voltage SBMBUS for Processor TSI)
(Primary SMBUS in the S5 domain)

L01 :

16G@/VGA@/LS@/X76@L03

L02 :

16G@/UMA@/LS@

L03 :

15G@/VGA@/LS@/X76@L03

L04 :

15G@/UMA@/LS@

L05 :

16G@/VGA@/LS@/X76@L01

: means Digital Ground

L06 :

15G@/VGA@/LS@/X76@L01

L07 :

1G@/VGA@/LS@/X76@L03

: means Analog Ground

L08 :

1G@/UMA@/LS@

L09 :

1G@/VGA@/LS@/X76@L01

Symbol Note :
BOM Structure

15G@: 1.5G CPU (E240)


16G@: 1.6G CPU (E350)
1G@ : 1G
CPU (C50)
UMA@ : APU output.
VGA@ : GPU used.
LS@ : Level shift used.
X76@L01 :VRAM 1G.
X76@L03 :VRAM 512M.

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

P03-Notes List
Size
B
Date:

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
E

of

47

Power-Up/Down Sequence

BACO option :

2. VDDR3 should ramp-up before or simultaneously with VDDC.

PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)


PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)

VDDR3(3.3VSG)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V)
C

PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation


PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.

Without BACO option :

VDDR1(1.5VSG)

dGPU Power Pins

Voltage

PX 3.0

BACO Mode Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,


DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18

1.8V

OFF

ON

1679mA

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and


SPV10

1.0V

OFF

ON

575mA

PCIE_VDDC

1.0V

OFF

ON

2A

VDDR3 , and A2VDD

3.3V

OFF

ON

190mA

BIF_VDDC (current consumption = 55mA@1.0V, in


BACO mode)

Same as
VDDC

OFF

ON
Same as
PCIE_VDDC

70mA

VDDR1

1.5V

OFF

OFF

2.8A

VDDC/VDDCI

1.12V

OFF

OFF

12.9A

VDDC/VDDCI(1.12V)
VDD_CT(1.8V)

iGPU

PE_GPIO0

PE_EN

dGPU

PERSTb

BACO Switch

BIF_VDDC
PE_GPIO1

REFCLK

PX_mode

+3.3VALW

Straps Reset

+1.0V

Straps Valid

MOS

Regulator

+3.3VSG

1
+1.0VSG

+1.5V

+1.5VSG

SI4800

Regulator

Global ASIC Reset


+1.8V

SI4800

T4+16clock

+B

+1.8VSG

+VGA_CORE

PWRGOOD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

P04-dGPU Block Diagram


Size
B
Date:

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
1

of

47

+1.8VS

D10
C10

TDP1_TXP2
TDP1_TXN2

11 APU_HDMI_CLKP
11 APU_HDMI_CLKN

A10
B10

TDP1_TXP3
TDP1_TXN3

10 APU_TXOUT2+
10 APU_TXOUT2-

B5
A5

LTDP0_TXP0
LTDP0_TXN0

10 APU_TXOUT1+
10 APU_TXOUT1-

D6
C6

LTDP0_TXP1
LTDP0_TXN1

APU_PROCHOT#

2 1K_0402_5%

12
12
R411 1

2 1K_0402_5%

APU_ALERT#_R

R143 1

2 1K_0402_5%

APU_SIC

R414 1

2 1K_0402_5%

APU_SID

10 APU_TXCLK+
10 APU_TXCLK-

D8
C8
V2
V1

APU_CLKP
APU_CLKN

D2
D1

12 APU_DISP_CLKP
12 APU_DISP_CLKN
43
43

APU_SVC
APU_SVD
APU_SIC
APU_SID
12 APU_RST#
12 APU_PWRGD

R169 1
R168 1

30 EC_THERM#
12 FCH_PROCHOT#

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

T93PAD
T94PAD
Close to APU
43 APU_VDDNB_RUN_FB_H
43 APU_VDD0_RUN_FB_H
T77PAD

DISP_CLKIN_H
DISP_CLKIN_L
SVC
SVD
SIC
SID

T3
T4

RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L

N2
N1
P1
P2
M4
M3
M1

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

F4
G1
F3

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

B4
W11
V5
+3VS

LTDP0_AUXP
LTDP0_AUXN

A3
B3

LTDP0_HPD

D3

DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC

C12
D13
A12
B12
A13
B13

F2
D4

DAC_ZVSS

D12

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

APU_HDMI_CLK
APU_HDMI_DATA

R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

APU_HDMI_HPD 11
APU_LCD_CLK
APU_LCD_DATA

RSVD_1
RSVD_2
RSVD_3

APU_LCD_CLK 10
APU_LCD_DATA 10

R406 1

2 100K_0402_5%

+5VS

R407 1

2 150_0402_1%

R408 1

2 150_0402_1%

R409 1

2 150_0402_1%

APU_CRT_R 10
APU_CRT_G 10
APU_CRT_B 10
APU_CRT_HSYNC 10
APU_CRT_VSYNC 10
APU_CRT_DDC_SCL 10
APU_CRT_DDC_SDA 10

R144 1

2 499_0402_1%
PAD T66
PAD T67
PAD T68

TEST15

R415 1

TEST18
TEST19
TEST25_H
TEST_25_L

R416 1
R417 1
R418 1

2 1K_0402_5%

2 1K_0402_5%
2 1K_0402_5%
2 510_0402_1%

TEST31
PAD T73
TEST33_H
C516 1
R420 1
2 0.1U_0402_16V4Z
TEST33_L
C517 1
R421 1
2 0.1U_0402_16V4Z
Delete Test point for layout limitation
20100917
TEST35
R422 1
@
2 1K_0402_5%
TEST36
TEST37
R958 1
2 1K_0402_5%
PAD T76
+1.8VS
C639 1

TEST38
DMAACTIVE_L

APU_HDMI_CLK 11
APU_HDMI_DATA 11

E1
E2

DAC_SCL
DAC_SDA

VSS_SENSE

K3
T1

2 51_0402_1%
2 51_0402_1%

Close to U22

2 0.1U_0402_16V4Z
@

ALLOW_STOP# 12
R423 1

2 1K_0402_5%

+1.8VS

ZACATE ZM161032B2238 1.6G BGA 413P

AMD Debug

Q79
1

U22 1G@

H_THERMTRIP# 13

+1.8VS

MMBT3904_NL_SOT23-3
R427 1

JHDT1
ONTARIO CMC50AFPB22GT 1G

APU_TRST#

2
R842

FDV301N, the Vgs is:


min = 0.65V
Typ = 0.85V
Max = 1.5V

BSH111, the Vgs is:


min = 0.4V
Typ = 1.0V
Max = 1.3V

2 0.1U_0402_10V7K

@
1 R160

CPU TSI interface level shift

C236 1

+1.8VS

2 0_0402_5%

If FCH internal pull-up disabled, level-shifter could be deleted.


Need BIOS to disable internal pull-up!!

EC_SMB_DA

1
@
Q22
BSH111 1N_SOT23-3

APU_TCK

R843 2

1 1K_0402_5%

APU_TMS

R840 2

1 1K_0402_5%

APU_TDI

R798 2

1 1K_0402_5%

APU_TDO

10

10

APU_PWRGD

11

12

12

APU_RST#

14

APU_DBRDY

16

APU_DBREQ#

R178 1

2 300_0402_5%

18

J108_PLLTST0

R799 1

2 0_0402_5%

TEST19

20

J108_PLLTST1

R863 1

2 0_0402_5%

TEST18

R847 2

2 APU_TRST#_R
0_0402_5%
1 10K_0402_5%

11

R176 2

1 10K_0402_5%

13

R177 2

1 10K_0402_5%

15

R846 1

1
R429
1
R430

If use level shift, EC_SMB need pull up


(pop R747 & R748)

FCH_SID

2
0_0402_5%
EC_SMB_DA2
2
0_0402_5%

FCH_SID

13

EC_SMB_DA2 18,30

19

13

14

15

16

17

18

19

20

+1.8VS

Please be noted about TEST_18 and TEST_19

T0 FCH

SAMTE_ASP-136446-07-B
CONN@

TO EC

2 0_0402_5%

R431 1

17

G
APU_SID 3

30K_0402_1%

1.607V for Gate

C1

APU_ENBKL 10
APU_ENVDD 10
APU_BLPWM 10

U22 16G@

31.6K_0402_1%

TDP1_HPD

2 150_0402_1%

ONTARIO-2M161000-1.6G_BGA413
15G@

APU_THERMTRIP#

TDP1_AUXP
TDP1_AUXN

B2
C2

R398 1

R425
1K_0402_5%

@
1 R428

G2
H2
H1

R424
10K_0402_5%
@

2
B

CLKIN_H
CLKIN_L

P3
P4

F1

43 APU_VDD0_RUN_FB_L

LTDP0_TXP3
LTDP0_TXN3

J1
J2

APU_PROCHOT#
U1
APU_THERMTRIP# U2
APU_ALERT#_R
T2

2 0_0402_5%
2 0_0402_5%

LTDP0_TXP2
LTDP0_TXN2

H3

TEST

R410 1

A6
B6

CLK

+3VS

10 APU_TXOUT0+
10 APU_TXOUT0-

DP_ZVSS
DP_BLON
DP_DIGON
DP_VARY_BL

SER

C237 @
0.01U_0402_25V7K
APU_RST#
1
2
C238 @
0.01U_0402_25V7K
APU_PWRGD
1
2

DP MISC

11 APU_HDMI_TX0P
11 APU_HDMI_TX0N

VGA DAC

TDP1_TXP1
TDP1_TXN1

DISPLAYPORT 1

B9
A9

DISPLAYPORT 0

11 APU_HDMI_TX1P
11 APU_HDMI_TX1N

CTRL

2
2
1
1
2
2

TDP1_TXP0
TDP1_TXN0

JTAG

1
1
2
2
1
1

APU_SVC
APU_SVD
APU_RST#
APU_PWRGD
TEST_25_L
TEST36

1K_0402_5%
1K_0402_5%
300_0402_5%
300_0402_5%
510_0402_1%
1K_0402_5%

1K_0402_5%

R399
R400
R142
R401
R402
R141

+3VS

U22B
A8
B8

11 APU_HDMI_TX2P
11 APU_HDMI_TX2N

APU_SIC 3

EC_SMB_CK
1
@
Q23
BSH111 1N_SOT23-3
R434 1

@
1
R432
1
R433

FCH_SIC
2
0_0402_5%
EC_SMB_CK2
2
0_0402_5%

FCH_SIC

13

EC_SMB_CK2 18,30

TO EC

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

Title

Compal Electronics, Inc.


P05-FT1 CTRL/DP/CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 0_0402_5%
5

T0 FCH

Size Document Number


Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

of

47

U22E

8,9 DDR_A_DQS0
8,9 DDR_A_DQS#0
8,9 DDR_A_DQS1
8,9 DDR_A_DQS#1
8,9 DDR_A_DQS2
8,9 DDR_A_DQS#2
8,9 DDR_A_DQS3
8,9 DDR_A_DQS#3
8,9 DDR_A_DQS4
8,9 DDR_A_DQS#4
8,9 DDR_A_DQS5
8,9 DDR_A_DQS#5
8,9 DDR_A_DQS6
8,9 DDR_A_DQS#6
8,9 DDR_A_DQS7
8,9 DDR_A_DQS#7

9
9
9
9
8
8
8
8

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

9
9
8
8
9
9
8
8

D15
B19
D21
H22
P23
V23
AB20
AA16

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

M17
M16
M19
M18
N18
N19
L18
L17

DDR_RST#
DDR_EVENT#

8,9 DDR_RST#
8,9 DDR_EVENT#
8,9
8,9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_CKE0
DDR_CKE1

DDR_CKE0
DDR_CKE1

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

F15
E15

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

W19
V15
U19
W15

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

T17
W16
U17
V16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

8,9 DDR_A_RAS#
8,9 DDR_A_CAS#
8,9 DDR_A_WE#

L23
N17

U18
V19
V17

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

DDR SYSTEM MEMORY

R18
T18
F16

8,9 DDR_A_BS0
8,9 DDR_A_BS1
8,9 DDR_A_BS2

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

M_RESET_L
M_EVENT_L
M_CKE0
M_CKE1

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

B14
A15
A17
D18
A14
C14
C16
D16

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

C18
A19
B21
D20
A18
B18
A21
C20

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

C23
D23
F23
F22
C22
D22
F20
F21

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

H21
H23
K22
K21
G23
H20
K20
K23

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

N23
P21
T20
T23
M20
P20
R23
T22

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

V20
V21
Y23
Y22
T21
U23
W23
Y21

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

M23

+MEM_VREF

M22

R437

DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]

DDR_A_D[0..63]

8,9

DDR_A_MA[0..15]
DDR_A_DM[0..7]

8,9
8,9

U22A
17 PCIE_GTX_C_FRX_P0
17 PCIE_GTX_C_FRX_N0

PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0

AA6
Y6

17 PCIE_GTX_C_FRX_P1
17 PCIE_GTX_C_FRX_N1

PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1

AB4
AC4

17 PCIE_GTX_C_FRX_P2
17 PCIE_GTX_C_FRX_N2

PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2

AA1
AA2

17 PCIE_GTX_C_FRX_P3
17 PCIE_GTX_C_FRX_N3

PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3

Y4
Y3

+1.05VS

1
2
R435 2K_0402_1%

P_ZVDD_10

Y14

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_GPP_TXP0
P_GPP_TXN0

PCIE I/F

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3

P_ZVDD_10

P_ZVSS

AB6 PCIE_FTX_GRX_P0
AC6 PCIE_FTX_GRX_N0

C518 1VGA@2 0.1U_0402_16V7K


C519 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P0 17
PCIE_FTX_C_GRX_N0 17

AB3 PCIE_FTX_GRX_P1
AC3 PCIE_FTX_GRX_N1

C520 1VGA@2 0.1U_0402_16V7K


C521 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P1 17
PCIE_FTX_C_GRX_N1 17

Y1
Y2

PCIE_FTX_GRX_P2
PCIE_FTX_GRX_N2

C522 1VGA@2 0.1U_0402_16V7K


C523 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P2 17
PCIE_FTX_C_GRX_N2 17

V3
V4

PCIE_FTX_GRX_P3
PCIE_FTX_GRX_N3

C524 1VGA@2 0.1U_0402_16V7K


C525 1VGA@2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P3 17
PCIE_FTX_C_GRX_N3 17

AA14 P_ZVSS

R436 1

1.27K_0402_1%

Less than 1"


Less than 1"
12 UMI_RX0P
12 UMI_RX0N

AA12
Y12

12 UMI_RX1P
12 UMI_RX1N

AA10
Y10

12 UMI_RX2P
12 UMI_RX2N

AB10
AC10

12 UMI_RX3P
12 UMI_RX3N

AC7
AB7

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_UMI_TXP0
P_UMI_TXN0

UMI I/F

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

AB12
AC12

UMI_TX0P_C
UMI_TX0N_C

C526 1
C527 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AC11
AB11

UMI_TX1P_C
UMI_TX1N_C

C528 1
C529 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AA8
Y8

UMI_TX2P_C
UMI_TX2N_C

C530 1
C531 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AB8
AC8

UMI_TX3P_C
UMI_TX3N_C

C532 1
C533 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

UMI_TX0P 12
UMI_TX0N 12
UMI_TX1P 12
UMI_TX1N 12
UMI_TX2P 12
UMI_TX2N 12
UMI_TX3P 12
UMI_TX3N 12

ONTARIO-2M161000-1.6G_BGA413
15G@

M_VREF

M_RAS_L
M_CAS_L
M_WE_L
M_ZVDDIO_MEM_S
ONTARIO-2M161000-1.6G_BGA413
15G@

15 mils

+1.5V

39.2_0402_1%

DDR_CKE0
DDR_CKE1

DDR_EVENT#

2
1

2
1K_0402_5%

R1706
68_0402_5%

+MEM_VREF

R149 1

R438
1K_0402_1%

R1705
68_0402_5%

2
+1.5V

+1.5V

R439
1K_0402_1%

C534

C535

1000P_0402_50V7K

0.1U_0402_16V4Z

Place within 1000 mils to APU


20100526

For AMD recommend to fix S3 issue.

Compal Secret Data

Security Classification
Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


P06-FT1 DDRIII/UMI/PCIE

Size
Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

of

47

+APU_CORE
+1.8VS

10U_0603_6.3V6M
2

C576

C577

10U_0603_6.3V6M
2

C578

10U_0603_6.3V6M
2

C579

10U_0603_6.3V6M
2

10U_0603_6.3V6M

1U_0402_6.3V6K
2

C583

C584

1U_0402_6.3V6K
2

C585

1U_0402_6.3V6K
2

C586

1U_0402_6.3V6K
2

C587

1U_0402_6.3V6K
2

180P_0402_50V8J
2

C588

1
@
2

10U_0603_6.3V6M

1U_0402_6.3V6K
C548

1U_0402_6.3V6K
C547

1U_0402_6.3V6K
C538

0.1U_0402_16V7K
C546

1U_0402_6.3V6K
C549

FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816
+1.05VS

VDDPL_10

L31
+VDDL_10

U11

2
1

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11

10U_0603_6.3V6M

0.2A

5.5A
VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4

U13
W13
V12
T12

FBMA-L11-201209-221LMA30T_0805

L32
2

0.5A
VDD_33

+VDD_10
1

1
FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC

C580

180P_0402_50V8J
2

S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 --->+APU_CORE(Qty : 3) Unpop:2

+APU_CORE

+APU_CORE_NB

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU--->+APU_CORE_NB(Qty : 1)

C591

0.1U_0402_16V7K
2

C592

C593

0.1U_0402_16V7K
2

C594

0.1U_0402_16V7K
2

1
C590

10U_0603_6.3V6M
2

C595

1
C596

1U_0402_6.3V6K
2

POWER

10U_0603_6.3V6M
2

0.1U_0402_16V7K
2

Power Cap. Summary


APU

S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->+APU_CORE_NB(Qty : 1)


C589

ONTARIO-2M161000-1.6G_BGA413
15G@

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+APU_CORE(Qty : 2)

+1.5V

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

+3VS

A4

ONTARIO-2M161000-1.6G_BGA413
15G@
C582

180P_0402_50V8J
C537

C545

POWER

10U_0603_6.3V6M
C684

VDD_18_DAC

2
10U_0603_6.3V6M
C604

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22

DP Phy/IO

G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

Change from SM010014520 to SD002000080


20100816

L30
+VDD_18_DAC

W9

DDR3

C575

2A

U22D
A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

+1.8VS

0.15A

PCIE/IO/DDR3 Phy

+1.5V

10U_0603_6.3V6M

+APU_CORE_NB

10U_0603_6.3V6M
C574

0.1U_0402_16V7K
2

1U_0402_6.3V6K
C573

0.1U_0402_16V7K
2

E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

10U_0603_6.3V6M

C563

10A

1U_0402_6.3V6K
C572

0.1U_0402_16V7K
2

+APU_CORE_NB

1U_0402_6.3V6K
C567

C562

0.1U_0402_16V7K
C571

C555

180P_0402_50V8J
2

1U_0402_6.3V6K
C558

1
C554
180P_0402_50V8J
2

0.1U_0402_16V7K
C566

U8
W8
U6
U9
W6
T7
V7

0.1U_0402_16V7K
C570

C553

1U_0402_6.3V6K
2

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7

1U_0402_6.3V6K

10U_0603_6.3V6M
2

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15

DIS PLL

0.1U_0402_16V7K
2

10U_0603_6.3V6M
2
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

L29
2
1
FBMA-L11-201209-221LMA30T_0805

GND

C561

C540

GPU AND NB CORE

1
C544

DAC

C560

C556

C552

1U_0402_6.3V6K
2

2
1U_0402_6.3V6K

1
C559
0.1U_0402_16V7K
2

C543

180P_0402_50V8J
C557

C551

1U_0402_6.3V6K
2

10U_0603_6.3V6M
2

C564

1
C550

C542

CPU CORE

10U_0603_6.3V6M
2
2
10U_0603_6.3V6M

180P_0402_50V8J
C565

C541

C568

180P_0402_50V8J
C569

C536

+VDD_18

0.1U_0402_16V7K
C581

1
C539

2A
TSense/PLL/DP/PCIE/IO

U22C

11A

+APU_CORE

C597

1U_0402_6.3V6K
2

C598

1U_0402_6.3V6K
2

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5V(Qty : 1)

+1.5V

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->1.05VS(Qty : 1)

+1.05VS

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.8VS(Qty : 1)

+1.8VS

DDR3 Socket

1U_0402_6.3V6K
2

S POLY C 330U 2V M X LESR6M SX H1.9 --->1.5V(Qty : 1)

+1.5V

+1.05VS

FCH
S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->1.1VS(Qty : 1) UMA unpop
1

0.1U_0402_16V7K
2

C601

0.1U_0402_16V7K
2

C602

0.1U_0402_16V7K
2

C603

180P_0402_50V8J
2

+1.1VS

GPU

180P_0402_50V8J
2

S POLY C 330U 2V M X LESR6M SX H1.9 --->VGA_CORE(Qty : 2) Unpop:1

+GPU_CORE

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+VGA_CORE(Qty : 1)


S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5VSG(Qty : 1)

+1.5V

POWER

USB

C103
180P_0402_50V8J

By case (Along split plane)

1
1

C623

C685

C624 +

C622 +

C617 +

C618 +

390U_2.5V_10M
2

390U_2.5V_10M
2

C619

10U_0603_6.3V6M
2
2
390U_2.5V_10M
2
10U_0603_6.3V6M

390U_2.5V_10M
2

C625
@
10U_0603_6.3V6M
2

10U_0603_6.3V6M
2

Near CPU Socket

Near CPU Socket

Compal Secret Data

Security Classification

Near CPU Socket

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00)

Title

Compal Electronics, Inc.


P07-FT1 PWR/VSS

Size
C
Date:

C613

C612

C608

180P_0402_50V8J

POWER
C611

+1.8VS

0.1U_0402_16V7K

POWER

+1.5V

Near CPU Socket


1

FOR EMI PURPOSE

+1.5V

+APU_CORE_NB

+USB_VCCA

C104
180P_0402_50V8J

C610

C102
0.1U_0402_16V7K

0.1U_0402_16V7K

C609

10U_0603_6.3V6M
1
C616
@
390U_2.5V_10M
2
2

C101
0.1U_0402_16V7K

0.1U_0402_16V7K

C605 +
@
330U_D2E_2.5VM_R9M
2

+1.5VSG

S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 --->+USB_VCCA(Qty : 1)


2

330U_D2E_2.5VM_R9M
C606
1
1
1
1
390U_2.5V_10M 390U_2.5V_10M
+@
C607 +
C1104+
C1105+

0.1U_0402_16V7K

+APU_CORE

180PF Qt'y follow the distance between


CPU socket and DIMM0. <2.5inch>

C615

1
C600

180P_0402_50V8J

C614

C599

180P_0402_50V8J

C621 +
@
390U_2.5V_10M
2

180P_0402_50V8J

1
C620
@
10U_0603_6.3V6M
2

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
1

of

47

+1.5V

+1.5V
JDIMM1

+VREF_DQ
1
C680

DDR_A_D0
DDR_A_D1

1
C681

0.1U_0402_16V4Z
2
D

DDR_A_DM0
1000P_0402_50V7K
2
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9

6,9 DDR_A_DQS#1
6,9 DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
6,9 DDR_A_DQS#2
6,9 DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0 6,9
DDR_A_DQS0 6,9

DDR_A_D[0..63]

6,9

DDR_CKE0

6,9 DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
6
6

DDR_B_CLK2
DDR_B_CLK#2
DDR_A_MA10

6,9 DDR_A_BS0
6,9 DDR_A_WE#
6,9 DDR_A_CAS#
DDR_A_MA13
6 DDR_CS1_DIMMB#

DDR_A_D32
DDR_A_D33
6,9 DDR_A_DQS#4
6,9 DDR_A_DQS4

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
6,9 DDR_A_DQS#6
6,9 DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1
2
R155 10K_0402_5%

DDR_A_DM[0..7]

@
1
2
R150 10K_0402_5%
1
2
R152 10K_0402_5%
@

R151

10K_0402_5%

205

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

G1

G2

DDR_A_DM[0..7] 6,9

DDR_A_DM1
DDR_RST# 6,9
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 6,9
DDR_A_DQS3 6,9

+1.5V

DDR_A_D30
DDR_A_D31
2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

0.1U_0402_16V4Z
2

1
0.1U_0402_16V4Z

DDR_CKE1 6,9

C45
1

0.1U_0402_16V4Z
2
2

2
C652

C653

1
1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
2
C654

C655

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
2
C682

1
1
0.1U_0402_16V4Z

C683

C47

1
0.1U_0402_16V4Z

2
C48

1
0.1U_0402_16V4Z

C49
0.1U_0402_16V4Z
C

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

CRB 0.1u X1

4,7uX1

DDR_A_MA2
DDR_A_MA0
+0.75VS
DDR_B_CLK3 6
DDR_B_CLK#3 6

2
C50
@
0.1U_0402_16V4Z
1

DDR_A_BS1 6,9
DDR_A_RAS# 6,9
DDR_CS0_DIMMB# 6
DDR_B_ODT0 6

C51

1
C664

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
1
2

DDR_B_ODT1 6
+VREF_CA
DDR_A_D36
DDR_A_D37

1
C665

Place near JDIMM2

1
C666

DDR_A_DM4
DDR_A_D38
DDR_A_D39

0.1U_0402_16V4Z
2

1000P_0402_50V7K
2

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5 6,9
DDR_A_DQS5 6,9
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 6,9
DDR_A_DQS7 6,9
DDR_A_D62
DDR_A_D63
DDR_EVENT# 6,9
FCH_SMDAT0 9,13,28
FCH_SMCLK0 9,13,28

+0.75VS

206

DDR3 SO-DIMM A H:5.2mm


Standard Typ

TYCO_2-2013289-1

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C46

0.1U_0402_16V4Z
2
2

DDR_A_MA15
DDR_A_MA14

1
C668

+3VS

0.1U_0402_16V4Z

1
C667
2.2U_0603_6.3V4Z

+3VS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

6,9

DDR_A_MA[0..15] 6,9

DDR_A_D12
DDR_A_D13

C44
C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_D6
DDR_A_D7

Title

Compal Electronics, Inc.


P08-DDR3 SODIMM-I Socket

Size Document Number


Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

of

47

+1.5V

+1.5V
JDIMM2

DDR_A_D8
DDR_A_D9
6,8 DDR_A_DQS#1
6,8 DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
6,8 DDR_A_DQS#2
6,8 DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

DDR_A_MA[0..15]

DDR_A_DQS#0 6,8
DDR_A_DQS0 6,8

+1.5V

6,8
2

DDR_A_D[0..63]

DDR_A_D[0..63]

DDR_A_MA[0..15] 6,8

DDR_A_DM[0..7]

R145
1K_0402_1%

DDR_A_DM[0..7] 6,8

DDR_A_D6
DDR_A_D7

R146
1K_0402_1%

15mil

15mil
1

DDR_A_D2
DDR_A_D3

+1.5V

DDR_A_D4
DDR_A_D5

+VREF_DQ

DDR_A_D12
DDR_A_D13

+VREF_CA

1000P_0402_50V7K
2

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

DDR_A_DM1

R147
1K_0402_1%

DDR_RST# 6,8
DDR_A_D14
DDR_A_D15

R148
1K_0402_1%
1

DDR_A_DM0
0.1U_0402_16V4Z
2

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

DDR_A_D0
DDR_A_D1

1
C627

1
C626

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

+VREF_DQ

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 6,8
DDR_A_DQS3 6,8
DDR_A_D30
DDR_A_D31

+1.5V
6,8

DDR_CKE0

6,8 DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
6
6

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_MA10

6,8 DDR_A_BS0
6,8 DDR_A_WE#
6,8 DDR_A_CAS#
DDR_A_MA13
6 DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
B

6,8 DDR_A_DQS#4
6,8 DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
6,8 DDR_A_DQS#6
6,8 DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7

For DRAM strap pin reservation


20100817

DDR_A_D58
DDR_A_D59
R961 1
R153 1

2 10K_0402_5%
2 10K_0402_5%

+3VS

1
1
C646

1
C647

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

CRB

only one 4.7k


5

DDR_CKE1 6,8
DDR_A_MA15
DDR_A_MA14

For DRAM strap pin reservation


20100817
4

0.1U_0402_16V4Z
2
C628

DDR_A_MA11
DDR_A_MA7

1
0.1U_0402_16V4Z

C629
1

0.1U_0402_16V4Z
2
C630

C631

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

C632

1
0.1U_0402_16V4Z

C633
1

0.1U_0402_16V4Z
2

C634

1
0.1U_0402_16V4Z

C635
1

0.1U_0402_16V4Z
2

C636

C637

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
C638

1
0.1U_0402_16V4Z

C110
1

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1 6
DDR_A_CLK#1 6
DDR_A_BS1 6,8
DDR_A_RAS# 6,8

CRB 0.1u X1

DDR_CS0_DIMMA# 6
DDR_A_ODT0 6
DDR_A_ODT1 6

4.7u X1

CRB

DDR_A_D36
DDR_A_D37

1
C645

X2

+1.5V
2
2
C640
C641
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1

1
C644

DDR_A_DM4
DDR_A_D38
DDR_A_D39

100U

+0.75VS
+VREF_CA

1000P_0402_50V7K 0.1U_0402_16V4Z
2
2

1
C642

1
+

4.7U_0603_6.3V6K
2

C1102
330U_D2E_2.5VM_R9M

DDR_A_D44
DDR_A_D45
DDR_A_DQS#5 6,8
DDR_A_DQS5 6,8

330U ESR:9m H:2


P/N:SGA20331E10

Place near JDIMM1

DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61

+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2

DDR_A_DQS#7 6,8
DDR_A_DQS7 6,8
DDR_A_D62
DDR_A_D63

C643
1

C675
1

C676
1

C678
1

DDR_EVENT# 6,8
FCH_SMDAT0 8,13,28
FCH_SMCLK0 8,13,28
+0.75VS

Compal Secret Data

Security Classification

DDR3 SO-DIMM B H:9.2mm


Standard Type

TYCO_2-2013310-1

2.2U_0603_6.3V4Z
2

R154
10K_0402_5%
0.1U_0402_16V4Z
R962
2
10K_0402_5%

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


P09-DDR3 SODIMM-II Socket

Size Document Number


Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

of

47

D1

HSYNC_L
1

2
1

VSYNC_L

YSDA0502C 3P C/A SOT-23


@
VGA_DDC_DATA_C

W=40mils

1
3

+CRT_VCC

0_0402_5%
CRT_B_R

C1573

C1574

For EMI
2

C1576

C1577

+3VS

+CRT_VCC
JCRT1

+CRT_VCC

R1648 1

2
1K_0402_5%

C1580

2
0_0603_5%

U88
74AHCT1G125GW_SOT353-5

C1583

Close to APU

5 APU_CRT_DDC_SCL

R1649
1

C1584 1

2 CRT_CLK
0_0402_5%

Q101B
CRT_DATA

R4

1 @

CRT_CLK

R31

1 @

DMN66D0LDW-7_SOT363-6

W=60mils

+LCDVDD

S
2
G

2
R1656
C1589

C9
@

R1657
10K_0402_5%

Q99B
2N7002DW-7-F_SOT363-6

26
26

DMIC_CLK
DMIC_DATA

5 APU_TXOUT25 APU_TXOUT2+
5 APU_TXCLK5 APU_TXCLK+

13
13

+3VS

Camera

USB20_N2
USB20_P2

USB20_N2
USB20_P2

W=60mils

+LCDVDD
+3VS

AZC199-02SPR7G_SOT23-3

BKOFF#

BKOFF#

For EMI, close to JLVDS1.

C122
2

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

G1
G2
G3
G4
G5

41
42
43
44
45

HONDA_LVD-A40SFYG+
CONN@

2
0_0402_5%
DISPOFF#

ESD

RB751V40_SC76-2
1

@ D5

AZC199-02SPR7G_SOT23-3

R1672 1

30

3
R1670
10K_0402_5%

@ D29

@ D30

INVTPWM
DISPOFF#

5 APU_LCD_CLK
5 APU_LCD_DATA

+3VS

@ 1
C1590

R1664
100K_0402_1%

R1662

2
0_0402_5%

APU_ENBKL

APU_ENBKL R1663

2.2K_0402_5%

R1661
100K_0402_5%

2.2K_0402_5%

R1660

30
1

ENBKL

1
INVTPWM

2
0_0402_5%

2
0_0402_5%
2
0_0402_5%

0.1U_0402_16V4Z

2N7002DW-7-F_SOT363-6
Q99A

0.047U_0402_16V7K

R1655 1

R1659 1

2
1
220K_0402_1%

R1654 1

INVT_PWM

5 APU_BLPWM
30

0.1U_0402_16V4Z

5 APU_TXOUT15 APU_TXOUT1+
22P_0402_50V8J

C1586

For EMI, close to JLVDS1.

5 APU_TXOUT05 APU_TXOUT0+

5 APU_ENVDD

C1588

W=60mils

4.7U_0805_10V4Z

1
C1585
4.7U_0805_10V4Z

0.1U_0402_16V4Z

6 2

C1587
B

1
R1653
47K_0402_5%

R1652
100_0805_5%

L119 1
B+_L
2
FBMA-L11-201209-221LMA30T_0805

B+

+3VS
Q93
SI2301BDS-T1-E3_SOT23-3

+LCDVDD

For AMD check list

LCD POWER CIRCUIT


+5VALW

VGA_DDC_CLK_C

C1582
@

VGA_DDC_DATA_C
2
0_0402_5%
VGA_DDC_CLK_C
2
0_0402_5%

680P_0402_50V7K @
1

+LCDVDD

VGA_DDC_CLK_C

CONN@

VGA_DDC_DATA_C

C1581
@

5
4

VSYNC_L

15P_0402_50V8J

0_0402_5%

R1650 1

15P_0402_50V8J

CRT_VSYNC_D

16
17

SUYIN_070546FR015S263ZR

VGA_DDC_DATA_C

Q101A
DMN66D0LDW-7_SOT363-6

5
1
2

APU_CRT_VSYNC_R

P
OE#

2.2K_0402_5%

1
1

G
G

100P_0402_50V8J

C1579
1
2
0.1U_0402_16V4Z

CRT_DATA
2
0_0402_5%

100P_0402_50V8J

5 APU_CRT_DDC_SDA

R1646

100P_0402_50V8J

R1647
1

R1645

+CRT_VCC

5 APU_CRT_VSYNC

VSYNC_L

R1642
2.2K_0402_5%

U87
74AHCT1G125GW_SOT353-5

R1644

HSYNC_L

2
0_0603_5%

R1651

HSYNC_L
BLUE

1
1
R1643 1

CRT_HSYNC_D

2.2K_0402_5%

0_0402_5%

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

T69 PAD

RED

DDC_MD2

2
1K_0402_5%

1
C1571
@

BLUE

2.2K_0402_5%

P
OE#

APU_CRT_HSYNC_R

GREEN

5
1
R1641
2

SMD1812P075TF .75A 13.2V


RB491D_SOT23-3
1
C1570

GREEN

+CRT_VCC
C1578
R1640 1
1
2
0.1U_0402_16V4Z

5 APU_CRT_HSYNC

RED

C1575
6.8P_0402_50V8J

6.8P_0402_50V8J

C1572

6.8P_0402_50V8J

150_0402_1%

R1639

150_0402_1%

R1638

1
2

R1637

150_0402_1%

0_0402_5%

W=40mils

0.1U_0402_16V4Z

R1636
1

CRT_G_R

6.8P_0402_50V8J

5 APU_CRT_B

0_0402_5%

6.8P_0402_50V8J

5 APU_CRT_G

L116
1
2
NBQ160808T-800Y-N 0603
L117
1
2
NBQ160808T-800Y-N 0603
L118
1
2
NBQ160808T-800Y-N 0603

CRT_R_R

L115
1+5VS_CRTVCC
1

ESD

R1635
1

D4

YSDA0502C 3P C/A SOT-23

YSDA0502C 3P C/A SOT-23


@

R1634
1

VOUT

AP2230_SOT23-3

VGA_DDC_CLK_C

VIN
@

+CRT_VCC

5 APU_CRT_R

Q92
1

YSDA0502C 3P C/A SOT-23


D6

D2
RED

+5VS

3
@

0.1U_0402_16V4Z

GND

BLUE
GREEN

CRT

D3

6.8P_0402_50V8J

R1677
10K_0402_5%

Compal Secret Data

Security Classification

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P10-LVDS/CRT CONN
Size
C
Date:

Compal Electronics, Inc.


Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
1

10

of

47

Q94

+5VS

Q95

LS@
APU_HDMI_CLK

R200, R201 place near JHDMI connect

SCLK

+3VS

SDATA
APU_HDMI_DATA

1
5 APU_HDMI_TX0P
5 APU_HDMI_TX0N

C1604 1
C1605 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX0
HDMI_TX0#

5 APU_HDMI_TX1P
5 APU_HDMI_TX1N

C1606 1
C1607 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX1
HDMI_TX1#

5 APU_HDMI_TX2P
5 APU_HDMI_TX2N

C1608 1
C1609 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

HDMI_TX2
HDMI_TX2#

HDMI_HPD_R#

HDMI_HPD_R

EN_HDMI
R1679
Q96
SSM3K7002FU_SC70-3

C1601 1

HDMI_CLK
HDMI_CLK#

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C1602 1
C1603 1

SI3456BDV-T1-E3 1N TSOP6

2
G

34,41 SUSP
R1701
10K_0402_5%

5 APU_HDMI_CLKP
5 APU_HDMI_CLKN

2
G

0.5A_15V_SMD1812P050TF
1
C1592

R1678

1
1U_0603_10V4Z

R205
2.2K_0402_5%

2.2K_0402_5%

1
R202

C1600

0.1U_0402_16V7K

LS@

+HDMI_5V_OUT
F2
+HDMI_5V

W=40mils

C1599

470K_0402_5%

LS@

C1598

+VSB

AP2230_SOT23-3
2

LS@

6
5
2
1

@
1
C1591

2.2K_0402_5%

C1597

R201

2
1
2.2K_0402_5%

R200

C1596
@

0.1U_0402_16V4Z

C1595
@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1594
@

10U_0805_10V4Z~D

0.1U_0402_16V4Z

C1593
@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

+HDMI_5V_OUT

+3VS

1.5M_0402_5%

+HDMI_5V_OUT
+3VS

+3VS

VOUT

1U_0603_10V6K

VIN

+5VS

GND

close to U10VCC (+3VS) pins (one Pin one Capacitor)

Q84
+HDMI_5V_OUT

SSM3K7002FU_SC70-3

5V PULL UP IN CONNECTER SIDE


JHDMI1

HDMI_HPD_R
U89

HDMI_CLK_L

1
R208

2
0_0402_5%

HDMI_R_CLK#

1
R210

2
0_0402_5%

HDMI_R_CLK

+3VS

Swap signal for layout route.

+3VS

HDMI_TX0_L

1
R211

HDMI_TX0#_L

1
R213

HDMI_R_TX0

2
0_0402_5%
2
0_0402_5%

+3VS

HDMI_R_TX0#

R1736 1

2 4.7K_0402_5%

R1685 1

2 4.7K_0402_5%

R1737 1

2 4.7K_0402_5%

R1687 1

@
2 4.7K_0402_5%
1
2
R1689
3.6K_0402_1%
APU_HDMI_HPD

5 APU_HDMI_DATA
5 APU_HDMI_CLK
+3VS

R1692

2
11
15
21
26
33
40
46

3
4
6

ANALOG1(REXT)
HPD_SOURCE

SDA_SOURCE

APU_HDMI_CLK
@
1
2 4.7K_0402_5%

SCL_SOURCE

2
4.7K_0402_5%

10

ANALOG2
OUT_D4+
OUT_D4-

HDMI_TX1_L

1
R214

2
0_0402_5%

HDMI_R_TX1

HDMI_R_CLK
HDMI_R_CLK#

13
14

HDMI_TX1#_L

1
R220

2
0_0402_5%

HDMI_R_TX1#

HDMI_R_TX2
HDMI_R_TX2#

16
17

HDMI_R_TX1
HDMI_R_TX1#

19
20

HDMI_R_TX0
HDMI_R_TX0#

22
23

Trace
1
R223

2
0_0402_5%

HDMI_R_TX2

HDMI_TX2#_L

1
R226

2
0_0402_5%

HDMI_R_TX2#

FUNCTION1
FUCNTION2

1
R1694

HDMI_TX2_L

VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V

APU_HDMI_DATA

5 APU_HDMI_HPD

OE*

25

HDMI_HPD_R#
2

HDMI_CLK#_L
C

28

SCLK

29

SDATA

HPD_SINK

30

DDC_EN

32

R1684 1 LS@
R1703 1
@

2 4.7K_0402_5%
2 4.7K_0402_5%

FUNCTION3
FUNCTION4

34
35

R1686 1
R1688 1

@
@

2 4.7K_0402_5%
2 4.7K_0402_5%

R1707 1

2 4.7K_0402_5%

R1704
100K_0402_5%
HDMI_CLK#_L
HDMI_CLK_L
HDMI_TX0#_L
HDMI_TX0_L
HDMI_TX1#_L

IN_D3+
IN_D3-

45
44

OUT_D2+
OUT_D2-

IN_D2+
IN_D2-

42
41

HDMI_TX1
HDMI_TX1#

OUT_D1+
OUT_D1-

IN_D1+
IN_D1-

39
38

HDMI_TX0
HDMI_TX0#

THERMAL_GND

49

1
R204

HDMI_TX1_L
HDMI_TX2#_L

+3VS
+3VS

HDMI_TX2_L

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

SUYIN_100042MR019S153ZL

+3VS

HDMI_CLK
HDMI_CLK#
2
2.2K_0402_5%
HDMI_TX2
HDMI_TX2#

48
47

OUT_D3+
OUT_D3-

SDATA
SCLK

HDMI_HPD_R

IN_D4+
IN_D4-

AS Short PASS
1
5
12
18
24
27
31
36
37
43

SCL_SINK
SDA_SINK

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D16
ASM1442 QFN 48P

D11

+5VS

D13

HDMI_R_TX1

1 1

10 9

HDMI_R_TX1

HDMI_R_TX2#

1 1

10 9

HDMI_R_TX2#

HDMI_R_TX1#

2 2

9 8

HDMI_R_TX1#

HDMI_R_TX2

2 2

9 8

HDMI_R_TX2

HDMI_R_TX0

4 4

7 7

HDMI_R_TX0

HDMI_R_CLK#

4 4

7 7

HDMI_R_CLK#

6 6

HDMI_R_TX0#

HDMI_R_CLK

6 6

HDMI_R_CLK

HDMI_R_TX0#

HDMI_HPD_R

5 5
3 3

5 5

+HDMI_5V_OUT

I/O4

I/O2

VDD

GND

I/O3

I/O1

SDATA

SCLK
A

AZC099-04S.R7G_SOT23-6

For ESD request.

3 3

L15ESDL5V0NA-4 SLP2510P8

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

For ESD request.


5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

L15ESDL5V0NA-4 SLP2510P8

Title

P11-HDMI CONN
Size Document Number
Custom
Date:

Rev
1.0

LA-7322P

Thursday, February 17, 2011

Sheet
1

11

of

47

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

U31E

APU_DISP_CLKP_R
APU_DISP_CLKN_R

U29
U28

R162 1
R163 1

2 0_0402_5%
2 0_0402_5%

APU_CLKP_R
APU_CLKN_R

V21
T21

17 CLK_PCIE_VGA
17 CLK_PCIE_VGA#

R569 1
R570 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R

V23
T23

25 CLK_PCIE_LAN
25 CLK_PCIE_LAN#

R571 1
R572 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

L29
L28

R573 1
R574 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R

N29
N28

T26
T27
5
5

LAN
WLAN

APU_CLKP
APU_CLKN

28 CLK_PCIE_MINI1
28 CLK_PCIE_MINI1#

M29
M28
3

NB_HT_CLKP
NB_HT_CLKN
CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N

L24
L23

GPP_CLK4P
GPP_CLK4N

P25
M25

GPP_CLK5P
GPP_CLK5N

P29
P28

GPP_CLK6P
GPP_CLK6N

N26
N27

GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N

ALLOW_LDTSTP/DMA_ACTIVE_L
PROCHOT_L
LDT_PG
LDT_STP_L
LDT_RST_L

L26

25M_CLK_X2
25MHZ_12PF_X5H025000FC1H-H

L27

25M_X1

C67
1

25M_CLK_X1

1M_0603_5%
R576

RTC

10P_0402_50V8J Y3

RTC_32KHI

R563
20M_0603_5%

1
2

C65
1

OSC

NC

OSC

NC

5
P
3

1
2

16
16
16
16
16

APU_PWRGD

H_PWRGD_L 43

FDV301N_NL_SOT23-3
Q90

U33
2 B

VGA_PWRGD

0.1U_0402_16V4Z

Y
A

@
1
R830

NC7SZ08P5X_NL_SC70-5
@
PAD T95
R595
@
1

PE_GPIO1 1
R109

2
10K_0402_5%

VGA_PWRGD_R

2
0_0402_5%

@
1
2
R838
100K_0402_5%

R839 1

20_0402_5% PE_GPIO0
PE_GPIO1
PE_GPIO1 23,30

PAD T97 1
R99

2 0_0402_5%

2
10K_0402_5% For GPIO45 leakage

RTC BATT Conn.

+RTCBATT

1
1
1
1

2
2
2
2

0_0402_5%
0_0402_5%
22_0402_5%
22_0402_5%

LPC_CLK1 16
LPC_CLK0 16
LPC_CLK0_EC 30
CLK_PCI_DB 28

JRTC1
SUYIN_060003HA002G202ZL

LPC_AD0 28,30
LPC_AD1 28,30
LPC_AD2 28,30
LPC_AD3 28,30
LPC_FRAME# 28,30
SERIRQ 30

ALLOW_STOP# 5
FCH_PROCHOT# 5
APU_PWRGD 5

+RTCBATT

APU_RST# 5

25M_X2

RTC_32KHI
RTC_32KHO

D2
B2
B1

RTC_CLK

RTCCLK
INTRUDER_ALERT_L
VDDBT_RTC_G

R179
1K_0402_5%
+RTCVCC

W=20mils

1 C1271

2
2
510_0402_5%

CLRP1
SHORT PADS

for Clear CMOS

C1270

2
@

Compal Secret Data


2010/06/30

Deciphered Date

2012/06/30

Title

+CHGRTC

DAN202UT106_SC70-3
4

Compal Electronics, Inc.


P12-FCH PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

D23

RTC_CLK 16,30
1
R864

C1272 1

Issued Date

2
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

23,41,42,44 VGA_PWRGD

C2

Security Classification

10P_0402_50V8J
A

R164
10K_0402_5%

PE_GPIO0 17

C1199
1
2

C1

RTC_32KHO

+3VS

+3VALW

32K_X2

FCH : SA000046H70 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 605P)

2
0_0402_5%

VGA_PWRGD_R

32K_X1

FCH : SA000046H60 (S IC 218-0792001 A12 HUDSON-M1 FCBGA 605P)

32.768KHZ_7PF_Q13MC1461000100

1
R585

G21
H21
K19
G22
J24

Y4

10P_0402_50V8J

+1.8VS

0.1U_0402_16V4Z

Close to FCH
2

PLT_RST# 17,25,28
2 PCIE_RST#
0_0402_5%

Need to check material?

R854
R853
H24 LPCCLK0R575
H25 LPCCLK1R577
J27
J26
H29
H28
G28
J25
AA18
AB19

12P_0402_50V8J
C64
1

@
2

AJ6
AG6
AG4
AJ4

21807-A11-HUDSON-M1_FCBGA605
4

C1233
150P_0402_50V8J

Y 4
1 A
@
1
R174
R582
8.2K_0402_5% U28
NC7SZ08P5X_NL_SC70-5

14M_25M_48M_OSC

EMI
CLK_SD_48M_RL25
2 22_0402_5%

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME_L
LDRQ0_L
LDRQ1_L/CLK_REQ6_L/GPIO49
SERIRQ/GPIO48

LPC

GPP_CLK3P
GPP_CLK3N

INTE_L/GPIO32
INTF_L/GPIO33
INTG_L/GPIO34
INTH_L/GPIO35

CPU

R655 1

NB_DISP_CLKP
NB_DISP_CLKN

T25
V25

T29
T28
C66
27 CLK_SD_48M
1
2

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

2 0_0402_5%
2 0_0402_5%

CLOCK GENERATOR

R564 1
R565 1

5 APU_DISP_CLKP
5 APU_DISP_CLKN

2 33_0402_5%

M23
P23

R175 1

close to FCH within 1"

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

0.1U_0402_16V4Z

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

A_RST#

AA22
Y21
AA25
AA24
W23
V24
W24
W25

PCIE_FRX_DTX_P0
PCIE_FRX_DTX_N0
PCIE_FRX_DTX_P1
PCIE_FRX_DTX_N1

PCIE_CALRP
PCIE_CALRN

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

C1234
1
2

AD29
AD28
PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1

+3VALW

PAD T92
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

V2

590_0402_1%
2K_0402_1%

2
2
2
2

16
16
16
16

1
1

PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

PCIE_FTX_C_DRX_P0
PCIE_FTX_C_DRX_N0
PCIE_FTX_C_DRX_P1
PCIE_FTX_C_DRX_N1

1
1
1
1

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0_L
CBE1_L
CBE2_L
CBE3_L
FRAME_L
DEVSEL_L
IRDY_L
TRDY_L
PAR
STOP_L
PERR_L
SERR_L
REQ0_L
REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41
REQ3_L/CLK_REQ5_L/GPIO42
GNT0_L
GNT1_L/GPO44
GNT2_L/GPO45
GNT3_L/CLK_REQ7_L/GPIO46
CLKRUN_L
LOCK_L

PAD T96

W2
W1
W3
W4
Y1

2
2
C61
C62
C717
C63

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

PCIRST_L

PCI I/F

25
25
28
28

R560
R561

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

25
25
28
28

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

PCIE_RST_L
A_RST_L

LAN
WLAN

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

0.1U_0402_16V4Z

+PCIE_VDDAN

UMI_RX0P_C
UMI_RX0N_C
UMI_RX1P_C
UMI_RX1N_C
UMI_RX2P_C
UMI_RX2N_C
UMI_RX3P_C
UMI_RX3N_C

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

6
6
6
6
6
6
6
6

2
2
2
2
2
2
2
2

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

1
1
1
1
1
1
1
1

P1
L1

PCI EXPRESS I/F

6
6
6
6
6
6
6
6

C53
C54
C55
C56
C57
C58
C59
C60

PCIE_RST#
A_RST#

1U_0402_6.3V4Z

A_RST#

PCI CLKS

30

Size Document Number


Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

12

of

47

+3VALW

U31A
EC_LID_OUT#
2
10K_0402_5%

1
R932

PCI_PME#
2
10K_0402_5%

PCI_PME#

MINI1_CLKREQ#
2
10K_0402_5%
NB_PWRGD
2
4.7K_0402_5%
FCH_SMCLK0
2
2.2K_0402_5%
FCH_SMDAT0
2
2.2K_0402_5%

1
R818
1
R597
1
R598
1
R599

R580 2

R579 1
@
2 10K_0402_5%
+3VALW
R627 2
25,28,30 FCH_PCIE_WAKE#
0_0402_5%
5 H_THERMTRIP#

1 0_0402_5%
25 LAN_CLKREQ#

@
@

P
G

5
@

VGATE 30,43
28 MINI1_CLKREQ#

NC7SZ08P5X_NL_SC70-5
U30 @

VRAM_SEL
2
2.2K_0402_5%
2
100K_0402_5%

VRAM_Freq : 1->900Hz
0-> 800Hz*

30 EC_LID_OUT#

VGA_CLKREQ#_R
2
10K_0402_5%
FCH_SMCLK1
2
10K_0402_5%
FCH_SMDAT1
2
10K_0402_5%
EC_RSMRST#
2
150_0402_1%
HDA_BITCLK
2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDOUT
2
10K_0402_5%

32
32

R583 1
R165 1

26 HDA_BITCLK_AUDIO
26 HDA_SDOUT_AUDIO
26 HDA_SDIN0

2 33_0402_5%
2 33_0402_5%

+3VALW

R593

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

R596

2 10K_0402_5%

R600

+3VALW +3VALW +3VALW

UMA@
VGA@ VGA@
R912
R911
R910
10K_0402_5%
10K_0402_5%
10K_0402_5%

GPIO189
GPIO190
GPIO191

T85
T86

2 10K_0402_5%

+3VALW
VGA@
UMA@ UMA@
R915
R914
R913
10K_0402_5%
10K_0402_5%
10K_0402_5%

PAD
PAD

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

GPIO187 E23
GPIO188 E24
F21
G29
GPIO189
GPIO190
GPIO191

D27
F28
F29
E27

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST_L
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST_L
GBE_PHY_INTR

GBE LAN

M3
N1
L2
M2
M1
M4
N2
P2

USB_FSD0P/GPIO185
USB_FSD0N

H9
J8

USB_HSD13P
USB_HSD13N

B12
A12

USB_HSD12P
USB_HSD12N

F11
E11

USB_HSD11P
USB_HSD11N

E14
E12

USB_HSD8P
USB_HSD8N

BLINK/USB_OC7_L/GEVENT18_L
USB_OC6_L/IR_TX1/GEVENT6_L
USB_OC5_L/IR_TX0/GEVENT17_L
USB_OC4_L/IR_RX0/GEVENT16_L
USB_OC3_L/AC_PRES/TDO/GEVENT15_L
USB_OC2_L/TCK/GEVENT14_L
USB_OC1_L/TDI/GEVENT13_L
USB_OC0_L/TRST_L/GEVENT12_L

PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2_L/GBE_STAT2/GPIO166
FC_RST_L/GPO160

R578
G19

J10
H11

USB_HSD9P
USB_HSD9N

USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N

USB_RCOMP 1

2
11.8K_0402_1%

USB_HSD[13:0]P/N:
USB P/N pairs with trace lengths up to
10" and have a decoupling 5.6-pF capacitor
footprint placed near the USB connector or device.

Root

J12
J14
A13
B13
D13
C13
G12
G14

Root
EHCI CTL
DEV 19, Fn 2

G16
G18

USB_HSD5P
USB_HSD5N

D16
C16

USB20_P5 26
USB20_N5 26

USB_HSD4P
USB_HSD4N

B14
A14

USB20_P4 27
USB20_N4 27

USB_HSD3P
USB_HSD3N

E18
E16

USB20_P3 28
USB20_N3 28

USB_HSD2P
USB_HSD2N

J16
J18

USB20_P2 10
USB20_N2 10

USB_HSD1P
USB_HSD1N

B17
A17

USB20_P1 32
USB20_N1 32

A16
B16

USB20_P0 32
USB20_N0 32

USB_HSD0P
USB_HSD0N

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

R5911
R5921

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

2 33_0402_5% HDA_SYNC
2 33_0402_5% HDA_RST#

R589 1
R590 1

26 HDA_SYNC_AUDIO
26 HDA_RST_AUDIO#

Pull-down for enable high performance mode


20100527 (required for M1)

USB_OC1#

USB_OC1#
USB_OC0#

H3
D1
E4
D4
E8
F7
E7
F8

A10

USB_FSD1P/GPIO186
USB_FSD1N

USB_HSD10P
USB_HSD10N

CLK_REQ4_L/SATA_IS0_L/GPIO64
CLK_REQ3_L/SATA_IS1_L/GPIO63
SMARTVOLT1/SATA_IS2_L/GPIO50
CLK_REQ0_L/SATA_IS3_L/GPIO60
SATA_IS4_L/FANOUT3/GPIO55
SATA_IS5_L/FANIN3/GPIO59
SPKR_GPIO66
SCL0_GPIO43
SDA0_GPIO47
SCL1_GPIO227
SDA1_GPIO228
CLK_REQ2_L/FANIN4_GPIO62
CLK_REQ1_L/FANOUT4_GPIO61
IR_LED_L/LLB_L/GPIO184
SMARTVOLT2/SHUTDOWN_L/GPIO51
DDR3_RST_L/GEVENT7_L
GBE_LED0/GPIO183
GBE_LED1/GEVENT9_L
GBE_LED2/GEVENT10_L
GBE_STAT0/GEVENT11_L
CLK_REQG_L/GPIO65_OSCIN

HD AUDIO

1
R173
1
R587
1
R588
1
R606
1
R607
1
R608
1
R609

EC_PWROK 30

RSMRST_L

USB OC

1
R626
1
R404

+3VS

USB_RCOMP

USB 2.0

8,9,28 FCH_SMCLK0
8,9,28 FCH_SMDAT0

AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
FCH_SMCLK1
F5
FCH_SMDAT1
F4
AH21
AB18
E1
AJ21
H4
VRAM_SEL
D5
D7
G5
K3
VGA_CLKREQ#_R AA20

USBCLK/14M_25M_48M_OSC

10mils and <1"

GPIO

@
C112
0.1U_0402_16V7K

G1

30 EC_RSMRST#

+3VS @
C111 0.1U_0402_16V7K
1
2

43 FCH_PWROK

30
30
30
30

T82
T83
T84
EC_GA20
EC_KBRST#
EC_SCI#
EC_SMI#

1 0_0402_5%

R581 2

SLP_S3#
SLP_S5#
PBTN_OUT#

PCI_PME_L/GEVENT4_L
RI_L/GEVENT22_L
SPI_CS3_L/GBE_STAT1/GEVENT21_L
SLP_S3_L
SLP_S5_L
PWR_BTN_L
PWR_GOOD
SUS_STAT_L
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0_L
KBRST_L/GEVENT1_L
LPC_PME_L/GEVENT3_L
LPC_SMI_L/GEVENT23_L
GEVENT5_L
SYS_RESET_L/GEVENT19_L
WAKE_L/GEVENT8_L
IR_RX1/GEVENT20_L
THRMTRIP_L/SMBALERT_L/GEVENT2_L
NB_PWRGD

USB 1.1

+3VS

30
30
30

J2
K1
D3
F1
H1
F2
FCH_PWROK H5
G6
B3
PAD
C4
PAD
F6
PAD
AD21
AE21
K2
J29
H2
J1
1FCH_PCIE_WAKE_R# H6
F3
J6
NB_PWRGD
AC19

USB MISC

1
R930

ACPI/WAKE UP EVENTS

USB_OC1#
2
10K_0402_5%
USB_OC0#
2
10K_0402_5%
FCH_SIC
2
10K_0402_5%
FCH_SID
2
10K_0402_5%
FCH_PCIE_WAKE_R#
2
10K_0402_5%
LAN_CLKREQ#
2
10K_0402_5%

1
R871
1
R872
1
R603
1
R604
1
R605
1
R817

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

D25
F23
B26
E26
F25
E22
F22
E21

GPIO193
GPIO194

R584 2
R586 2

USB3
CardReder
WLAN(BT)
CMOS
USB2
USB1

Root
EHCI CTL
DEV 18, Fn 2

1 10K_0402_5%
1 10K_0402_5%
FCH_SIC 5
FCH_SID 5

EC_PWM2
EC_PWM3

EC_PWM2 16
EC_PWM3 16

G24
G25
E28
E29
D29
D28
C29
C28

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
21807-A11-HUDSON-M1_FCBGA605

SKU_ID
(GPIO189)

SKU_ID : 1->VGA*
0->UMA

PX_FN
(GPIO190)

PX_Function : 1->PX Enable*


0->PX Disable

PX_SEL
(GPIO191)

PX_SEL : 1->PX 3.0*


0->PX 4.0

GPIO

189

190

191

UMA
DISO
PX3.0
PX4.0

0
1
1
1

0
0
1
1

1
1
1
0

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

P13-FCH HDA/USB/ACPI
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

13

of

47

U31B

HDD

C656
C658

29 SATA_ITX_DRX_P0
29 SATA_ITX_DRX_N0

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

SATA_ITX_C_DRX_P0 AH9
SATA_ITX_C_DRX_N0 AJ9
AJ8
AH8

29 SATA_DTX_C_IRX_N0
29 SATA_DTX_C_IRX_P0

ODD

C648
C649

29 SATA_ITX_DRX_P1
29 SATA_ITX_DRX_N1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

SATA_ITX_C_DRX_P1 AH10
SATA_ITX_C_DRX_N1 AJ10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

AJ17
AH17

AH19
AJ19

10 mils and < 1"


R610
R611

28

SATA_CALRP
SATA_CALRN

2 1K_0402_1%
2 931_0402_1%

1
1

AB14
AA14
AD11

SATA_LED#
R616 1

+3VS

25M_SATA_X1 AD16

22P_0402_50V8J

SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
SATA_CALRP
SATA_CALRN

@C106

25M_SATA_X2 AC16

SATA_X2

22P_0402_50V8J

FCH_SI_SPI_SO
FCH_SO_SPI_SI
FCH_SPICLK R510 1
FCH_SPICS#/FSEL#

EMI

J5
E2
2FCH_SPICLK_RR K4
0_0402_5%
K9
G2
T78PAD

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1_L/GPIO165
ROM_RST_L/GPIO161

SPI ROM

25MHZ_20PF_7A25000012

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

SATA_X1

1M_0603_5%
R861

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174
TEMP_COMM

SATA_ACT_L/GPIO67

@
Y7

SATA_RX4N
SATA_RX4P

2 10K_0402_5%
@

@C107
1

SATA_TX4P
SATA_TX4N

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

HW MONITOR

AJ18
AH18

FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146
FC_WE_L/GPIOD148
FC_CE1_L/GPIOD149
FC_CE2_L/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

SATA_TX1P
SATA_TX1N

AG10
AF10

AG17
AF17

+AVDD_SATA

SATA_RX0N
SATA_RX0P

SERIAL ATA

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

GPIOD

29 SATA_DTX_C_IRX_N1
29 SATA_DTX_C_IRX_P1

SATA_TX0P
SATA_TX0N

NC1
NC2

AH28
AG28
AF26
AF28
AG29
AG26
AF27
AE29
AF29
AH27
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

W5
W6
Y9

BT_ON

W7
V9
W8

28

WL_OFF# 28

B6
A6
A5
B5
C7

TEMPIN0 R612 2
TEMPIN1 R613 2
TEMPIN2 R614 2
R615 2

1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

A3
B4
A4
C5
A7
B7
B8
A8

GPIO175
GPIO176
GPIO177
GPIO178
GPIO179
GPIO180
GPIO181
GPIO182

1
1
1
1
1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R617
R618
R619
R620
R621
R622
R623
R624

2
2
2
2
2
2
2
2

VIN6/GBE_STAT3/GPIO181
Enable integrated pull-down/up and leave unconnected

G27
Y2
+3VALW
+3V_SPI
U11

21807-A11-HUDSON-M1_FCBGA605

1
4
9
19

+3VALW

30,31
30,31
30,31
30,31

@
+3V_SPI

1
R504

2
0_0603_5%

C784 1

2 0.1U_0402_16V4Z

FCH_+SPI_VCC

@
@
C785
1 R511
2
1
2
0_0402_5%
0.1U_0402_16V4Z

U32 @

+3V_SPI

R507 1
R491 1

@
@

FCH_SPICS#/FSEL#_R
2 4.7K_0402_5% FCH_SPI_WP#
2 4.7K_0402_5%FCH_SPI_HOLD#

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

EMI

KSI4
KSI5
KSI6
KSI7
+3VALW

FCH_SPICLK_R
FCH_SO_SPI_SI_R
FCH_SI_SPI_SO_R

24
22
18
17
14

KSI4
KSI5
KSI6
KSI7

23
21
16
15
13

FCH_SPICS#/FSEL#
FCH_SPICLK
FCH_SO_SPI_SI
FCH_SI_SPI_SO

VDD
VDD
VDD
VDD

SEL
YA
YB
YC

A0
B0
C0
D0
E0
A1
B1
C1
D1
E1

YD
YE
GND
GND
GND
GND

12

EC_ON

2
5
6

FCH_SPICS#/FSEL#_R
FCH_SPICLK_R

8
11

EC_ON

30,33

FCH_SO_SPI_SI_R
FCH_SI_SPI_SO_R

3
7
10
20
4

PI3V512QE_QSOP24
@

MX25L1606EM2I-12G_SO8
SA000041N00

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

P14-FCH-SATA/SPI
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

14

of

47

PLL

0.1U_0402_16V7K

C94

C93

2.2U_0603_6.3V6K

FBMA-L11-160808-221LMT_2P

+VDDAN_11_USB

C11
D11

88.6mA

A21
D21
B21
K10
L10
J9
T6
T8

VDDCR_11_S_1
VDDCR_11_S_2

F26
G26

VDDPL_33_USB_S

L48
2

+1.1VALW

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

VDDPL_33_SYS

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

VDDAN_33_HWM_S
VDDXL_33_S

+VDDPL11

+VDDIO_AZ

58mA

C99

C776

C775

C778

C68

10U_0603_6.3V6M

10U_0603_6.3V6M

C109

10U_0603_6.3V6M

C743

C75

1U_0402_6.3V6K

330U_D2_2.5VY_R9M

10U_0603_6.3V6M

C71

C118

1U_0402_6.3V6K

1U_0402_6.3V6K

C117
C74

1U_0402_6.3V6K

0.1U_0402_16V7K

F19

FB

1U_0402_6.3V6K
1
2

C989
@
2

Reserve
+1.1VALW

+VDDAN33_HWM
+VDDXL_33_S

L20

GND

L47
2
1
FBMA-L11-201209-221LMA30T_0805

+1.1VALW

+AVDD_USB

11.4mA

D6

VIN
VOUT

APL5317

+VDDPL11

16.1mA

@
U85

EN

+VDDPL33

65.3mA

L22

+3VALW

46.5mA

M21

5mA

0.1U_0402_16V7K

0.1U_0402_16V7K

+VDDCR_11_USB @
L107
2
1
5
FBMA-L11-160808-221LMT 0603

+VDDCR_11_USB

L49
2

+3VS

FBMA-L11-160808-221LMT_2P

+VDDIO_AZ

+3VALW
@
1
R634
1
R635

2
0_0603_5%
2
0_0603_5%

+3VS

C98
2.2U_0603_6.3V6K

For 3V AZ device

+VDDAN33_HWM
+3VALW

L53
2
1
FBMA-L11-160808-221LMT_2P

2 2.2U_0603_6.3V6K
C100

2
+VDDPL33

C782

L52
2
1
FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

+1.1VALW

1U_0402_6.3V6K

C97

1U_0402_6.3V6K

C96

10U_0603_6.3V6M

2 2.2U_0603_6.3V6K

+1.1VS

0.1U_0402_16V7K

C777 1

C108

2
1
FBMA-L11-160808-221LMT_2P

L50
2
1
FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V7K

C119

15.3mA

A11
B11

10U_0603_6.3V6M

+3VS

+1.1VS

C70

165.2mA

M8

21807-A11-HUDSON-M1_FCBGA605

+AVDD_SATA
+VDDPL_33_SATA

C73

49.5mA

L51

+3VALW

C92

M6
P8

VDDPL_11_SYS_S

L43 2

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

VDDIO_GBE_S_1
VDDIO_GBE_S_2

VDDIO_AZ_S

+
2

M10

L7
L9

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

+1.1VS

C91

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

+1.1VS

0.1U_0402_16V7K

C89

C88

0.1U_0402_16V7K

1U_0402_6.3V6K

C87

1U_0402_6.3V6K

10U_0603_6.3V6M

C86

C85

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

USB I/O

534.5mA

0.1U_0402_16V7K

+AVDD_USB

1
10U_0603_6.3V6M

FBMA-L11-201209-221LMA30T_0805

C90

CORE S5

L46

C82

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

2.2U_0603_6.3V6K

VDDPL_33_SATA

V1

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

3.3V_S5 I/O

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

SERIAL ATA

+VDDPL_33_SATA AD14

1345.2mA

+3VALW

C84

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

15.5mA
+AVDD_SATA

U26
V22
V26
V27
V28
V29
W22
W26

1U_0402_6.3V6K

+PCIE_VDDAN

C81

1115.6mA

VDDPL_33_PCIE

382.9mA

+VDDAN_11_CLK

K28
K29
J28
K26
J21
J20
K21
J22

C83

AE28

2.2U_0603_6.3V6K

+VDDPL33_PCIE

VDDIO_33_GBE_S

1U_0402_6.3V6K

C80

C79

VDDRF_GBE_S

22.5mA

979.4mA

2.2U_0603_6.3V6K

0.1U_0402_16V7K

1U_0402_6.3V6K

C78

C105

10U_0603_6.3V6M

2
1
FBMA-L11-201209-221LMA30T_0805

C77

L45

10U_0603_6.3V6M

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

N13
R15
N17
U13
U17
V12
V18
W12
W18

C95

C76

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

GBE LAN

2
1
FBMA-L11-160808-221LMT_2P

+3VS

AF22
AE25
AF24
AC22

PCI EXPRESS

L44

0.16mA

0.1U_0402_16V7K

2.2U_0603_6.3V6K

0.1U_0402_16V7K

C746

C69

0.1U_0402_16V7K

4.7U_0603_6.3V6K

C744

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

C738

0.1U_0402_16V7K

C116

0.1U_0402_16V7K

C114

C115

0.1U_0402_16V7K

10U_0603_6.3V6M

C113
1
R633
2

FLASH I/O

0_0603_5%

+1.1VS

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

+VDDIO_18_FC

0_0402_5%

C121

10U_0603_6.3V6M

AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

CLKGEN I/O

GPIO I/F implemented: tied to +1.8V_S0


GPIO I/F not implemented: tied to
+1.8V_S0 or 0 ohm to ground

R632

+1.8VS

CORE S0

PCI/GPIO I/O

POWER

U31C

42mA
2

C72

+3VS

0.1U_0402_16V7K

0.1U_0402_16V7K

L55
+3VS

2
1
FBMA-L11-160808-221LMT_2P
C120 1

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2 2.2U_0603_6.3V6K

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

P15-FCH PWR
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

15

of

47

U31D

VSSXL

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

PCI_CLK3

PCI_CLK4

LPC_CLK0 LPC_CLK1

WATCHDOG
TIMER
ENABLE

ALLOW PCIE
GEN2

USE
DEBUG
STRAP

NON Fusion
CLOCK
Mode

internal EC
ENABLE

VSSPL_SYS

RTC_CLK

Internal
CLKGEN
Mode

EC_PWM2 EC_PWM3
LPC ROM (H.L)

S5 PLUS
MODE
DISABLED

DEFAULT

DEFAULT
DEFAULT

WATCHDOG
TIMER
DISABLE

PULL
LOW

FORCE PCIE
GEN1

IGNORE
DEBUG
STRAP

Fusion
CLOCK
Mode

internal EC
DISABLE

DEFAULT

DEFAULT

DEFAULT

External
CLKGEN
Mode

S5 PLUS
MODE
ENABLED

SPI ROM(L,H)
*

DEFAULT

+3VALW

+3VALW

+3VALW

+3VALW

+3VALW

+3VS

+3VS

+3VS

+3VS

PCI_CLK2
PCI_CLK1
PCI_CLK3
PCI_CLK4
LPC_CLK0
LPC_CLK1
EC_PWM2
EC_PWM3
RTC_CLK

12
12
12
12
12
12
13
13
12,30

R649
R636
R637
R638
R639
R166
R594
R550
R551
@
@
@
@
@
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R640
R641
R642
R643
R167
R601
R602
R625
@
@
@
@
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2

R650

VSSAN_HWM

PCI_CLK1

D8
M19

Check Internal PU/PD

EFUSE

PULL
HIGH

PCI_CLK2

Y4

REQUIRED STRAPS

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

GND

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

M20

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

DEBUG STRAPS
FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

DEFAULT

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

21807-A11-HUDSON-M1_FCBGA605

BYPASS
PCI PLL

ILA
AUTORUN
Enabled

Check AD29,AD28 strap function

Getting Value
from I2C EPROM

check default

2010/06/30

Deciphered Date

Compal Electronics, Inc.


2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

R644
R645
R646
R647
R648
@
@
@
@
@
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

Reserved

Compal Secret Data

Security Classification
Issued Date

FC PLL
bypassed

PULL
LOW

DEFAULT

DEFAULT

12
12
12
12
12

DEFAULT

Required Setting

Disable I2C
ROM

ILA AUTORUN Selects


Disabled
FC PLL

DEFAULT

PCI_AD23
Enable ROM Straps

PCI_AD24

USE internal
PLL generated
PLL CLK

PCI_AD25

PULL
HIGH

PCI_AD26

PCI_AD27

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

P16-FCH-VSS/Strap
Size
B
Date:

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
1

16

of

47

GFX PCIE LANE REVERSAL


U2G

U2A

6 PCIE_FTX_C_GRX_P[0..3]
6 PCIE_FTX_C_GRX_N[0..3]

PCIE_FTX_C_GRX_P[0..3]

PCIE_GTX_C_FRX_P[0..3]

PCIE_FTX_C_GRX_N[0..3]

PCIE_GTX_C_FRX_N[0..3]

PCIE_GTX_C_FRX_P[0..3] 6
LVDS CONTROL

PCIE_GTX_C_FRX_N[0..3] 6

AA38
Y37

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

Y33
Y32

PCIE_GTX_FRX_P0
PCIE_GTX_FRX_N0

C1
C2

1
1

2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P0


2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N0

PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1

Y35
W36

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W33
W32

PCIE_GTX_FRX_P1
PCIE_GTX_FRX_N1

C3
C4

1
1

2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P1


2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N1

PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2

W38
V37

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33
U32

PCIE_GTX_FRX_P2
PCIE_GTX_FRX_N2

C5
C6

1
1

2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P2


2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N2

PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3

V35
U36

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30
U29

PCIE_GTX_FRX_P3
PCIE_GTX_FRX_N3

C7
C8

1
1

2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P3


2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N3

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

T33
T32

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

T30
T29

R38
P37

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

P33
P32

P35
N36
N38
M37

PCIE_RX8P
PCIE_RX8N

M35
L36

PCIE_RX9P
PCIE_RX9N

L38
K37
K35
J36
J38
H37
H35
G36
B

PCIE_RX7P
PCIE_RX7N

G38
F37
F35
E37

PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0

PCIE_TX7P
PCIE_TX7N

P30
P29

PCIE_TX8P
PCIE_TX8N

N33
N32

PCIE_TX9P
PCIE_TX9N

N30
N29

PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

VARY_BL
DIGON

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AK27
AJ27

R1
R2

1 VGA@ 2 10K_0402_5%
1 VGA@ 2 10K_0402_5%

AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37

TXOUT_U3P
TXOUT_U3N

AF35
AG36

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

LVTMDP

TXOUT_L3P
TXOUT_L3N

AN36
AP37

2160809000A11SEYMOU_FCBGA962

VGA@

L33
L32
L30
L29
K33
K32
J33
J32

K30
K29
H33
H32
+3VSG

CLOCK
PCIE_REFCLKP
PCIE_REFCLKN

1
Y29

R6 1 VGA@ 2 2K_0402_1%

R3 1 VGA@ 2 1.27K_0402_1%
PE_GPIO0

12,25,28 PLT_RST#

+1.0VSG

12

U16
VGA@
4 VGA_RST#

Y
A

PERSTB
3

AA30

PCIE_CALRN

Y30

PCIE_CALRP

2 VGA@ 1
AH16
R5
10K_0402_5% PWRGOOD
VGA_RST#

R394
2.2K_0402_5%
@

CALIBRATION

AB35
AA36

12 CLK_PCIE_VGA
12 CLK_PCIE_VGA#

AH16
Accessiable for "Test Purposes"
Connect to GND for "Normal Operation"

NC7SZ08P5X_NL_SC70-5

2160809000A11SEYMOU_FCBGA962

VGA@
R554

Seymour XT P/N: SA000047H10 (S IC 216-0809000 A11 SEYMOUR XT M2)

0_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

P17-Vancouver_ PCIE / LVDS


Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

17

of

47

U2B

External VGA Thermal Sensor

CONFIG[2]
CONFIG[1]
CONFIG[0]

GPIO13,12,11 (config 2,1,0) :


a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.

GPIO13
GPIO12
GPIO11

BIOS_ROM_EN

b) If BIOS_ROM_EN = 0, then Config[2:0] defines


the primary memory aperture size.

GPIO22

AUD[1]
AUD(0)

memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010

Enable external BIOS ROM device


0: Diable, 1: Enable

GPIO2

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

001

00: No audio function;


10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software

HSYNC
VSYNC

BIF_GEN2_EN

00

H2SYNC
Internal use only. THIS PAD HAS AN INTERNAL
(GENLK_CLK) PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected
GPIO8
GPIO21
GENERICC
GPIO5

DNI

+3VSG

+3VSG
VGA@ R11
VGA@ R13
VGA@ R15
@ R16
@ R17
VGA@ R18
@ R19
@ R20
@ R21
@ R22
@ R23
@ R24
@ R25
@ R26
@ R27
@ R28

AJ21
AK21

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
SOUT_GPIO8
SIN_GPIO9
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
HSYNC
VSYNC
GENERICC
V2SYNC
H2SYNC
BB_EN_GPIO21
ROMSE_GPIO22
VGA_GPIO5

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R12
R14

Hynix
SA000041S60 64M16
H5TQ1G63DFR-11C

Hynix
SA00003YO30 128M16
H5TQ2G63BFR-11C

T1

GPU_VID1
BB_EN_GPIO21
ROMSE_GPIO22

GPU_VID1
T2
T3
T4
T5
T6
T7

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

THM_ALERT#

44

1
GENERICC

2
VGA@

2
1

2
1

2
1
2

1
2
1
2

HOLD
W
VCC

VSS

2
VGA@

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
NC_GENERICF_HPD5
NC_GENERICG_HPD6

2
VGA@

1
R49
1
R50

XTALOUT

HSYNC
VSYNC
RSET

70mA
45mA

AVDD
AVSSQ
VDD1DI
VSS1DI
R2/NC
R2B/NC
G2/NC
G2B/NC
B2/NC
B2B/NC

C/NC
Y/NC
COMP/NC

AF29
AG29

GND

OUT

IN

GND

27MHZ_16PF_X7S027000BG1H-U
VGA@
1
VGA@ C35
18P_0402_50V8

120ohm/0.3A

2
VGA@

C36
VGA@
18P_0402_50V8

10mil

+TSVDD
1

2
VGA@

2
VGA@

C34
0.1U_0402_16V4Z

C33
1U_0402_6.3V4Z

2
20P_0402_50V8
@

AK32
AL31

L5
BLM18AG121SN1D_0603
2
1
VGA@
1

Y1

AV33
AU34

AJ32
AJ33

H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

100mAVDD2DI/NC

1
R8

1
Q1A

EC_SMB_CK2

EC_SMB_CK2

5,30

EC_SMB_DA2
6
VGA@
DMN66D0LDW-7_SOT363-6

EC_SMB_DA2

5,30

AU22
AV21
AT23
AR22

AF37
AE38
AC36
AC38

HSYNC
VSYNC

AB34

R30

AD34
AE34

+AVDD

AC33
AC34

+VDD1DI

1 VGA@

10mil

2
VGA@

AF30
AF31

AC32
AD32
AF32

2
VGA@

AD29
AC29
AG31
AG32

AD33

H2SYNC
V2SYNC
+VDD1DI

DDC1CLK
DDC1DATA

DDC2CLK
DDC2DATA
XO_IN
AUX2P
AUX2N

XO_IN2

NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

TS_FDO
DDC6CLK
DDC6DATA

TS_A/NC

NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

2160809000A11SEYMOU_FCBGA962

10mil
10mil

2
VGA@

10mil

AA29

R48
715_0402_1%
1
2
VGA@

L78
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@

120ohm/0.3A

2
VGA@
L79
BLM18AG121SN1D_0603
2
1
+1.8VSG
VGA@

120ohm/0.3A

NC on Whistler and Seymour

2
VGA@

2
VGA@

+3VSG

In Whistler and Seymour, change to


GENLK_CLK, GENLK_VSYNC for
Global Swap Lock on multiple GPUs

VGA@
1

VGA@
1

+1.8VSG

Except A2VSSQ change to TSVSSQ,


others are NC on Whistler and Seymour

AM26
AN26
AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30
AL29
AM29

NC on Park,
Robson and Seymour

AN21
AM21
A

AJ30
AJ31
AK30
AK29

Issued Date

2
VGA@

VGA@
1

NC on Park,
Robson and Seymour

Compal Electronics, Inc.

Compal Secret Data

Security Classification

VGA@

2
VGA@

2
VGA@

2
VGA@

AF33

AUX1P
AUX1N

XTALIN
XTALOUT

20mA

499_0402_1%

AD30
AD31

75mA

THERMAL

10mil

AC30
AC31

2mAA2VDDQ/NC

PLL/CLOCK
DPLL_VDDC

DPLUS
DMINUS

AE36
AD35

AG33

R2SET/NC
DPLL_PVDD
DPLL_PVSS

AD39
AD37

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

+3VSG

Q1B VGA@
DMN66D0LDW-7_SOT363-6

Title

P18-Vancouver_Strap/DP/HDMI//CRT
Size
Document Number
Custom

Rev
1.0

LA-7322P

Date:
5

2
4.7K_0402_5%
VGA@

VGA_SMB_DA2

130mAA2VDD/NC
VREFG

TSVDD
TSVSS

THM_ALERT#

1
0_0402_5%

GND

R10
4.7K_0402_5%
VGA@

AT21
AR20

DAC2

DDCCLK_AUX3P
DDCDATA_AUX3N

AL31 Manhattan/Vancouver is NC, Boardway is


ADC input(0-1V) use measure regulator current or temperature

1M_0603_5%

C32
10U_0603_6.3V6M

For EMI

B
BB

DAC1

DDC/AUX
AN31

2
AW34
0_0402_5%
2
AW35
0_0402_5%

GPU_THERM_D+
GPU_THERM_D-

R75
VGA@
27MCLK

27MCLK
XTALOUT

+1.8VSG
R74
0_0402_5%
CLK_GPIO10 2
@
1
1
C123

HPD1

G
GB

125mA

+DPLL_VDDC

M25P10-AVMN6P
C31
@
0.1U_0402_16V4Z

10mil

VGA_SMB_DA2
R7 2

C23
10U_0603_6.3V6M

TYPE 1

2
VGA@

THERM#

AU20
AT19

C20
10U_0603_6.3V6M

@
A

470ohm/1A

2
VGA@

AM32
AN32

VGA_SMB_CK2

AT17
AR16

C24
0.1U_0402_16V4Z

+1.0VSG
L4
BLM18AG121SN1D_0603
2
1
VGA@

SOUT_GPIO8

2
VGA@

C27
1U_0402_6.3V4Z

@
2
1
R52
0_0402_5% 2

AH13

ALERT#

Not share via for other GND


R
RB

A2VSSQ/TSVSSQ

+DPLL_PVDD

C30
1U_0402_6.3V4Z

7
R51
0_0402_5%
@
2
1

NC_TX4P_DPD1P
NC_TX4M_DPD1N

10mil

470ohm/1A

C
S

+VGA_VREF

AU16
AV15

C22
1U_0402_6.3V4Z

L3
BLM18AG121SN1D_0603
2
1
VGA@
1

C26
0.1U_0402_16V4Z

DPD

NC_TX5P_DPD0P
NC_TX5M_DPD0N

15mil

2 VGA@
0.1U_0402_16V4Z

+1.8VSG

C29
0.1U_0402_16V4Z

ROMSE_GPIO22

2 249_0402_1%

C28
10U_0603_6.3V6M

+3VSG

CLK_GPIO10

2 499_0402_1%

1 VGA@
C21

1 VGA@

R43

C25
10U_0603_6.3V6M

R42

PD-Reset

U5
5

NC_TX3P_DPD2P
NC_TX3M_DPD2N

VSS2DI/NC
+1.8VSG

Internal PD

FLASH ROM
SIN_GPIO9

NC_TXCDP_DPD3P
NC_TXCDM_DPD3N

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

R9
4.7K_0402_5%
VGA@

C19
0.1U_0402_16V4Z

AK24

R47
10K_0402_5%

R46
10K_0402_5%

R45
10K_0402_5%

R44
10K_0402_5%

R41
10K_0402_5%

R40
10K_0402_5%

R39
10K_0402_5%

R38
10K_0402_5%
@

TX2P_DPC0P
TX2M_DPC0N

D-

+3VSG

AT15
AR14

C18
1U_0402_6.3V4Z

+1.8VSG

TX1P_DPC1P
TX1M_DPC1N

SCL
SDA

DPC

SDATA

VGA_SMB_CK2

SCLK

D+

+3VSG

AU14
AV13

C52
10U_0603_6.3V6M

TX0P_DPC2P
TX0M_DPC2N

VDD

Address 1001 101X b

AT33
AU32

C17
10U_0603_6.3V6M

TXCCP_DPC3P
TXCCM_DPC3N

ADM1032ARMZ-2REEL_MSOP8

AR32
AT31

C14
10U_0603_6.3V6M

TX5P_DPB0P
TX5M_DPB0N

AV31
AU30

C16
0.1U_0402_16V4Z

Samsung
SA000047QA0 128M16
K4W2G1646C-HC11

VGA_ENBKL
SOUT_GPIO8
SIN_GPIO9

GPU_VID0

GPU_VID0

TX4P_DPB1P
TX4M_DPB1N

AR30
AT29

C15
1U_0402_6.3V4Z

DPB

U4 VGA@
1

GPU_THERM_D+
2200P_0402_50V7K
VGA@ 1
2
C11
GPU_THERM_D-

C12
1U_0402_6.3V4Z

TX3P_DPB2P
TX3M_DPB2N

AT27
AR26

C13
0.1U_0402_16V4Z

For EMI
44

TXCBP_DPB3P
TXCBM_DPB3N

I2C

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

VGA_GPIO5
1
R29
VGA@
10K_0402_5%
CLK_GPIO10 2
1
R53
@ 0_0402_5%

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2

Samsung
SA00004GS30 64M16
K4W1G1646G-BC11

TX2P_DPA0P
TX2M_DPA0N

GENERAL PURPOSE I/O

GPIO_0 will use to control


PSI in the future product

Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0

SWAPLOCKA
SWAPLOCKB

2 4.7K_0402_5%
2 4.7K_0402_5%
AK26
AJ26

Robson (XT)/Seymour(XT)

VRAM

1 VGA@
1 VGA@

NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
NC_DVPCNTL_0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
NC_DVPDATA_17
NC_DVPDATA_18
NC_DVPDATA_19
NC_DVPDATA_20
NC_DVPDATA_21
NC_DVPDATA_22
NC_DVPDATA_23

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

1
C10
VGA@

AU26
AV25

PCI Express Transmitter De-emphasis Enable


0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

GPIO1

TX1P_DPA1P
TX1M_DPA1N

AT25
AR24

TX_DEEMPH_EN

DPA

Transmitter Power Saving Enable


0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

GPIO0

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

+3VSG

AU24
AV23

TX_PWRS_ENB

TXCAP_DPA3P
TXCAM_DPA3N

0.1U_0402_16V4Z

VGA Disable determines


0: VGA Controller capacity enabled
1: The device will not be recognized as the systems VGA controller

GPIO9

VGA_DIS

RESERVED

Setting

Pin Straps description <all internal PD>

Strap Name

Thursday, February 17, 2011


1

Sheet

18

of

47

Robson,Seymour only support single channel


memory (channel B only)
D

D
U2D

DDR2
GDDR3/GDDR5
DDR3

MVREFDA
MVREFSA

+1.5VSG

NC_CASA0B
NC_CASA1B

K20
K17

NC_CSA0B_0
NC_CSA0B_1

K24
K27

NC_CSA1B_0
NC_CSA1B_1

M13
K16

NC_CKEA0
NC_CKEA1

K21
J20

1
K23
K19

NC_MVREFDA
NC_MVREFSA

NC_RASA0B
NC_RASA1B

L18
L20

J14
H14

VGA@

+1.5VSG

R60
VGA@
40.2_0402_1%

R61
VGA@
100_0402_1%

MVREFSB
1

C40
VGA@

NC_WEA0B
NC_WEA1B

K26
L15

R66
R67
R69

2 VGA@
2 VGA@
2 VGA@

1 243_0402_1% M12
1 243_0402_1% M27
1 243_0402_1% AH12

MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2

NC_MAA0_8
NC_MAA1_8

H23
J19

TESTEN
2 VGA@ 1
R65
5.11K_0402_1%
TEST_MCLK
TEST_YCLK
C41
@
0.1U_0402_16V4Z

GDDR5

NC_MEM_CALRN0
MEM_CALRN1
NC_MEM_CALRN2

2160809000A11SEYMOU_FCBGA962

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

ADBIB0/ODTB0
ADBIB1/ODTB1

AD28

TESTEN

AK10
AL10

CLKTESTA
CLKTESTB

DQMB#[0..7]

QSB[0..7]

L9
L8

CLKB0
CLKB0#

CLKB1
CLKB1B

AD8
AD7

CLKB1
CLKB1#

RASB0B
RASB1B

T10
Y10

RASB0#
RASB1#

CASB0B
CASB1B

W10
AA10

CASB0#
CASB1#

CSB0B_0
CSB0B_1

P10
L10

CSB0#_0

CSB1B_0
CSB1B_1

AD10
AC10

CSB1#_0

CKEB0
CKEB1

U10
AA11

CKEB0
CKEB1

WEB0B
WEB1B

N10
AB11

WEB0#
WEB1#

MAB0_8
MAB1_8

T8
W8

DRAM_RST

2160809000A11SEYMOU_FCBGA962

22
22

CLKB0
CLKB0#

22
22

CLKB1
CLKB1#

22
22

RASB0#
RASB1#

22
22

CASB0#
CASB1#

22
22

CSB0#_0

22

VGA@
1

CSB1#_0

22

CKEB0
CKEB1

22
22

WEB0#
WEB1#

22
22

VGA@
2

10_0402_5%
1

DQMB#[0..7]

22

22

22

MAB13
R68

AH11

22

QSB#[0..7]

ODTB0
ODTB1

22

B_BA[0..2]

QSB[0..7]

QSB#[0..7]

CLKB0
CLKB0B

MVREFDB
MVREFSB

MAB[0..12]

B_BA[0..2]

C43
120P_0402_50V8

1 243_0402_1%
L27
1 243_0402_1%
N12
1 243_0402_1% AG12

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

R71
VGA@
5.11K_0402_1%

2 VGA@
2 VGA@
2 VGA@

MVREFDB
Y12
MVREFSB AA12

C42
@
0.1U_0402_16V4Z

R62
R63
R64

0.1U_0402_16V4Z

H27
G27

NC_CLKA1
NC_CLKA1B

C38

MAB[0..12]

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

VGA@

NC_CLKA0
NC_CLKA0B

MVREFDB

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

J21
G19

R57
VGA@
100_0402_1%

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

GDDR5

C39
0.1U_0402_16V4Z

R59
VGA@
100_0402_1%

NC_ADBIA0/ODTA0
NC_ADBIA1/ODTA1

R56
VGA@
40.2_0402_1%

MVREFSA

R58
VGA@
40.2_0402_1%

NC_DDBIA0_0/QSA_0B/WDQSA_0
NC_DDBIA0_1/QSA_1B/WDQSA_1
NC_DDBIA0_2/QSA_2B/WDQSA_2
NC_DDBIA0_3/QSA_3B/WDQSA_3
NC_DDBIA1_0/QSA_4B/WDQSA_4
NC_DDBIA1_1/QSA_5B/WDQSA_5
NC_DDBIA1_2/QSA_6B/WDQSA_6
NC_DDBIA1_3/QSA_7B/WDQSA_7

C34
D29
D25
E20
E16
E12
J10
D7

0.1U_0402_16V4Z

+1.5VSG

A34
E30
E26
C20
C16
C12
J11
F8

+1.5VSG

VGA@

NC_WCKA0_0/DQMA_0
NC_WCKA0B_0/DQMA_1
NC_WCKA0_1/DQMA_2
NC_WCKA0B_1/DQMA_3
NC_WCKA1_0/DQMA_4
NC_WCKA1B_0/DQMA_5
NC_WCKA1_1/DQMA_6
NC_WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
NC_EDCA0_0/QSA_0/RDQSA_0
NC_EDCA0_1/QSA_1/RDQSA_1
NC_EDCA0_2/QSA_2/RDQSA_2
NC_EDCA0_3/QSA_3/RDQSA_3
NC_EDCA1_0/QSA_4/RDQSA_4
NC_EDCA1_1/QSA_5/RDQSA_5
NC_EDCA1_2/QSA_6/RDQSA_6
NC_EDCA1_3/QSA_7/RDQSA_7

A32
C32
D23
E22
C14
A14
E10
D9

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

C37

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

NC_MAA0_0/MAA_0
NC_MAA0_1/MAA_1
NC_MAA0_2/MAA_2
NC_MAA0_3/MAA_3
NC_MAA0_4/MAA_4
NC_MAA0_5/MAA_5
NC_MAA0_6/MAA_6
NC_MAA0_7/MAA_7
NC_MAA1_0/MAA_8
NC_MAA1_1/MAA_9
NC_MAA1_2/MAA_10
NC_MAA1_3/MAA_11
NC_MAA1_4/MAA_12
NC_MAA1_5/MAA_13_BA2
NC_MAA1_6/MAA_14_BA0
NC_MAA1_7/MAA_A15_BA1

MDB[0..63]

MDB[0..63]

0.1U_0402_16V4Z

R55
VGA@
100_0402_1%

22

MVREFDA

R54
VGA@
40.2_0402_1%
C

NC_DQA0_0/DQA_0
NC_DQA0_1/DQA_1
NC_DQA0_2/DQA_2
NC_DQA0_3/DQA_3
NC_DQA0_4/DQA_4
NC_DQA0_5/DQA_5
NC_DQA0_6/DQA_6
NC_DQA0_7/DQA_7
NC_DQA0_8/DQA_8
NC_DQA0_9/DQA_9
NC_DQA0_10/DQA_10
NC_DQA0_11/DQA_11
NC_DQA0_12/DQA_12
NC_DQA0_13/DQA_13
NC_DQA0_14/DQA_14
NC_DQA0_15/DQA_15
NC_DQA0_16/DQA_16
NC_DQA0_17/DQA_17
NC_DQA0_18/DQA_18
NC_DQA0_19/DQA_19
NC_DQA0_20/DQA_20
NC_DQA0_21/DQA_21
NC_DQA0_22/DQA_22
NC_DQA0_23/DQA_23
NC_DQA0_24/DQA_24
NC_DQA0_25/DQA_25
NC_DQA0_26/DQA_26
NC_DQA0_27/DQA_27
NC_DQA0_28/DQA_28
NC_DQA0_29/DQA_29
NC_DQA0_30/DQA_30
NC_DQA0_31/DQA_31
NC_DQA1_0/DQA_32
NC_DQA1_1/DQA_33
NC_DQA1_2/DQA_34
NC_DQA1_3/DQA_35
NC_DQA1_4/DQA_36
NC_DQA1_5/DQA_37
NC_DQA1_6/DQA_38
NC_DQA1_7/DQA_39
NC_DQA1_8/DQA_40
NC_DQA1_9/DQA_41
NC_DQA1_10/DQA_42
NC_DQA1_11/DQA_43
NC_DQA1_12/DQA_44
NC_DQA1_13/DQA_45
NC_DQA1_14/DQA_46
NC_DQA1_15/DQA_47
NC_DQA1_16/DQA_48
NC_DQA1_17/DQA_49
NC_DQA1_18/DQA_50
NC_DQA1_19/DQA_51
NC_DQA1_20/DQA_52
NC_DQA1_21/DQA_53
NC_DQA1_22/DQA_54
NC_DQA1_23/DQA_55
NC_DQA1_24/DQA_56
NC_DQA1_25/DQA_57
NC_DQA1_26/DQA_58
NC_DQA1_27/DQA_59
NC_DQA1_28/DQA_60
NC_DQA1_29/DQA_61
NC_DQA1_30/DQA_62
NC_DQA1_31/DQA_63

MEMORY INTERFACE A

+1.5VSG

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DDR2
GDDR5/GDDR3
DDR3

DDR2
GDDR3/GDDR5
DDR3

MEMORY INTERFACE B

U2C

DDR2
GDDR5/GDDR3
DDR3

22

R70
2

MAB13 is for 128M*16 VRAM


VRAM_RST# 22

51.1_0402_1%

VGA@

R72
@
51.1_0402_1%

VGA@

VGA@

R73
@
51.1_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

P19-Vancouver_Memory
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

19

of

47

U2E

MEM I/O

2800mA
+1.5VSG

C347 VGA@
10U_0603_6.3V6M

C346 VGA@
1U_0402_6.3V4Z

C345 VGA@
1U_0402_6.3V4Z

+ C395
+ C396
C394
VGA@
VGA@
VGA@
390U_2.5V_10M 330U_D2_2V_Y330U_D2_2V_Y
2
2
2

Issued Date

+ C447
@
330U_D2_2V_Y
2

J7
2
@

2
1
FBMA-L11-201209-121LMA50T_0805

Compal Electronics, Inc.

Compal Secret Data


2010/06/30

+VGA_CORE

JUMP_43X118

L41 VGA@

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C428 VGA@
10U_0603_6.3V6M

C427 VGA@
10U_0603_6.3V6M

C421 VGA@
10U_0603_6.3V6M

C420 VGA@
1U_0402_6.3V4Z

Security Classification

VGA@

L39 VGA@
2
1
FBMA-L11-201209-121LMA50T_0805

+VDDCI
C419 VGA@
1U_0402_6.3V4Z

2160809000A11SEYMOU_FCBGA962

C426 VGA@
1U_0402_6.3V4Z

FB_GND

0_0402_5%

+BIF_VDDC

C425 VGA@
1U_0402_6.3V4Z

FB_VDDCI

55mA

C424 VGA@
1U_0402_6.3V4Z

FB_VDDC

AG28

+VGA_CORE

C383 VGA@
1U_0402_6.3V4Z

C373 VGA@
1U_0402_6.3V4Z

C382 VGA@
1U_0402_6.3V4Z

C372 VGA@
1U_0402_6.3V4Z

C381 VGA@
1U_0402_6.3V4Z

C371 VGA@
1U_0402_6.3V4Z

C393 VGA@
10U_0603_6.3V6M

330U ESR:10m H:5.7


P/N:SF000002O00

C423 VGA@
1U_0402_6.3V4Z

AF28

VGA@
390U_2.5V_10M
2

C380 VGA@
1U_0402_6.3V4Z

C418 VGA@
1U_0402_6.3V4Z

SPVSS

1
C686 +

C370 VGA@
1U_0402_6.3V4Z

C392 VGA@
10U_0603_6.3V6M

C379 VGA@
1U_0402_6.3V4Z

C369 VGA@
1U_0402_6.3V4Z

C391 VGA@
10U_0603_6.3V6M

C378 VGA@
1U_0402_6.3V4Z

C368 VGA@
1U_0402_6.3V4Z

C390 VGA@
10U_0603_6.3V6M

AN10

C357 VGA@
10U_0603_6.3V6M

C356 VGA@
1U_0402_6.3V4Z

C355 VGA@
1U_0402_6.3V4Z

C377 VGA@
1U_0402_6.3V4Z

SPV10

FB_GND AH29

C422 VGA@
1U_0402_6.3V4Z

C367 VGA@
1U_0402_6.3V4Z

SPV18

AN9

R375
1

C334 VGA@
1U_0402_6.3V4Z

GCORE_SEN

4A

AM10

VOLTAGE
SENESE
GCORE_SEN

C344 VGA@
1U_0402_6.3V4Z

C417 VGA@
1U_0402_6.3V4Z

44

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

C416 VGA@
1U_0402_6.3V4Z

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

FOR XT DDR3 13 A (RMS)/14.2 A(Peak)

C415 VGA@
1U_0402_6.3V4Z

MPV18#1
MPV18#2

C389 VGA@
10U_0603_6.3V6M

120mA

+SPV10

H7
H8

C376 VGA@
1U_0402_6.3V4Z

NC_VDDRHB
NC_VSSRHB

FBMA-L11-201209-221LMA30T_0805
2
1
+1.8VSG
L34 VGA@
1
1
220ohm/2A

+1.0VSG
1

C414 VGA@
0.1U_0402_16V4Z

470ohm/1A

V12
U12

2A

C366 VGA@
1U_0402_6.3V4Z

75mA

C413 VGA@
0.1U_0402_16V4Z

2
1
L40
VGA@
BLM18AG121SN1D_0603

NC_VDDRHA
NC_VSSRHA

C333 VGA@
1U_0402_6.3V4Z

75mA

+MPV_18

C412 VGA@
1U_0402_6.3V4Z

+1.0VSG

M20
M21

PLL

C408 VGA@
10U_0603_6.3V6M

C411 VGA@
0.1U_0402_16V4Z

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

C328 VGA@
1U_0402_6.3V4Z

C402 VGA@
0.1U_0402_16V4Z

C407 VGA@
0.1U_0402_16V4Z

C406 VGA@
1U_0402_6.3V4Z

C405 VGA@
0.1U_0402_16V4Z

C404 VGA@
1U_0402_6.3V4Z

+SPV_18
C410 VGA@
1U_0402_6.3V4Z

C409 VGA@
10U_0603_6.3V6M

BLM18AG121SN1D_0603
2
1
+1.8VSG
L38
VGA@
1
120ohm/0.3A

C403 VGA@
10U_0603_6.3V6M

C401 VGA@
1U_0402_6.3V4Z

+1.8VSG

C400 VGA@
10U_0603_6.3V6M

AD12
AF11
AF12
AG11

+VDDR4

2
1
L36
VGA@
BLM18AG601SN1D_2P

120ohm/0.3A

BLM18AG121SN1D_0603
2
1
L37
VGA@
1
470ohm/1A

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

C354 VGA@
1U_0402_6.3V4Z

170mA
+1.8VSG

AF13
AF15
AG13
AG15

C327 VGA@
1U_0402_6.3V4Z

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

C388 VGA@
10U_0603_6.3V6M

C399 VGA@
0.1U_0402_16V4Z

C398 VGA@
1U_0402_6.3V4Z

C397 VGA@
10U_0603_6.3V6M

Removed bead on ref137-12

I/O
AF23
AF24
AG23
AG24

C375 VGA@
1U_0402_6.3V4Z

60mA
+3VSG

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

C387 VGA@
10U_0603_6.3V6M

AF26
AF27
AG26
AG27

C365 VGA@
1U_0402_6.3V4Z

219mA

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

+PCIE_VDDR
1

C374 VGA@
1U_0402_6.3V4Z

LEVEL
TRANSLATION

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

POWER

C386 VGA@
0.1U_0402_16V4Z

C385 VGA@
1U_0402_6.3V4Z

120ohm/0.3A

C384 VGA@
10U_0603_6.3V6M

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

504mA

C364 VGA@
1U_0402_6.3V4Z

+VDD_CT

2
1
L35
VGA@
BLM18AG121SN1D_0603

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

C332 VGA@
1U_0402_6.3V4Z

C363 VGA@
1U_0402_6.3V4Z

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

C343 VGA@
0.1U_0402_16V4Z

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

C353 VGA@
1U_0402_6.3V4Z

PCIE
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C326 VGA@
0.1U_0402_16V4Z

C352VGA@
1U_0402_6.3V4Z

C362 VGA@
1U_0402_6.3V4Z

C342 VGA@
1U_0402_6.3V4Z

C351VGA@
1U_0402_6.3V4Z

C337 VGA@
1U_0402_6.3V4Z

C341 VGA@
1U_0402_6.3V4Z

C350VGA@
1U_0402_6.3V4Z

C325 VGA@
1U_0402_6.3V4Z

C361 VGA@
1U_0402_6.3V4Z

C360 VGA@
10U_0603_6.3V6M

C331VGA@
1U_0402_6.3V4Z

C330VGA@
1U_0402_6.3V4Z

C359 VGA@
10U_0603_6.3V6M

+1.8VSG

C336 VGA@
10U_0603_6.3V6M

C358 VGA@
10U_0603_6.3V6M

C329VGA@
1U_0402_6.3V4Z

C349VGA@
1U_0402_6.3V4Z

C348VGA@
1U_0402_6.3V4Z

390U ESR:10m H:5.7


P/N:SF000002O00

C340 VGA@
1U_0402_6.3V4Z

C324 VGA@
1U_0402_6.3V4Z

C339 VGA@
1U_0402_6.3V4Z

C322
VGA@
390U_2.5V_10M

C338 VGA@
1U_0402_6.3V4Z

C323 VGA@
1U_0402_6.3V4Z

Title

P20-Vancouver_Power/GND
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

20

of

47

U2F

U2H

DP C/D POWER

+1.8VSG

470ohm/1A

150mA

+1.0VSG

110mA

+DPCD_VDD10

+DPCD_VDD10

+1.8VSG

AN19
AP18
AP19
AW20
AW22

PX_EN

23

C443
VGA@
1U_0402_6.3V4Z

C442
VGA@
0.1U_0402_16V4Z

2
R378

AW18

+DPEF_VDD18

AH34
AJ34

+DPEF_VDD10

AL33
AM33

470ohm/1A
1

440mA

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AN34
AP39
AR39
AU37

0_0402_5%

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS
+DPEF_VDD18

+1.0VSG

L80
VGA@
BLM18AG121SN1D_0603
2
1

470ohm/1A

AF34
AG34

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2
DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

+DPEF_VDD10

AK33
AK34

+DPAB_VDD10

AN27
AP27
AP28
AW24
AW26

AP25
AP26

AF39
AH39
AK39
AL34
AM34
R379
2 VGA@ 1 AM39

470ohm/1A

+1.8VSG

+DPAB_VDD18

+DPAB_VDD10

AN33
AP33

220mA

AN29
AP29
AP30
AW30
AW32

L66
VGA@
BLM18AG121SN1D_0603
1
+1.0VSG

470ohm/1A

R377
150_0402_1%
1 VGA@ 2

AW28

AU28
AV27

+DPAB_VDD18

AV29
AR28

+DPAB_VDD18

AU18
AV17

+DPCD_VDD18

AV19
AR18

+DPCD_VDD18

AM37
AN38

+DPEF_VDD18

AL38
AM35

+DPEF_VDD18

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

C446 VGA@
1U_0402_6.3V4Z

C445 VGA@
0.1U_0402_16V4Z

C444 VGA@
10U_0603_6.3V6M

240mA

AP31
AP32

R376
150_0402_1%
2 VGA@ 1
L67
VGA@
BLM18AG121SN1D_0603
2
1

AP14
AP15

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

C440
VGA@
10U_0603_6.3V6M

AP22
AP23

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

C439
VGA@
1U_0402_6.3V4Z

AP13
AT13
AN17
AP16
AP17
AW14
AW16

C437 VGA@
1U_0402_6.3V4Z

C436 VGA@
0.1U_0402_16V4Z

+DPAB_VDD18

C438
VGA@
0.1U_0402_16V4Z

470ohm/1A

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

L63
VGA@
BLM18AG121SN1D_0603
2
1

300mA
1

+DPCD_VDD18
L64
VGA@
BLM18AG121SN1D_0603
2
1

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

AN24
AP24

C434 VGA@
1U_0402_6.3V4Z

+DPCD_VDD18

DP A/B POWER

C433 VGA@
0.1U_0402_16V4Z

AP20
AP21

C432 VGA@
10U_0603_6.3V6M

C431 VGA@
1U_0402_6.3V4Z

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR

150_0402_1%
2160809000A11SEYMOU_FCBGA962

VGA@

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A39
AW1
AW39

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160809000A11SEYMOU_FCBGA962

VGA@
5

L42
VGA@
BLM18AG121SN1D_0603
2
1
C430 VGA@
0.1U_0402_16V4Z

GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

C441
VGA@
10U_0603_6.3V6M

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

C435 VGA@
10U_0603_6.3V6M

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
@
1
2
V13
R4550_0603_5%

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

C429 VGA@
10U_0603_6.3V6M

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

Title

P21-Vancouver_Power/GND
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

21

of

47

U6

19

VREFCB_A1 M8
VREFDB_Q1 H1

MDB[0..63]

19

MAB[13..0]

19

DQMB#[7..0]

19

QSB[7..0]

19

QSB#[7..0]

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

ZZZ1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

VREFCB_A2 M8
VREFDB_Q2 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

19
19
19

B_BA0
B_BA1
B_BA2

19

CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

19
19
19
19
19

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

CLKB0
CLKB0#

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSG

U8

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

1GVRAM
X76L01@

U7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#

+1.5VSG

+1.5VSG

U9
VREFCB_A4 M8
VREFDB_Q4 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#
CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSG

19

CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

19
19
19
19
19

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

VREFCA
VREFDQ

+1.5VSG

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSG

+1.5VSG

ZZZ2

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

R79
VGA@
243_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R80
VGA@
243_0402_1%

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@
+1.5VSG

+1.5VSG

J1
L1
J9
L9

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E7
D3

QSB#4
QSB#5

G3
B7

VRAM_RST#

DML
DMU

T2

B1
B9
D1
D8
E2
E8
F9
G1
G9

RESET
ZQ/ZQ0

J1
L1
J9
L9

R81
VGA@
243_0402_1%

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

L8

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@
+1.5VSG

+1.5VSG

DQMB#4
DQMB#5

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSG

+1.5VSG

VGA@ 2

VREFCB_A3
1

R78
VGA@
4.99K_0402_1%

C173
VGA@ 2

VREFDB_Q3
1

C172

VREFDB_Q2
1

R89
VGA@
4.99K_0402_1%

R100
VGA@
4.99K_0402_1%

C174
VGA@ 2

VGA@ 2

R98
VGA@
4.99K_0402_1%

R88
VGA@
4.99K_0402_1%

C171

VREFCB_A2
1

R97
VGA@
4.99K_0402_1%

1
2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R90
VGA@
4.99K_0402_1%

VREFCB_A4
1

R101
VGA@
4.99K_0402_1%

C175
VGA@ 2

R102
VGA@
4.99K_0402_1%

VREFDB_Q4
1
C176
VGA@ 2

+1.5VSG
+1.5VSG

+1.5VSG

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

C206 VGA@
10U_0603_6.3V6M

C205 VGA@
10U_0603_6.3V6M

C204 VGA@
10U_0603_6.3V6M

VRAM P/N :
Samsung : SA00004GS10 (S IC D3 64M16 K4W1G1646G-BC11 FBGA) 900MHz
Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )800MHz
Hynix : SA000041S40 ( S IC D3 64MX16 H5TQ1G63DFR-11C FBGA )900MHz

C203 VGA@
10U_0603_6.3V6M

C202 VGA@
10U_0603_6.3V6M

C201 VGA@
10U_0603_6.3V6M

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C197 VGA@
1U_0402_6.3V6K

C196 VGA@
1U_0402_6.3V6K

C195 VGA@
1U_0402_6.3V6K

C194 VGA@
1U_0402_6.3V6K

C193 VGA@
1U_0402_6.3V6K

C192 VGA@
1U_0402_6.3V6K

C191 VGA@
1U_0402_6.3V6K

C190 VGA@
1U_0402_6.3V6K

C189 VGA@
1U_0402_6.3V6K

C188 VGA@
1U_0402_6.3V6K

C187 VGA@
1U_0402_6.3V6K

C186 VGA@
1U_0402_6.3V6K

C185 VGA@
1U_0402_6.3V6K

C184 VGA@
1U_0402_6.3V6K

C183 VGA@
1U_0402_6.3V6K

C182 VGA@
1U_0402_6.3V6K

C181 VGA@
1U_0402_6.3V6K

+1.5VSG

C200 VGA@
10U_0603_6.3V6M

CLKB1#

R106 VGA@
56_0402_1%
1
2

C199 VGA@
10U_0603_6.3V6M

CLKB1

R105 VGA@
56_0402_1%
1
2

C180 VGA@
1U_0402_6.3V6K

C179 VGA@
1U_0402_6.3V6K

19

ZQ/ZQ0

+1.5VSG

C198 VGA@
0.01U_0402_25V7K

+1.5VSG

19

1
2
2

R104 VGA@
56_0402_1%
2

RESET

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

0.1U_0402_16V4Z

R103 VGA@
56_0402_1%
2

C178 VGA@
1U_0402_6.3V6K

CLKB0#

C177 VGA@
0.01U_0402_25V7K

19

CLKB0

DQSL
DQSU

0.1U_0402_16V4Z

19

VGA@ 2

J1
L1
J9
L9

R82
VGA@
243_0402_1%

0.1U_0402_16V4Z

VGA@ 2

VREFDB_Q1
1
C170

L8

+1.5VSG

0.1U_0402_16V4Z

R95
VGA@
4.99K_0402_1%

R96
VGA@
4.99K_0402_1%

T2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@

R87
VGA@
4.99K_0402_1%

0.1U_0402_16V4Z

VREFCB_A1
1
C169

R86
VGA@
4.99K_0402_1%

0.1U_0402_16V4Z

R1735 @
56_0402_1%
2

R83
VGA@
4.99K_0402_1%

ODTB1

G3
B7

DML
DMU

+1.5VSG

R85
VGA@
4.99K_0402_1%

0.1U_0402_16V4Z

ODTB1

ODTB0

0.1U_0402_16V4Z

19

ODTB0

19

R84
VGA@
4.99K_0402_1%

QSB#6
QSB#7

96-BALL
SDRAM DDR3
K4W1G1646G-BC11
X76@
+1.5VSG

R1734 @
56_0402_1%
2

E7
D3

VRAM_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQMB#6
DQMB#7

J1
L1
J9
L9

VRAM_RST# T2

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQSL
DQSU

ZQ/ZQ0

G3
B7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F3
C7

RESET

L8

QSB#2
QSB#0

DML
DMU

QSB6
QSB7

A1
A8
C1
C9
D2
E9
F1
H2
H9

T2

E7
D3

DQSL
DQSU

VRAM_RST#

VRAM_RST#

DQMB#2
DQMB#0

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

19

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB4
QSB5

G3
B7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

QSB#3
QSB#1

DML
DMU

F3
C7

E7
D3

QSB2
QSB0

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQMB#3
DQMB#1
C

DQSL
DQSU

A1
A8
C1
C9
D2
E9
F1
H2
H9

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

QSB3
QSB1

X76L03@

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

A1
A8
C1
C9
D2
E9
F1
H2
H9

512MVRAM

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

Title

P22-VRAM_DDR3 / Channel B
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

22

of

47

Power Sequence of Whistler and Seymour


VGA Muxless with BACO Status Mapping table
Normal mode
BACO mode
PX_EN
0
1
1.5_VDDC_PWREN
1
0
VDDC_EN
1
0
1.0_EN
0
1
+3.3VSG
ON
ON
+1.8VSG
ON
ON
+1.0VSG
ON
ON
+VGA_CORE
ON
OFF
+1.5VSG
ON
OFF
+BIF_VDDC
+VGA_CORE
+1.0VSG

SUSP#
+3VSG

For PX sequence, >1mS delay is required between


PE_GPIO1 and VGA_PWR_ON

(JUMP form +3VS)

10ms

VGA_ON
D

VGA_PWR_ON
PE_GPIO1

1.5_VDDC_PWREN

VGA_PWR_ON

>1ms

+VGA_CORE
+1.0VSG
+1.5VSG

VGA Power Enable Signal Mapping table


Seymour
VGA_PWR_ON source signal
VGA_ON
+3.3VSG
SUSP#
+1.8VSG
VGA_PWR_ON#
+1.0VSG
VGA_PWR_ON
+VDDCI
Combine with +VGA_CORE
+VGA_CORE
1.5_VDDC_PWREN
+1.5VSG
1.5_VDDC_PWREN#

20ms

+1.8VSG

R114
1.5_VDDC_PWREN

0_0402_5%

Y
A

2
1

5
4

12,41,42,44 VGA_PWRGD

From +VGA_CORE regulator

NC7SZ08P5X_NL_SC70-5

6
2

Q3A
VGA@
DMN66D0LDW-7_SOT363-6

VGA_PWR_ON 24,41

1.0_EN
U12
VGA@

Q3B
VGA@
DMN66D0LDW-7_SOT363-6

12,30 PE_GPIO1

VGA_PWR_ON

For VGA Power on control


0_0402_5%
1
2
R119
10K_0402_1%
@

VDDC_EN

+3VS

C209 VGA@
0.1U_0402_10V7K
2
1

VGA_ON

R113
VGA@
1K_0402_5%

30

R112
VGA@
1K_0402_5%

R111

Delay SUSP# 10ms

+5VS

+5VS

@
R107 1

WOBACO@

2 0_0402_5%
Q4

Y
3

VGA@

+VGA_CORE

2
0_0805_5%

1
C212
C239
VGA@
VGA@
10U_0603_6.3V6M
2
2 10U_0603_6.3V6M

2
G

VDDC_EN

30mil

+VGA_CORE

1
VGA@

Q7
AO3416_SOT23-3

3
VGA@

Q2
VGA@
2N7002_SOT23

3
VGA@

1.0_EN

R110 0_0402_5%
5.11K_0402_1%
VGA@

1.5_VDDC_PWREN 24,44

@
1
R117

30mil

NC7SZ08P5X_NL_SC70-5

2
G
3

1.5_VDDC_PWREN

WOBACO@

+BIF_VDDC

PX_EN

R77
21

2
G

2 10K_0402_5% 1

R108 1

1
VGA@

U10
VGA@
G

+3VS

20mil

3
VGA_PWR_ON

Q5
AO3416_SOT23-3

AO3416_SOT23-3

+1.0VSG

C207 VGA@
0.1U_0402_10V7K
1
2

+3VS

AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V

Q8
AO3416_SOT23-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

P23-VGA power sequence and BACO


Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
1

23

of

47

+5VALW

+5VALW

R1134
10K_0402_5%

R1123
100K_0402_5%

Q68
2
G

23,41 VGA_PW R_ON

Q77
2
G

23,44 1.5_VDDC_PW REN

VGA_PW R_ON#
D

1.5_VDDC_PW REN#

SSM3K7002FU_SC70-3

34 1.5_VDDC_PW REN#

+3VSG

1 VGA@ 2
R124
0_0805_5%

+3VS

R1119
100K_0402_5%

R1131
100K_0402_5%

SSM3K7002FU_SC70-3

+3.3VS TO +3.3VSG

+1.8VS TO +1.8VSG

+1.5V TO +1.5VSG

Change P/N SB00000GV00


+1.8VS

2
10U_0603_6.3V6M

+VSB

1.5VSG_GATE
1 VGA@ 2
R136
100K_0402_5%

Q17

2
G
VGA@

+VSB

1.5_VDDC_PW REN#

C235
VGA@
0.1U_0603_25V7K

Q19
2
G
VGA@

SSM3K7002FU_SC70-3

2 VGA@ 1
R139 47K_0402_5%

1.5_VDDC_PW REN#

2
D

1.8VSG_GATE
2 VGA@ 1
R135 100K_0402_5%

Q16

2 VGA_PW R_ON#
G
VGA@

SSM3K7002FU_SC70-3
Q18
VGA_PW R_ON# 2 VGA@ 1
2
G
R137 100K_0402_5%
VGA@
1

SSM3K7002FU_SC70-3

VGA@

VGA@ VGA@
2
2
10U_0603_6.3V6M 10U_0603_6.3V6M

R134
VGA@
470_0603_5%

R133
VGA@
470_0603_5%

1
1
C227
VGA@
10U_0603_6.3V6M C228
2
2 VGA@
1U_0402_6.3V4Z

C225
VGA@
1U_0402_6.3V4Z
2

1
2
3

C224
VGA@
10U_0603_6.3V6M
2

C229

C233
VGA@
0.1U_0603_25V7K

VGA@

C226

8
7
6
5

C234
VGA@
2
0.1U_0603_25V7K

SSM3K7002FU_SC70-3

1
2
3

8
7
6
5

2
10U_0603_6.3V6M

C231

+1.5VSG

VGA@
U14
AO4478L 1N SO8

+1.5V

C230
VGA@

+1.8VSG
U15
AO4478L 1N SO8

C232
VGA@
0.1U_0603_25V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

P24-VGA DC Interface
Size
Document Number
Custom

Rev
1.0

LA-7322P

Date: Thursday, February 17, 2011

Sheet
1

24

of

47

1
1

1
C1616

1
C1615

0.1U_0402_16V7K

1
C1614

C1621

C1622

C1623

These caps close to Pin 12,27,39,42,47,48


+LAN_IO
+LAN_IO

2 +LAN_VDDREG

R1620
10K_0402_5%

0_0603_5%
C1625

2
G

W=40mils

R535
1

R553
10K_0402_5%

2
LAN_WAKE#

3
S

13,28,30 FCH_PCIE_WAKE#

1
C1626
2

W=20mils

+LAN_VDD

R536
2 +LAN_EVDD10

0_0603_5%

1
C1627
2

1
C1628
2

1U_0402_6.3V6K

C1624
0.1U_0603_25V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

4.7U_0603_6.3V6K

1
1

C1620

These caps close to Pin 3,6,9,13,29,41,45

Q30
SSM3K7002FU_SC70-3
3

2
EN_WOL#

C1619

SSM3K7002FU_SC70-3

R534
1
2 EN_WOL#
220K_0402_5%~N

2
G

EN_WOL
2

30

C1618

Q54
2
G

R533
100K_0402_5%

C1617

0.1U_0402_16V7K

R1102
470_0603_5%

1
C1613

0.1U_0402_16V7K

1
C1612

0.1U_0402_16V7K

C1611

0.1U_0402_16V7K

AO3419L_SOT23-3

0.1U_0402_16V7K

+5VALW

1.5A

C1610
1U_0402_6.3V6K

+LAN_VDD

+LAN_IO
Q29
3

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

JUMP_43X118

0.1U_0402_16V7K

+LAN_IO

0.1U_0402_16V7K

+3VALW

W=60mils

0.1U_0402_16V7K

J8

W=60mils

0.1U_0402_16V7K

Q91
2N7002_SOT23
U49
22

12 PCIE_FRX_DTX_N0

C1630 1

20.1U_0402_16V7K

PCIE_FRX_C_DTX_N0

23
17
18

12 PCIE_FTX_C_DRX_P0
12 PCIE_FTX_C_DRX_N0

HSOP
HSON

LED3/EEDO
LED1/EESK
LED0

31
37
40

EECS/SCL
EEDI/SDA

30
32

HSIP
HSIN

R5371
R5381

2 10K_0402_5%
2 10K_0402_5%
+LAN_SROUT1.05

16

13 LAN_CLKREQ#
12,17,28 PLT_RST#

25

PERSTB

12 CLK_PCIE_LAN
12 CLK_PCIE_LAN#

19
20

REFCLK_P
REFCLK_N

+3VS

XTLO

43

XTLI

44

LAN_WAKE#

R540
1

CLKREQB

ISOLATEB

28
26

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

2
R541
15K_0402_5%
1

+LAN_IO

2
1 R544
+LAN_IO
0_0402_5%
3.3V : Enable switching regulator
0V
: Disable switching regulator

R545
B

R547 1

2 10K_0402_5%
2 1K_0402_5%

14
15
38
33

+LAN_VDDREG

34
35

2 2.49K_0402_1%

46

2
24
49

0_0603_5%
R546
1 @
2

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

W=60mils

W=60mils

4.7UH_SIA4012-4R7M_20%

1
C1631
2

1
C1632
2

C1633
1

CKXTAL2

DVDD10
DVDD10
DVDD10
DVDD33
DVDD33

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

27
39
12
42
47
48

+LAN_IO

EVDD10
VDDREG
VDDREG

AVDD10
AVDD10
AVDD10
AVDD10

RSET
GND
PGND

REGOUT

21

+LAN_EVDD10

3
6
9
45
36

LAN_MDIP1

I/O4

LAN_MDIN0

I/O2

+LAN_VDD
5

+LAN_IO

VDD

GND

0_0402_5%
Y6
25MHZ_12PF_X5H025000FC1H-H
XTLO

JLAN1

RJ45_TX3-

RJ45_TX3+

RJ45_RX1-

RJ45_TX2-

RJ45_TX2+

RJ45_RX1+

RJ45_TX0-

RJ45_TX0+

PR4PR4+
PR2PR3PR3+
PR2+
PR1PR1+
SHLD1

+LAN_SROUT1.05
LAN_MDIN1

I/O3

LAN_MDIP0

I/O1

XTLI

12P_0402_50V8J

D18

ENSWREG

C1634

These components close to Pin 36


( Should be place within 200 mils )

+LAN_VDD

LANWAKEB
ISOLATEB

1
13
29
41

R539

15P_0402_50V8J

CKXTAL1

1K_0402_5%
R542 1
R543 1

1
2
4
5
7
8
10
11

+LAN_VDD

L120

PCIE_FRX_C_DTX_P0

20.1U_0402_16V7K

4.7U_0603_6.3V6K

C1629 1

0.1U_0402_16V7K

12 PCIE_FRX_DTX_P0

SHLD2

10

AZC099-04S.R7G_SOT23-6
RTL8111E-VL-CGT_QFN48_6X6

SANTA_130452-C

0_0603_5%

GND_LAN

@
GND_LAN

TS1
@ D38

C1635 1

0.01U_0402_16V7K

+V_DAC
LAN_MDIN3
LAN_MDIP3

1
2
3

+V_DAC
LAN_MDIN2
LAN_MDIP2

4
5
6

+V_DAC
LAN_MDIN1
LAN_MDIP1

7
8
9

+V_DAC
LAN_MDIN0
LAN_MDIP0

10
11
12

MCT1
MX1+
MX1-

24
23
22

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT1
TD1+
TD1-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

18
17
16
15
14
13

R549 1
R1529 1
R1530 1
R552 1

RJ45_TX3RJ45_TX3+

2
2
2
2

75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%

RJ45_TX0+ 1

RJ45_TX0-

PD10943-T7_SOD323-2

RJ45_TX2RJ45_TX2+

D19
2

RJ45_RX1RJ45_RX1+

LAN_MDIP3

C1636
1000P_1206_2KV7K

I/O4

I/O2

VDD

GND

LAN_MDIP2

RJ45_RX1+ 1

@ D40

+LAN_IO

RJ45_TX2+ 1

GND_LAN
RJ45_TX0RJ45_TX0+

RJ45_RX1-

PD10943-T7_SOD323-2
2

RJ45_TX2-

PD10943-T7_SOD323-2
LAN_MDIN3

I/O3

I/O1

LAN_MDIN2

@ D41
RJ45_TX3+ 1

AZC099-04S.R7G_SOT23-6
LG-2446S-1 100/1000BASE-TX LAN

D21

@
1

LSE-200NX3216TRLF_1206-2
2

D22

@
1

LSE-200NX3216TRLF_1206-2
2

D31

@
1

LSE-200NX3216TRLF_1206-2
2

D34

@
1

LSE-200NX3216TRLF_1206-2
2

ESD
4

GND_LAN

RJ45_TX3-

PD10943-T7_SOD323-2

For ESD request.

Issued Date

ESD

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

SOD323 package
A

Compal Secret Data

Security Classification

@ D39

Title

Compal Electronics, Inc.


P25-LAN RTL8111E

Size Document Number


Custom LA-7322P
Date:

Rev
1.0
Sheet

Thursday, February 17, 2011


1

25

of

47

MIC1_R 1
2
1K_0402_5%
MIC2_R 1
1 R1540 2
1K_0402_5%
1 R1539

MIC2

10
10
30

DMIC_DATA

DMIC_DATA

DMIC_CLK

DMIC_CLK

R1543 1
L121 1

EMI request 12.24


EC_MUTE#

EC_MUTE#

R1545

2 0_0402_5% DMIC_DATA_CODEC
DMIC_CLK_CODEC
2
FBMA-L10-160808-301LMT_2P
PD#

2
3
4

SPKOUT_R1

R1535 1

2 0_0603_5%

SPK_R1

1
1 C1480

2 0_0603_5%

SPK_R2

1
C1478

2
0.22U_0603_16V7K
@

1
1

@
SPK_OUT_L+
SPK_OUT_LSPK_OUT_R+
SPK_OUT_R-

45
44

SPKOUT_R1
SPKOUT_R2

HP_OUT_L
HP_OUT_R

32
33

HP_OUTL
HP_OUTR

MIC1_L
MIC1_R
MIC2_L
MIC2_R

HDA_SYNC_AUDIO
2
C1494
@

GPIO0/DMIC_DATA

SYNC

10

HDA_SYNC_AUDIO

BCLK

HDA_BITCLK_AUDIO_R 1 R1590

GPIO1/DMIC_CLK
PD#

SDATA_IN

HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

HDA_SDIN_AUDIO1 R1546 2
33_0402_5%

2
0_0402_5%

R1538
@

1
C1492
@

R1541
R1542

2
2

13
+MIC1_VREFO_R
+MIC1_VREFO_L

1 2.2K_0402_1%
1 2.2K_0402_1%

HDA_SDIN0 13

PCBEEP
MONO_OUT

SENSE_A

13
18
36

+MIC1_VREFO_L

SPDIFO

1
2
35
C1497 2.2U_0603_16V6K
31
43
42
49
7

+1.5VS

47

1 R1547

48

0_0402_5%

EAPD

30

MIC2

20

MIC2_VREFO
SENSE B
CBP

MIC1_VREFO_R
LDO_CAP

CBN

VREF

MIC1_VREFO_L

JDREF

PVSS2
PVSS1
DVSS2
DVSS1

CPVEE
AVSS1
AVSS2

13
13

USB20_N5
USB20_P5

MIC_JD

29
30
28

+MIC1_VREFO_R

27

AC97_VREF

19

AC_JDREF

34
26
37

1 R1552 2
20K_0402_1%
1
2
C1498
2.2U_0603_16V6K

1
C1499

C1500

C1501
2

MIC-2
BLM18PG121SN1D_0603
2 MIC-1
BLM18PG121SN1D_0603
1
1
2

L110
MIC1

SENSE A

L109

C1495
220P_0402_50V7K

10U_0805_10V6K

1 R1548 2
20K_0402_1%
2 R1549 1
39.2K_0402_1%

EAPD

ACES_87213-1400G

C1506

0.1U_0402_16V7K
<BOM Structure>

12

RESET#

+USB_VCCB

HDA_BITCLK_AUDIO 13

10U_0805_10V6K

HP_JD

11

D10

HDA_SDOUT_AUDIO 13

MIC_JD

HDA_RST_AUDIO#

5
6

HDA_BITCLK_AUDIO

220P_0402_50V7K
13 HDA_RST_AUDIO#

D9
@

C1491
SPKOUT_L1
SPKOUT_L2

G1
G2

ACES_88266-04001

2
0.22U_0603_16V7K
@

Close to JSPK1

HDA_SDOUT_AUDIO
2

1
2
3
4

PJMBZ6V8_SOT23-3

1
C1484

1
2
3
4

+5VS

<BOM Structure>

U50

SPK_L1
SPK_L2
SPK_R1
SPK_R2

2
0.22U_0603_16V7K
@
1U_0603_10V6K

R1536 1

2
1
MBK1608800YZF 0603

10P_0402_50V8J

38

25

JSPK1

AVDD2

AVDD1

46

39

PVDD2

PVDD1

C1487

40
41

SDATA_OUT

0_0402_5%

0_0402_5%

LINE2_L
LINE2_R

SPK_L2

14
15
2 C1490 4.7U_0603_6.3V6K MIC1_C 21
MIC2_C 22
2 C1493 4.7U_0603_6.3V6K
16
17

LINE1_L
LINE1_R

C1486

23
24

2 0_0603_5%

22P_0402_50V8J

MIC1
2

R1533 1

L108

C1485

DVDD

C1489

2
0.22U_0603_16V7K
@
1U_0603_10V6K

SPKOUT_L2

+5VS_PVDD +VDDA

DVDD_IO

C1488

1
1 C1473

@ C1483

0.1U_0402_16V7K

0_0603_5%

C1477

SPK_L1

2 0_0603_5%

@ C1474

SPKOUT_R2

+3VS_DVDD
1

10U_0603_6.3V6M

R1532 1

10P_0402_50V8J

R1537
+3VS

10U_0805_10V6K

1
C1482

C1476

0.1U_0402_16V7K

C1481

0.1U_0402_16V7K

0_0603_5%

0.1U_0402_16V7K

1 +3VS_DVDD_R

10U_0603_6.3V6M

R1534
2

+3VS_DVDD

PJMBZ6V8_SOT23-3

C1475

0.1U_0402_16V7K

10U_0805_10V6K

SPKOUT_L1
1

0_0805_5%

+5VS_PVDD

R1531
2

+5VS

0.1U_0402_16V7K

HP_JD
HPR
HPL

C1496
220P_0402_50V7K

14
13
12
11
10
9
8
7
6
5
4
3
2
1

14
13
12
11
10
9
8
7
6
5
4
3
2
1
JAU1

ALC269-GR_QFN48_7X7

4.7K_0402_5%
R1553 @
2
HDA_RST_AUDIO#
1

HP_OUTR 1

Change to cap PN for audio issue.

@
0.1U_0402_16V7K
C1503

R1556 1

2 0_0402_5%

R1557 1

2 0_0402_5%

R1558 1

2 0_0402_5%

R1559 1

2 0_0402_5%

R1554
75_0603_1%
2 HP_R

L111
1

2
L112

HP_OUTL 1 R1555 2 HP_L


75_0603_1%

HPR
BLM18PG121SN1D_0603
HPL
BLM18PG121SN1D_0603
1
1

C1502
470P_0402_50V7K

C1504
470P_0402_50V7K

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

P26-HD CODEC ALC259


Size Document Number
Custom LA-7322P
Date:

Thursday, February 17, 2011


G

Rev
1.0
Sheet

26
H

of

47

Card Reader RTS5137


(only SD/MMC/MS function)
+3VS

+3VS_CR

R1560

2 0_0603_5%

30mil

13
13

+RREF & +VREF need 12mils


1

12mil

U51

+RREF

REFE

2
3

DM
DP

+3VS_CR
4
5
30mil +CARDPWR
+VREG
6
1
10mil
C1512
7
1U_0402_6.3V6K
SDWP_MSCLK
1 R515
2 SDWP_MSCLK_R8
2
0_0402_5% MS_INS#
9
SDD1
10
SDD0
11
MSD3
12

C1511

1
0.1U_0402_16V4Z

GPIO0

3V3_IN
CARD_3V3
V18
NC
SP1
SP2
SP3
SP4
SP5

25

C1510
4.7U_0805_10V4Z

1
100P_0402_50V8J
2
6.2K_0603_1%
USB20_N4
USB20_N4
USB20_P4
USB20_P4

EPAD

2
C1507
R1733 1

17

CLK_IN

24

NC

23

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

@
1
R1561
CLK_SD_48M

2
1
10_0402_5% @
@C1509
C1509

2
10P_0402_50V8J

CLK_SD_48M 12

MS_BS
SDD2
SDD3_MSD1
SDCMD
MSD0
SDCLKMSD2 1
R441
SDCD#

EMI
SDCLK_MSD2
2
0_0402_5%

RTS5137-GR_QFN24_4X4

Card Reader Connector

SDCLK_MSD2

@
C787
1
2
0.1U_0402_16V4Z

+CARDPWR

30mil
SDWP_MSCLK

R1562
100K_0402_5%

1
C1514
0.1U_0402_16V4Z

C1515
0.1U_0402_16V4Z

@
C788
1
2
0.1U_0402_16V4Z

+CARDPWR
JCR1

C1513
0.1U_0402_16V4Z

Close to connector

Close to U51

EMI

SDCD#
SDWP_MSCLK
SDD1
SDD0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

MS_BS
SDCLK_MSD2
MSD0

MS_INS#
MSD3
SDCMD
SDD3_MSD1
SDD2
B

22
23

SD-CD
SD-WP
SD-D1
SD-D0
MS-GND
SD-GND
MS-BS
SD-CLK
MS-D1
MS-D0
SD-VCC
MS-D2
SD-GND
MS-INS
MS-D3
SD-CMD
MS-SCLK
MS-VCC
SD-D3
MS-GND
SD-D2

GND
GND
TAITW_R009-142-HM

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

P27-RTS5137 Media Card Controller


Size Document Number
Custom
LA-7322P
Date:

Rev
1.0

Thursday, February 17, 2011

Sheet
1

27

of

47

W=60mils

Mini-Express Card for WLAN/WiMAX(Half)

+3VS_WLAN

+3VALW

+1.5VS

13 MINI1_CLKREQ#

2 0_0402_5%

WLAN_WAKE#

C124

EMI

2
10P_0402_50V8J
@

PCI_RST#_R
CLK_PCI_DB

R517
1CLK_PCI_DB

12 PCIE_FRX_DTX_N1
12 PCIE_FRX_DTX_P1

0_0402_5%
@

12 PCIE_FTX_C_DRX_N1
12 PCIE_FTX_C_DRX_P1
+3VS_WLAN

14

BT_ON

53

For EC to detect
debug card insert.

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1

C1517
0.1U_0402_16V4Z

C1518
0.1U_0402_16V4Z

R548
100K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R1567 1
R1568 1

FCH_SMCLK0_R
FCH_SMDAT0_R

@D

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
0_0402_5%
2
0_0402_5%
2

R1569 1
R1570 1

2 @ 0_0402_5%
2 @ 0_0402_5%

R1571 1
R1572 1

2 @ 0_0402_5%
2 @ 0_0402_5%

30,34,38,42

2
G

SUSP#

0_0402_5%
2
1 R1577 WLAN_LED#
BT_LED#
2
1
R1575
0_0402_5%

C1663
0.1U_0603_25V7K
@

WL_OFF# 14
WL_OFF#_EC 30
PLT_RST# 12,17,25

FCH_SMCLK0
FCH_SMDAT0

8,9,13
8,9,13

Reserve for SW mini-pcie debug card.


Series resistors closed to KBC side.

WLAN_LED# 30
BT_LED# 30

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

54

GND2

@
Q32
SSM3K7002FU_SC70-3
@

+3VALW
+3VS

USB20_N3 13
USB20_P3 13
WLAN_R_LED#
BT_R_LED#

2
0_0402_5%

R115

R1573
R1574
R1576
R1578
R1579
R1580

1
1
1
1
1
1

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

LPC_FRAME# 12,30
LPC_AD3 12,30
LPC_AD2 12,30
LPC_AD1 12,30
LPC_AD0 12,30
CLK_PCI_DB

BELLW_80003-1021

30 EC_TX_P80_DATA
30 EC_RX_P80_CLK

100_0402_1%
R1581
EC_TX_P80_DATA 1
2 EC_TX_P80_DATA_R
EC_RX_P80_CLK 1
2 EC_RX_P80_CLK_R
@ R1582
100_0402_1%
BT_ON R1566 1
2 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

@
C1516
0.1U_0402_16V4Z

2 0_0402_5%

12 CLK_PCIE_MINI1#
12 CLK_PCIE_MINI1

JMINI1

R1565 1
BT_ONR1594 1
@
MINI1_CLKREQ#

FCH_PCIE_WAKE#

1
R1564
0_0805_5%

13,25,30

1 0_1206_5%

R1563 2

AO3413_SOT23-3

+5VALW

Mini-Express Card(WLAN/WiMAX)

1 0_1206_5%

C1664
1U_0402_6.3V6K

+1.5VS

+3VS_WLAN

R1596

+3VALW
+3VS

Q31
3

12

R1583
100K_0402_5%

+5VALW

R654
10K_0402_5%

Add to prevent leakage issue.


1

LED

LED1

White
30,33 PWR_LED#

2
300_0402_5%

1
R1584

+5VALW

19-217/T1D-DP1Q2QY/3T 0603 WHITE


D26

Orange
30 CHARGE_LED1#

LED2

BATT_LOW_LED#

30 CHARGE_LED0#

White

PWR_LED#

2
1

BATT_CHG_LED#

O
W

2
300_0402_5%

1
R1585

+3VALW

2
300_0402_5%

1
R1586

+3VALW

3
YSDA0502C 3P C/A SOT-23
D36

HT-297DQ/GQ 0603 AMB/YG

CHARGE_LED1#

CHARGE_LED0#

@
1

D24
WLAN_R_LED#

Green
2

WLAN_D_LED#

RB751V_SOD323
@
D25
BT_R_LED#

LED3
1

2
300_0402_5%

1
R1588

+3VS

YSDA0502C 3P C/A SOT-23


D37
@

19-21SYGC/S530-E3/TR8 0603 Y/G

WLAN_D_LED#

SATA_LED#

RB751V_SOD323

30 RF_LED#

R1589

YSDA0502C 3P C/A SOT-23


D35

2 0_0402_5%

NUM_LED#

CAPS_LED#

@
1

LED4

Green
14 SATA_LED#

2
300_0402_5%

1
R1591

YSDA0502C 3P C/A SOT-23

+3VS

19-21SYGC/S530-E3/TR8 0603 Y/G

ESD
LED5

Green
30 NUM_LED#

2
300_0402_5%

1
R1592

+3VS

2
300_0402_5%

1
R1593

+3VS

19-21SYGC/S530-E3/TR8 0603 Y/G

LED6

Green
30 CAPS_LED#

19-21SYGC/S530-E3/TR8 0603 Y/G

Compal Secret Data

Security Classification

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P28-Mini PCIE/LED
Size

Document Number

Rev
1.0

LA-7322P
Date:

Compal Electronics, Inc.

Sheet

Thursday, February 17, 2011


E

28

of

47

SATA HDD Conn.


JHDD1

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

14 SATA_DTX_C_IRX_N0
14 SATA_DTX_C_IRX_P0

1
2
3
4
5
6
7

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

14 SATA_ITX_DRX_P0
14 SATA_ITX_DRX_N0

C1519 1
C1520 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

GND
A+
AGND
BB+
GND

+3VS
1

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS
C1472
0.1U_0402_16V4Z

R1595
1

+5VS

+5VS_HDD

2
0_0805_5%
10U_0603_6.3V6M
C660

0.1U_0402_16V4Z

C661

C662

C663

1U_0402_6.3V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12 GND1
V12 GND2
V12

23
24

SUYIN_127043FR022S21MZR

1000P_0402_50V7K

SATA ODD FFC Conn.


JODD1

14 SATA_ITX_DRX_P1
14 SATA_ITX_DRX_N1
C1521 1
C1522 1

14 SATA_DTX_C_IRX_N1
14 SATA_DTX_C_IRX_P1

80mils

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

R1598
1

+5VS
+3VS

+5VS_ODD
0_0805_5%
@
1
2
R629
10K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND
GND

15
14

OCTEK_SLS-13DC1G_RV

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

P29-HDD & ODD CONN


Size
B

Document Number

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011


G

Sheet

29
H

of

47

ID
+3VALW

R1602
2

+3VALW_EC
L1131
2
FBM-11-160808-601-T_0603

ECAGND

1
R1605

2
47K_0402_5%

12 LPC_CLK0_EC
12
A_RST#
13

2
C1533
0.1U_0402_16V4Z

2
47K_0402_5%
2
47K_0402_5%
2
100K_0402_1%
2
100K_0402_1%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

+3VALW

1
R1609
1
R1610
@
1
R1611
@
1
R1612
1
R1613
1
R1615
1
R1616
@
1
R1617
1
R1619
1
R35

A_RST#

EC_SCI#

KSO1
KSO2
SPI_SO
SPI_CS#
EC_SMB_CK1
EC_SMB_DA1
EC_MUTE#
EC_SMI#
USB_ON#
LID_SW#

+3VS

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

12
13
37
20
38

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

Vab

R02 ER

100K

34.8K 0.851V

R10 PR

100K

46.4K 1.045V

AVCC

+3VALW

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

PWM Output

PS2 Interface

21
23
26
27

Ra
BRDID
ACOFF

ACOFF

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

FAN_SET
IREF

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

USB_ON#
WLAN_LED#
BT_LED#
TP_CLK
TP_DATA

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

GPIO
SM Bus

ECAGND
2
100P_0402_50V8J

1
C1531

R1603 1

2 100K_0402_5%

R1606 1

2 46.4K_0402_1%

Rb
BATT_TEMP 35

ADP_I

36

BRDID
+5VS
TP_CLK

LID_SW#

SPI Device Interface


SPI Flash ROM

36

BATT_TEMP

63
64
65
66
75
76

DA Output

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

26.1K 0.683V

U47

AD Input

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

100K

SPI_SO_R
SPI_SI_R
SPI_CLK
SPI_CS#

FAN_SET 33
IREF
36
CHGVADJ 36
EC_MUTE# 26
USB_ON# 32
WLAN_LED# 28
BT_LED# 28
TP_CLK 31
TP_DATA 31

R1607 1

2 4.7K_0402_5%

TP_DATA R1608 1

2 4.7K_0402_5%

ACIN

1
C1534

2
100P_0402_50V8J
+3VALW

VGATE
13,43
EN_WOL 25
VLDT_EN 34
LID_SW# 33

R1614
10K_0402_5%

R1631
2
1 SPI_CLK_R
FBMA-10-100505-101T

13,25,28 FCH_PCIE_WAKE#

@
2
0_0402_5%

1
R1618

EC_PME#

1
EMI request 12.24
FSTCHG
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
SYSON
ACIN

FSTCHG 36
CHARGE_LED0# 28
CAPS_LED# 28
CHARGE_LED1# 28
PWR_LED# 28,33
SYSON
34,39
VR_ON
43
ACIN
36

C126
10P_0402_50V8J

2
@

SPI_CLK_R
2

35
35
5,18
5,18

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

BRD ID

+3VALW

C1532
1
2 R1604 1
@ 22P_0402_50V8J
@ 10_0402_5%

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

C1530
1000P_0402_50V7K

Rb

R01 SR

13
EC_GA20
13
EC_KBRST#
12
SERIRQ
12,28 LPC_FRAME#
12,28
LPC_AD3
12,28
LPC_AD2
12,28
LPC_AD1
12,28
LPC_AD0

+EC_VCCA

67

VCC
VCC
VCC
VCC
VCC
VCC

C1529
1000P_0402_50V7K

KSI[0..7]

C1528
1000P_0402_50V7K

14,31

C1527
0.1U_0402_16V4Z

KSI[0..7]

C1526
0.1U_0402_16V4Z

KSO[0..15]

C1525
0.1U_0402_16V4Z

KSO[0..15]
31

C1524
0.1U_0402_16V4Z

0_0805_5%

9
22
33
96
111
125

Ra

@
C1538
100P_0402_50V8J

@
C1537
100P_0402_50V8J

R138

RTC_CLK
100K_0402_5%

12,16

EC_SMB_CK2
EC_SMB_DA2

NUM_LED#

1
C125
2

1
R1628

NUM_LED#

XCLKI
XCLKO
2
0_0402_5%

122
123

GPI

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

XCLK1
XCLK0

D8
1

BKOFF# 10
WL_OFF#_EC 28
RF_LED# 28
VGA_ON 23

SUSP#
PBTN_OUT#

1
C1535

PE_GPIO1 12,23
ENBKL 10
EAPD
26
EC_THERM# 5
SUSP# 28,34,38,42
PBTN_OUT# 13

EMI request 12.24

FOR EC 128KB SPI ROM


(150mil PACKAGE) SA00002C100

EC_PWROK 13

1
2
1
2
+3VS
R1624 0_0402_5% R1625 10K_0402_5%

V18R

KB930QF A0 LQFP 128P

R516
33_0402_5%

@
RB751V_SOD323
2

EC_RSMRST# 13
EC_LID_OUT# 13
EC_ON
14,33

C1536
4.7U_0805_10V4Z
+3VALW

20mils
L114
ECAGND

1
2
FBM-11-160808-601-T_0603

C1539
0.1U_0402_16V4Z

R1629
10K_0402_5%
U48

1
C1540

15P_0402_50V8J

XCLKI

SUSP#

15P_0402_50V8J
@

CS#
SO
WP#
GND

VCC
HOLD#
SCK
SI

8
7
6
5

SPI_HOLD#
SPI_CLK_R

MX25L1606EM2I-12G_SO8

C1541

1
2
3
4

SPI_SI 1 R1632 2 SPI_SI_R


15_0402_5%

@
R1633
20M_0603_5%

OSC

@ Y5
1

2 SPI_SO
15_0402_5%

NC

1
R1630

XCLKO

32.768KHZ_12.5PF_9H03200413
3 NC
OSC 4
2

SPI_CS#
SPI_SO_R

Reserve for EC
Close to U47

22P_0402_50V8J

EC_LID_OUT#
EC_ON
EC_PME#
EC_PWROK_R
BKOFF#

28

@
R1627
2.2K_0402_5%

EC_TX_P80_DATA
EC_RX_P80_CLK

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

If Q8 or R429, R432 implemented,


R747 & R748 need to be mounted

INVT_PWM
FAN_SPEED

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

AGND

28 EC_TX_P80_DATA
28 EC_RX_P80_CLK
33
ON/OFF#

+3VS

@
R1626
2.2K_0402_5%

INVT_PWM
FAN_SPEED

EC_SMI#

69

10
33

SLP_S3#
SLP_S5#
EC_SMI#

GND
GND
GND
GND
GND

13
13
13

EC_SCI#

11
24
35
94
113

2
10K_0402_5%
2
10K_0402_5%

22P_0402_50V8J

1
R1622
1
R1623

BKOFF#

Compal Secret Data

Security Classification
@
C1542
1000P_0402_50V7K

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


P30-BIOS & EC KB930

Size Document Number


Custom
Date:

Friday, February 18, 2011

Rev
1.0

LA-7322P
Sheet

30

of

47

ACES_88514-02401-071

INT_KBD Conn.
KSI[0..7]

26
25

KSI[0..7]

KSO[0..15]

14,30

KSO7
KSO0
KSI1
KSI7
KSO9
KSI6
KSI5
KSO3
KSI4
KSI2
KSO1
KSI3
KSI0
KSO13
KSO5
KSO2
KSO4
KSO8
KSO6
KSO11
KSO10
KSO12
KSO14
KSO15

KSO[0..15] 30

KSO2

C1543 1

2 @ 100P_0402_50V8J

KSO1

C1544 1

2 @ 100P_0402_50V8J

KSO15

C1546 1

2 @ 100P_0402_50V8J

KSO7

C1545 1

2 @ 100P_0402_50V8J

KSO6

C1547 1

2 @ 100P_0402_50V8J

KSI2

C1548 1

2 @ 100P_0402_50V8J

KSO8

C1549 1

2 @ 100P_0402_50V8J

KSO5

C1550 1

2 @ 100P_0402_50V8J

KSO13

C1551 1

2 @ 100P_0402_50V8J

KSI3

C1552 1

2 @ 100P_0402_50V8J

KSO12

C1553 1

2 @ 100P_0402_50V8J

KSO14

C1554 1

2 @ 100P_0402_50V8J

KSO11

C1555 1

2 @ 100P_0402_50V8J

KSI7

C1556 1

2 @ 100P_0402_50V8J

KSO10

C1557 1

2 @ 100P_0402_50V8J

KSI6

C1558 1

2 @ 100P_0402_50V8J

KSO3

C1559 1

2 @ 100P_0402_50V8J

KSI5

C1560 1

2 @ 100P_0402_50V8J

KSO4

C1561 1

2 @ 100P_0402_50V8J

KSI4

C1562 1

2 @ 100P_0402_50V8J

KSI0

C1563 1

2 @ 100P_0402_50V8J

KSO9

C1564 1

2 @ 100P_0402_50V8J

KSO0

C1565 1

2 @ 100P_0402_50V8J

KSI1

C1566 1

2 @ 100P_0402_50V8J

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

GND2
GND1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JKB1

Pin define

CONN PIN define need double check

To TP/B Conn.
+5VS

ACES_88514-00601-071

C1567
0.1U_0402_16V4Z

30
30

TP_CLK
TP_DATATP_DATA
1
1
@
@
C1568
C1569
100P_0402_50V8J
100P_0402_50V8J
2
2

TP_CLK
TP_DATA

SW /L
SW /R

6
5
4
3
2
1

6
5
4
3
2
1
B

GND
GND

JTP1

D17

D28
@

8
7

YSDA0502C 3P C/A SOT-23

YSDA0502C 3P C/A SOT-23

Reserve for ESD

DTSGZML-63N-Q-T-R_5P
SW 5

DTSGZML-63N-Q-T-R_5P
SW 6
SW /R

4
5

SW /L

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


P31-KB /SW/TP/Lid

Size
B
Date:

Document Number

Rev
1.0

LA-7322P
Thursday, February 17, 2011

Sheet
1

31

of

47

Left USB Conn.

L54
13
13

USB20_P0

USB20_P0

USB20_N0

USB20_N0

1
4

USB20_P0_C

USB20_N0_C

+USB_VCCA

S COM FI_ KINGCORE WCM-2012HS-900T


C708
470P_0402_50V7K

L57
13

USB20_P1

13

USB20_N1

USB20_P1

USB20_N1

USB20_P1_C
USB20_N1_C

W=80mils

JUSB1
USB20_N0_C
USB20_P0_C

C709
47U_0805_6.3V

+USB_VCCA

C711
470P_0402_50V7K

JUSB2
USB20_N1_C
USB20_P1_C

C712
47U_0805_6.3V

USB_ON#

GND
IN
IN
EN#

OUT
OUT
OUT
OC#

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

SUYIN_020173MR004S50DZL
CONN@

+USB_VCCA

U54

1
2
3
4

GND1
GND2
GND3
GND4

W=80mils

+5VALW

10.1U_0402_16V4Z
30
USB_ON#

5
6
7
8

Left USB Conn.

EMI request

VCC
DD+
GND

SUYIN_020173MR004S50DZL
CONN@

S COM FI_ KINGCORE WCM-2012HS-900T

C707

1
2
3
4

8
7
6
5

USB_OC0# 13

AP2301MPG-13 MSOP 8P

Low Active

C710
@ 1000P_0402_50V7K

D20
USB20_P0_C

I/O4

I/O2

VDD

GND

I/O3

I/O1

USB20_P1_C

2
+5VALW

USB20_N0_C

USB20_N1_C
3

AZC099-04S.R7G_SOT23-6

For ESD request.

+5VALW

30
C1508

USB_ON#

USB_ON#

1
C1505

220P_0402_50V7K

+USB_VCCB

U55

2
2
220P_0402_50V7K

C714
0.1U_0402_16V4Z

1
2
3
4

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
OC#

AP2301MPG-13 MSOP 8P

Low Active

USB_OC1# 13

C713
@ 1000P_0402_50V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

P32-USB/BT/USBsub
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

32

of

47

ON/OFF switch

Power Button
+3VALW

Fan Control Circuit


+3VS

R495

ON/OFFBTN#

ON/OFF#

51_ON#

R653
10K_0402_5%

30
35

DAN202UT106_SC70-3

8
7
6
5

FAN_SPEED

Change to SC600000B00
C773

C702
1000P_0402_50V7K~N

R496

Q27
2
G

EC_ON

EC_ON

1000P_0402_50V7K
1

14,30

C701

C700

U53

D12

6
5

@ SW 4
SMT1-05-A_4P
1
3

+5VS

100K_0402_5%

Bottom Side

GND
GND
GND
GND

EN
VIN
VOUT
VSET

1
2
3
4

2
30

1000P_0402_50V7K~N

+5VS_FAN

APL5607KI-TRG_SO8

ACES_85205-0300N

2.2U_0603_106K

30

FAN_SPEED

FAN_SPEED

C703
10U_0603_6.3V6M

5
4

GND
GND

3
2
1

3
2
1
JFAN1

FAN_SET

SSM3K7002FU_SC70-3

10K_0402_5%

ON/OFFBTN#

H22
H_3P0
@

H13
H_3P0

H11
H_3P0

H20
H_3P0

H9
H_3P0

H15
H_3P0

1
3
PJSOT24CH_SOT23-3
D27

H18
H_4P2
@

H2
H_6P2X3P2

H19
H_4P2
@

H8
H_3P0

H17
H_4P2

H23
H_3P8

H16
H_4P2

H10
H_3P8

H7
H_3P8

H6
H_3P8

H5
H_3P8

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

Issued Date

2010/06/30

PCB

Compal Electronics, Inc.

Compal Secret Data

Security Classification

FD4

FD3

FD2

ZZZ
FD1

GND_LAN
H24
H25
H_3P2
H_3P3

220P_0402_50V7K

H14
H_3P0

C1523

H4
H_3P0N

ACES_85201-06051

H3
H_3P0

H1
H_3P0

PW R_LED# 28,30
+5VALW
LID_SW # 30
+3VALW

LID_SW #

JBTN1
1 1
2 2
3 3
4 4
5 5
6 6
GND 7
GND 8

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P33-Other IO/USB (right)


Size
Document Number
Custom

Rev
1.0

LA-7322P

Date: Friday, February 18, 2011

Sheet

33

of

47

+1.1VALW TO +1.1VS
+1.1VALW

R1101
150_0603_5%

10U_0603_6.3V6M
C1444
2
2
1U_0402_6.3V4Z

5VS_GATE

+5VALW

2
C1447

R1111
100K_0402_5%

10U_0603_6.3V6M
C1449
2
2
1U_0402_6.3V4Z

2
10U_0603_6.3V6M

VLDT_EN#

30

SUSP

+VSB

1
R1105

2
47K_0402_5%

1.1VS_GATE

SSM3K7002FU_SC70-3

Q56
2
G

SSM3K7002FU_SC70-3
R1107
10K_0402_5%
C1451

VLDT_EN#
0.1U_0603_25V7K

C1450

Q51
2
G

VLDT_EN

SSM3K7002FU_SC70-3

Q55
2
G

SUSP

Q53
2
G

2
47K_0402_5%

1
R1103

+VSB

R1104
C1448
1K_0402_5%

1
2
3

10U_0603_6.3V6M
2
2
10U_0603_6.3V6M

8
7
6
5

2
C1446

C1445

1
2
3

C1443

8
7
6
5

+1.1VS
U39
AO4478L 1N SO8

+5VS

U38
AO4478L 1N SO8

+5VALW

Change P/N SB00000HZ00

+5VALW TO +5VS

0.1U_0603_25V7K

SSM3K7002FU_SC70-3

+3VALW TO +3VS

Change P/N SB00000HZ00


+3VS

+3VALW

U41
AO4478L 1N SO8
2

+5VALW
+5VALW
2

0.1U_0603_25V7K

R1109
100K_0402_5%

28,30,38,42 SUSP#

Q59
2
G

1
1

Q52
2
G

C1456

SYSON

SSM3K7002FU_SC70-3

30,39

SUSP

SUSP

R1115
10K_0402_5%
2

11,41

SYSON#

SSM3K7002FU_SC70-3

SUSP

SSM3K7002FU_SC70-3

Q61
2
G

R1116
100K_0402_5%

R1108
100K_0402_5%
Q60
2
G

SSM3K7002FU_SC70-3

10U_0603_6.3V6M
C1455
2
2
1U_0402_6.3V4Z

R1110
300_0603_5%

3VS_GATE

1
200K_0402_5%
SUSP

2
R1112

+VSB

10U_0603_6.3V6M
2
2
10U_0603_6.3V6M

C1452

1 1

C1454

1
2
3

C1453

8
7
6
5

+1.5VS

C1463
0.1U_0603_25V7K

SUSP

2
G

SUSP

SSM3K7002FU_SC70-3

Q80

SSM3K7002FU_SC70-3

Q74
2
G

D
SYSON#

Q78
2
G

D
VLDT_EN#

SSM3K7002FU_SC70-3

Q28
2
G

1.5_VDDC_PWREN#

1.5_VDDC_PWREN#

24

VGA@
SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S
SSM3K7002FU_SC70-3
4

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

R1126
470_0603_5%
VGA@

D
Q67

2
G

R1128
470_0603_5%

1
200K_0402_5% 1

2
G
3

+VGA_CORE

SUSP#

Q65
3

D
D
R1122

R1137
470_0603_5%

R1135
470_0603_5%

R1120
470_0603_5%
1

C1461

10U_0603_6.3V6M
2

+1.1VS

100K_0402_5%

+0.75VS

2
2

R1121

+1.5V

+1.5VS

Q63
SI2301CDS-T1-GE3_SOT23-3

+1.5V

Title

P34-DC Interface
Size Document Number
Custom

Rev
1.0

LA-7322P

Date:

Thursday, February 17, 2011

Sheet
E

34

of

47

PL1
HCB2012KF-121T50_0805
1
2

X7R type

PC5
0.1U_0603_16V7K

PR1
22K_0402_1%

PC4
100P_0402_50V8J

PU1
1

VCC TMSNS1

GND RHYST1

OT1 TMSNS2

OT2 RHYST2

OTP_N_001
OTP_N_002

1
PR2

22.1K_0402_1%

1
2

VL

PC3
1000P_0402_50V7K

@ACES_88323-0471

PC2
100P_0402_50V8J

PC1
1000P_0402_50V7K

PH1 under CPU botten side :


CPU thermal protection at 92 +-3 degree C
Recovery at 80 +-3 degree C

VIN

PL2
HCB2012KF-121T50_0805
1
2

ADPIN

PJPDC1

OTP_N_003

VMB

PJP2

@SUYIN_200275MR009G186ZL

VS_ON 37

0_0402_5%

BATT+

PC6
1000P_0402_50V7K

1
2

2
PD1

PC7
0.01U_0402_25V7K

PR27
1K_0402_1%
2

GND
GND

B/I
EC_SMCA
EC_SMDA
TS_A

PH1
100K_0402_1%_NCP15W F104F03RC

PR4
PL4
HCB2012KF-121T50_0805
1
2

1
2
3
4
5
6
7
8
9

@PJSOT24CW_SOT323-3

10
11

G718TM1U_SOT23-8
2

PL3
HCB2012KF-121T50_0805
1
2

1
2
3
4
5
6
7
8
9

PD2

VL

PR13
100K_0402_1%
BATT_TEMP 30

1K_0402_1%
37,40

SPOK

PR16
0_0402_5%
2VSB_N_002 2
G

VSB_N_001

VIN

PQ1
TP0610K-T1-GE3_SOT23-3

PQ2
SSM3K7002FU_SC70-3

PC10
0.1U_0402_16V7K

1VSB_N_003

+3VALW

100K_0402_5%
PR30

PR12
22K_0402_1%
1
2

PC9
0.1U_0603_25V7K

EC_SMB_DA1 30
PR29

+VSBP

EC_SMB_CK1 30

@PJSOT24CW _SOT323-3

PC8
0.22U_0603_25V7K

1
PR31
100_0402_1%

2
1
PR10
100K_0402_1%

PR28
100_0402_1%
1
2

B+

1
3

PD3
RLS4148_LL34-2
VS_N_001
1

+VSB

(120mA,40mils ,Via NO.= 1)

PR18
68_1206_5%

VS

PC12
0.1U_0603_25V7K

PC11
0.22U_0603_25V7K

PR21
100K_0402_1%

JUMP_43X39

PQ3
PR17
TP0610K-T1-GE3_SOT23-368_1206_5%
N1

PD4
RLS4148_LL34-2

BATT+

PJ2
+VSBP

33

2
PR22
22K_0402_1%

51_ON#

VS_N_002

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DCIN / BATT CONN / OTP


Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B


Date:

Friday, February 18, 2011

Sheet
D

35

of

44

21

ICOMP

CSIN

20

VCOMP

CSIP

19

ICM

PHASE

18

LX_CHG

VREF

UGATE

17

DH_CHG

CHG_CHLIM

CHLIM

BOOT

16

6251aclim

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

GND

PGND

13

Rtop

30 CHGVADJ

PR128
20K_0402_1%

12

26251VDD

1
2

PD106
RB751V-40TE17_SOD323-2

6251VDDP
DL_CHG

PC121
0.1U_0603_25V7K
BST_CHGA 2
1
1CHG_SNUB2

PR127
226K_0402_1%
6251VREF 1
2

PQ110

PR126
0_0603_5%
BST_CHG 1

2 ACPRN
G
PQ109
@SSM3K7002FU_SC70-3
2

PL101
PR102
10UH_MSCDRI-104A-100M-E_4.6A_20% 0.02_1206_1%
CHG
1
2
1
4

5
6251VREF

PC114
@2200P_0402_25V7K

PQ108
AON7408L_DFN8-5

PR122
2.2_0603_1%

1
2
PC120
0.1U_0402_16V7K

PC106
2200P_0402_25V7K

PC125
@10U_0805_25V6K
2
1

PC105
0.1U_0402_25V6
2
1

CSOP

CHG_N_006

D
5

CSON

CHG_N_001

BATT+

3
PC101
10U_0805_25V6K
2
1

CHG_VCOMP

1CHG_N_0081

CSOP

100_0402_1%
2 CHG_ICM 7

PR111
14.3K_0402_1%

1
2

CELLS

DCIN

PR125
@4.7_1206_5%

PR123

PC110
1000P_0402_50V7K
2
1

22

AON7406L_DFN8-5

PR129
4.7_0603_5%
PC123
4.7U_0805_6.3V6K

CSON

PR118
20_0603_5%
CHG_CSON 1
2
PC113
0.047U_0603_16V7K
CHG_CSOP 1
2
PR119
20_0603_5%
CHG_CSIN
2
1
PC118
PR120
0.1U_0603_25V7K
20_0603_5%
CHG_CSIP
1
2

3
2
1

PR104
140K_0402_1%

EN

PQ106
DTC115EUA_SC70-3

ACPRN

PQ111
DTC115EUA_SC70-3

PR115
100K_0402_1%
1
2

ISL6251AHAZ-T QSOP 24P

PR105
10K_0402_1%
1
2
1

ACOFF

ACOFF

23

PR103
150K_0402_1%

PC122
0.01U_0402_25V7K
2
1

IREF

30

ADP_I

ACSET ACPRN

30

30

10K_0402_1%
2
1

PC120 must close EC pin.

6800P_0402_25V7K
CHG_ICOMP
2

PR121
1

0.01U_0402_25V7K

PACIN

PR124
22K_0402_5%
1
2

24

DCIN

VIN

PC124
@680P_0402_50V7K

PC117
1
2

VDD

PC112
1U_0603_25V6K
1
2

CHG_N_009

6251_EN
PR130
0_0402_5%
1
2

PR110
47K_0402_1%
1
2
PR112
10K_0402_1%

3
2
1

PC116
1

SSM6N7002FU_US6

10_1206_5%

PQ107B

2S: Float
3S: GND

PU101

CHG_N_005

SSM6N7002FU_US6

PR113

CHG_VADJ

3CHG_N_002

PQ107A
2

CHG_VIN 1

PC109
2.2U_0603_6.3V6K
2
1
PR117

PR116
150K_0402_1%

100K_0402_1%

FSTCHG

ACSETIN

PD101

PC104
10U_0805_25V6K
2
1

1
1
2

30

RB751V-40TE17_SOD323-2

ACSETIN

PR114
10K_0402_1%
2
1

CHG_N_001

PQ105
DTC115EUA_SC70-3

PR108
191K_0402_1%
1
2

6251VDD

CHG_N_003

CSIN

CSIP

PR107
200K_0402_1%

PC108
0.1U_0603_25V7K

PR109
47K_0402_1%

1CHG_N_010

PQ104
DTA144EUA_SC70-3

PQ103
AO4407AL 1P SO8
8
7
6
5

1
2
3

VIN

8
7
6
5

B+
CHG_B+

PL102
@HCB2012KF-121T50_0805
1
2
PC103
4.7U_0805_25V6K
2
1

1
2
3

8
7
6
5

PR101
0.02_1206_1%
1
4

PC107
5600P_0402_25V7K
1
2

VIN

P3

PQ102
AO4409L_SO8
1
2
3

P2

PQ101
AO4435L_SO8

PC102
10U_0805_25V6K
2
1

B+

1.2UH_1127AS-1R2N_2.4A_30%

(B+ 6A,240mils ,Via NO.= 12)

PL103

10U_0805_25V6K
PC129
2
1

4.7U_0805_25V6K
PC128
2
1

PR106
22K_0402_1%

6251VDD

PR131
47K_0402_1%

PR132
10K_0402_1%

ACIN

30

PACIN

ACPRN

PQ112

2
B

Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K


90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N

CP= 85%*Iada;

PR133
10K_0402_1%
1
2

PR136
20K_0402_1%

Add

E
MMBT3904W H NPN SOT323-3

CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A

CC=0.25A~3A

CHGVADJ=(Vcell-4)/0.10627

IREF=1.016*Icharge

Vcell

IREF=0.254V~3.048V

4V

VCHLIM need over 95mV

4.2V

CHGVADJ
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0V
1.882V

2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CHARGER
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B


Date:

Friday, February 18, 2011


D

Sheet

36

of

44

2VREF_6182

LX_5V

19

LG_5V

2
35,40

4
SNUB_5V

18

1
2

PQ306

SPOK
17

PC306
10U_0805_25V6K

PL305
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
1

UG_5V

20

S IC RT8205LZQW(2) WQFN 24P PWM

EN0
3
2
1

AON7406L_DFN8-5

+ PC305
220U_6.3VM_R15

1
1
PC318
4.7U_0805_10V6K

1
PC320
1U_0603_10V6K

+5VALWP

AO4406AL_SO8

VL

1
2

PR315
95.3K_0402_1%

PR313
4.7_1206_5%

21

3
2
1

22

4
PR309
PC315
2.2_0402_5%
0.1U_0402_10V7K
BST_5V 1
2 BST1_5V 1
2

PC317
680P_0402_50V7K

LGATE1

23

PQ305
AON7408L_DFN8-5

5
6
7
8

LGATE2

24

NC

PHASE1

VREG5

PHASE2

PC312
2200P_0402_50V7K
2
1

ENTRIP1
2

1
ENTRIP1

FB1

REF

BOOT1
UGATE1

PR314
499K_0402_1%
2

B++

PR307
162K_0402_1%
2

UGATE2

EN

BOOT2

13

B++

PR306
20K_0402_1%
2

PGOOD

VIN

12

PR305
30.9K_0402_1%
2

VO1

VREG3

16

1
2
3

LG_3V
PQ304

PC316
680P_0402_50V7K
2
1 SNUB_3V

11

1
PC303
220U_6.3VM_R15

LX_3V

+3VALWP

PR312
4.7_1206_5%

PL303
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
2
1

VO2

15

1
2
3

PC314
8
0.1U_0402_10V7K
PR308
BST1_3V 1
1
2
2 BST_3V 9
2.2_0402_5%
UG_3V 10

TONSEL

P PAD

GND

25
2

ENTRIP2

PU301

PC313
10U_0805_6.3V6M

FB2

PQ303
AON7408L_DFN8-5

SKIPSEL

1
2

PC304
4.7U_0805_25V6K

PC310
2200P_0402_50V7K
2
1

PR303
140K_0402_1%
1

FB_5V 1

ENTRIP2

+3VLP

2
PC309
0.1U_0402_25V6
2
1

1
2

PC322
@680P_0402_50V7K

FB_3V

14

PL301
HCB2012KF-121T50_0805
1

PR302
20K_0402_1%
1
2

B++

B+

PC311
0.1U_0402_25V6
2
1

PR301
13.7K_0402_1%
1

PC308
1U_0603_16V6K

B++
3

PC319
0.1U_0603_25V7K

N_3_5V_001

D
PQ307A
SSM6N7002FU_US6

ENTRIP2

ENTRIP1

2VREF_6182

PQ307B
SSM6N7002FU_US6

+3VLP
1

+5VALWP

+CHGRTC
PJP302

PJP305
2

+5VALW

(11A,440mils ,Via NO.= 22)

1
PAD-OPEN 2x2m

PAD-OPEN 4x4m
PJP306
1

VL

VL
PJP301

PAD-OPEN 4x4m

PJP303
PQ308
DTC115EUA_SC70-3

+3VALWP

+3VALW

(4A,120mils ,Via NO.= 8)

PAD-OPEN 4x4m

EC:+3VL, reserve PR319, install PR318, PR320 100K


EC:+3VALW, reserve PR318, install PR319, PR320 42.2K

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

1
PAD-OPEN 2x2m

PC321
2.2U_0603_10V6K

PR317
100K_0402_5%

PR319
100K_0402_1%

2
1
PR320
42.2K_0402_1%

VS

35 VS_ON

Title

Compal Electronics, Inc.


3.3VALWP/5VALWP

Size Document Number


Custom
Date:

Rev
0.1

LAXXXX

Friday, February 18, 2011

Sheet
E

37

of

44

1
2

<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V

PC402
22U_0805_6.3VAM

1
PR402
10K_0402_1%

PC401
22U_0805_6.3VAM

SY8033BDBC_DFN10_3X3

PR401
20K_0402_1%

PC404
68P_0402_50V8J
2
1

1.8VSP_FB

NC

TP

PR405
@47K_0402_5%

11

EN_1.8VSP

PR404 0_0402_5%

FB

+1.8VSP

EN

LX

PR403
4.7_1206_5%

SVIN

PC405
@0.1U_0402_10V7K

30,34,41,42 SUSP#

PL401
1UH_PCMC063T-1R0MN_11A_20%
1
2

1.8VSP_LX

PVIN

PC406
680P_0402_50V7K
SNUB_1.8VSP
2
1

LX

NC

PVIN

PC403
22U_0805_6.3VAM

10

1.8VSP_VIN

PU401

HCB1608KF-121T30_0603
1
2

PG

PL402
+5VALW

PJP401
+1.8VSP

+1.8VS

(2.5A, 100mils, Via NO.= 5)

PAD-OPEN 3x3m

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

+1.8VSP
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B


Date:

Friday, February 18, 2011

Sheet
D

38

of

44

1.5V_B+
PR503

30,34 SYSON

0_0402_5%

B+

PL502
HCB1608KF-121T30_0603
2
1

EN_1.5V

PR502
2.15K_0402_1%

3
2
1
11
10

LGATE

TRIP_1.5V 1

PR508

+5VALW
LG_1.5V

1
2

PC502
@680P_0402_50V7K

1
2

1
2

2200P_0402_50V7K
PC506

1
2

PC504
@4.7U_0805_25V6-K

PC507
0.1U_0402_25V6

+1.5VP
C

15.4K_0402_1%

+5VALW

PGOOD

CS
VDDP

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

PQ502

PC510
4.7U_0805_10V6K

1
+ PC501
220U_6.3VM_R15

FDS6690AS-G_SO8

3
2
1

RT8209MGQW _W QFN14_3P5X3P5

PR509
@4.7_1206_5%

PHASE

LX_1.5V

FB

UG_1.5V

12

1SNUB_1.5V

NC

14

VDD

13

PQ501
AON7408L_DFN8-5

PC511
@680P_0402_50V7K

2.21K_0402_1%

PC509
4.7U_0603_10V6K

FB_1.5V

5
6
7
8

PR501

PGND

+1.5VP

V5FILT_1.5V

PR507
100_0402_1%

+5VALW 1

VOUT

GND

+1.5VP

UGATE

TON

PC508
0.1U_0402_10V7K

BOOT

EN/DEM

PU501
PR506
255K_0402_1%
1
2TON_1.5V

15

PR504
2.2_0402_5%
BST_1.5V 1
2BST1_1.5V

+5VALW

PC503
10U_0805_25V6K

PC505
@0.1U_0402_10V7K

PJP502

2
@PAD-OPEN 4x4m
PJP501

+1.5VP

+1.5V

(8A,320mils ,Via NO.= 16)

@PAD-OPEN 4x4m

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


+1.5VP

Size

Document Number

Rev
0.1

LAXXXX
Date:

Friday, February 18, 2011

Sheet
1

39

of

44

1.1V_B+
PR703

SPOK

0_0402_5%

PL702
HCB1608KF-121T30_0603
2
1

EN_1.1V

1
PC704
@0.1U_0402_10V7K

B+

3
2
1
TRIP_1.1V 1

VDDP

10

LGATE

PR708
+5VALW

+5VALW

PQ702

PC709
4.7U_0805_10V6K

FDS6690AS-G_SO8

LG_1.1V

15.4K_0402_1%
2

3
2
1

RT8209MGQW _W QFN14_3P5X3P5

PC706
0.1U_0402_25V6

PC705
2200P_0402_50V7K
2
1

PC702
10U_0805_25V6K
2
1

PC703
@4.7U_0805_25V6-K
2
1

11

+1.1VALWP

1
+

PR706
@100K_0402_5%

CS

PL701
1UH_PCMC063T-1R0MN_11A_20%
1
2

PHASE

LX_1.1V

PR709
@4.7_1206_5%

UG_1.1V

12

1SNUB_1.1V

14

NC

BOOT

13

PQ701
AON7408L_DFN8-5

5
6
7
8

PGOOD

UGATE

FB

PC701
220U_6.3VM_R15

PC710
@680P_0402_50V7K

PR702
10K_0402_1%

5
FB_1.1V

2
2

PC707
0.1U_0402_10V7K

VDD

PGND

PR701

4.64K_0402_1%

VOUT

+1.1VALW P

PC708
4.7U_0603_6.3V6M

1
1

PR707
100_0603_1%
C

V5FILT_1.1V

+5VALW 1

TON

+1.1VALW P

EN/DEM

PR705
255K_0402_1%
1
2TON_1.1V

GND

PU701

15

PR704
2.2_0402_5%
BST_1.1V 1
2 BST1_1.1V 1

+5VALW

35,37

PJP701
+1.1VALW P

+1.1VALW

(8A,320mils ,Via NO.=16)

PAD-OPEN 4x4m
B

Compal Secret Data

Security Classification
2009/12/01

Issued Date

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR+1.1VALWP

Size
Document Number
Custom

Rev
0.1

LAXXXX

Date:

Friday, February 18, 2011

Sheet
1

40

of

44

+1.5V

+1.1VALW TO +1.05VSP
PU601

VOUT

NC

TP

8
7
6
5

1
2

PC603
1U_0603_10V6K

APL5336KAI-TRL_SOP8P8

PC609
4.7U_0603_6.3V6K

VREF_G2992

1
2
3

VREF VCNTL

GND

PQ601
IRF8707GTRPBF_SO8

PC602
1U_0402_6.3V6K

PR601
1K_0402_1%

+1.05VSP_L

+3VALW

PC608
4.7U_0603_6.3V6K

NC

NC

VIN

PC601
4.7U_0805_6.3V6K

+1.1VALW

1
D

PR603
1
2
47K_0402_5%

+VSB

PQ603
2
G

SUSP
PC616
@0.1U_0402_10V7K

1
PR605
330K_0402_5%

PC605
10U_0805_6.3V6M

PC607
0.1U_0402_25V6

PR602
1K_0402_1%

2
G

0_0402_5%

10.75VS_N_002

2
1
PC604
0.1U_0402_16V7K

PR604

11,34 SUSP

PQ602
SSM3K7002FU_SC70-3

+VSB1

+0.75VSP

SSM3K7002FU_SC70-3
+3VALW
2

PC606
@0.1U_0402_10V7K

PR606
@100K_0402_1%

G
S

PQ604A
@SSM6N7002FU_US6

2 +1.05VSP_N001

PJP601
1

(2A,80mils ,Via NO.= 4)

+0.75VS

+1.05VSP_N002

PQ604B
S
@SSM6N7002FU_US6

VGA_PWRGD 12,23,42,44C

@0_0402_5%

+0.75VSP

PR607
G

PAD-OPEN 3x3m

PC610
@0.1U_0402_10V7K

PJP602
+1.05VSP_L

+1.05VS

(5A,200mils ,Via NO.=10)

PAD-OPEN 4x4m

Need to confirm with HW power sequence.


+5VALW

PC613
0.1U_0402_25V6

1
2

PR611
7.32K_0402_1%

+1.0VSP
PR610
1.82K_0402_1%

FB

GND

3
4

PC615
22U_0805_6.3V6M

PD601
1

VOUT
VOUT

2
1

VGA_PWR_ON

EN
POK

30,34,38,42

8
7

PC614
180P_0402_50V8J

2
1

PR609
100K_0402_1%
1
2

APL5930KAI-TRG_SO8

VCNTL
VIN
VIN

PU602
6
5
9

1
PR608
@1K_0402_1%

PC611
4.7U_0805_6.3V6K

+3VS

PC612
1U_0603_10V6K

+1.5VP

1SS355_SOD323-2

PJP603
1

+1.0VSP

+1.0VSG

(2.5A,100mils ,Via NO.= 5)

PAD-OPEN 3x3m

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR 0.75VSP +1.05VSP

Size

Document Number

Rev
0.1

LAXXXX
Date:

Friday, February 18, 2011

Sheet
1

41

of

44

PL802

1
2

PC802
@22U_0805_6.3VAM

1
2

PC804
@68P_0402_50V8J
2
1

1
1
PR802
@10K_0402_1%

PC801
@22U_0805_6.3VAM

@SY8035DBC_DFN10_3X3

PR801
@7.5K_0402_1%
2

1.05VSP_FB

+1.05VSP

PR805
@47K_0402_5%

LX
FB

11

EN_1.05VSP

PR804 @0_0402_5%

SNUB_1.05VSP

EN

LX

1.05VSP_LX

SS

TP

PR803
@4.7_1206_5%

SVIN

LX

PC806
@680P_0402_50V7K

@0_0402_5%
1

PL801
@1UH_PCMC063T-1R0MN_11A_20%
1
2

PVIN

PC805
@0.1U_0402_10V7K

30,34,38,41 SUSP#

PC803
@22U_0805_6.3VAM

PR806

12,23,41,44 VGA_PWRGD

PU802
10 PVIN

1.05VSP_VIN

PG

@HCB1608KF-121T30_0603
1
2

+5VALW

PJP801
+1.05VSP

+1.05VS

(5A,200mils ,Via NO.=10)

PAD-OPEN 4x4m

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

+1.05VSP
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B


Date:

Friday, February 18, 2011

Sheet
D

42

of

44

PC235
68P_0402_50V8J
1
2

PR226
100_0402_5%
2
1

PC236
470P_0402_50V8J
1
2

APU_VDD0_RUN_FB_H 45

PR234
0_0402_5%
2
1

PC238
@68P_0402_50V8J

PC237
@68P_0402_50V8J

PC239
@68P_0402_50V8J

+APU_CORE 45

PR230
0_0402_5%

COMP

+5VS

PR232
10K_0402_1%
1
2

PR231
47K_0402_1%
1
2

PR252
10K_0402_1%

APU_VDD0_RUN_FB_L 45

PR236
100_0402_5%

FB

RGND

CPU_B+
2

25

LGATE0

PHASE0

22

UGATE0

PC249
2200P_0402_50V7K
2
1

PC247

PC243
2200P_0402_50V7K
2
1

@68U_25V_M_R0.44

PC245
0.1U_0402_25V6
2
1

10U_0805_25V6K
PC244

PR242
2.43K_0402_1%
1
2
PR244
2.43K_0402_1%
1
2

+CPU_CORE
Imax=7.7A
Ipeak=11A
Iocp(minimum)=13.2A
DCR=4.2mohm
Rdson = 7mohm

PC242
0.1U_0402_25V6
PR246

21

BOOT0

ISN0

1
2
1

2
0_0402_5%

10uF_0603 * 7
1uF_0402 * 4
0.1uF_0402 * 5
180P_0402 * 2
390uF * 3
Reserve 330uF * 2

PC241
0.1U_0402_25V6

BOOT_NB 2

PR206
2.2_0603_5%

PR222
10K_0402_1%
1
2

PR223
47K_0402_1%
1
2

PC211
2200P_0402_50V7K

(10A, 400mils, via no = 20)


3
2
1

PHASE_NB
5
6
7
8

COMP_NB
PC227
@68P_0402_50V8J

PQ203
AO4468L_SO8
LGATE_NB

FB_NB

PC206
0.1U_0402_25V6
2
1

2
4

PC228
@68P_0402_50V8J
RGND_NB

PL202
1
2
1UH_MMD-06CZ-1R0M-V1_11A_20%

+APU_CORE_NB

1
+
PR213
2K_0402_1%
2
1
PR251
8.2K_0402_1%
1
2

ISP_NB

PR225
1

PC216
0.22U_0603_10V7K

3
2
1

PR224
0_0402_5%
1
2

PC229
@68P_0402_50V8J

PC204
@4.7U_0805_25V6-K
2
1

PC215
0.1U_0402_25V6
2
1

PR210
1SNUB_NB2
1
4.7_1206_5%
PC220
680P_0603_50V7K

APU_VDD0_RUN_FB_L

PC226
68P_0402_50V8J
1
2

PR220
0_0402_5%
1
2
2

45 APU_VDDNB_RUN_FB_H

PC225
470P_0402_50V8J
1
2

45 +APU_CORE_NB

PR219
100_0402_5%
1
2

PQ202
AON7408L_DFN8-5

1 2

2
1
130K_0402_1%

TON_NB

PR205

PR207
1_0402_5%

1
PC205
10U_0805_25V6K

CPU_B+

2
1

PC203
1U_0603_10V6K

2
PC231
1
2

(14A, 560mils, via no = 28)

ISP0

BOOT_NB

PHASE_NB

20

15
RGND_NB

19

14
ISN_NB

BOOT_NB

13
ISP_NB

UGATE_NB

12
TON_NB

BOOT0

18

COMP_NB
11
COMP_NB

FB_NB

UGATE_NB

UGATE0

23

UGATE_NB

45

PC218
220U_6.3VM_R15

PC222
1

10uF_0603 * 6
1uF_0402 * 5
0.1uF_0402 * 4
180P_0402 * 2
390uF * 1
Reserve 390uF

PR217
ISN_NB
PC223
0.1U_0402_25V6

0_0402_5%

Compal Secret Data

Security Classification

Issued Date

2009/12/01

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


PWR-CPU_CORE

Size
C
Date:

+CPU_CORE_NB
Imax=7A
Ipeak=10A
Iocp(minimum)=12A
DCR=10mohm
Rdson = 22mohm

0.1U_0402_25V6

100_0402_5%

+APU_CORE

4.7_1206_5%

1SNUB_CPU
2

LGATE0

24

PC232
@0.01U_0402_25V7K

@0.01U_0402_25V7K
1
2

2
1

PR240
22K_0402_1%

PC252
1U_0603_10V6K

+
2

PR249

26

PR221
0_0402_5%
1
2

PQ205
AO4726L_SO8

680P_0603_50V7K
PC251

27

PVCC

29
28

PL204
0.47UH_MMD-06CZ-R47M-V1_17.5A_20%
1
2

3
2
1
PHASE0

VCC

PR202
2_0603_5%

OCSET_NB

PR239
5.1K_0402_1%

UGATE0

3
2
1

1
PGND0

OCSET_NB

FB_NB

B+

+3VS

VFIX/DRPSEL

PHASE0

32

31
BOOT1

ISP1

ISN1

33

34
RGND

35
ISN0

37

38

36
ISP0

TON

COMP

39

40

LGATE0

VFIX/DRPSEL

1
PR229
33K_0402_1%

PR228
10K_0402_1%

PVCC

RT8870AZQW_WQFN40_5X5

PGOOD

2
2

+5VS

FB

41

PWORK

PHASE_NB

0_0402_5%

PR255
10K_0402_1%

9
10

+5VS

7
8

OCSET_NB
VCC

LGATE1

LGATE_NB

PR235

45,52 VGATE

VFIX/DRPSEL

PGND1

SVD

17

H_PWRGD_L

5
PGOOD

SVC

PGND_NB

FCH_PWROK

45

PQ206
AON7408L_DFN8-5

5
6
7
8
4

16

45

PHASE1

LGATE_NB

45 APU_SVD

EN

30

2
3

1
2
0_0402_5%
PR238
1
2
0_0402_5%
1
2
PR233 @0_0402_5%
1
2

BOOT0
PR250
2_0603_5%

UGATE1

RGND_NB

ENABLE

PR227

45 APU_SVC

PC250
PR248
0.1U_0402_25V6
2.2_0603_5%
2
1
2
1
PC240
0.22U_0603_10V7K

+5VS

RBIAS

ISN_NB

+1.5V

ISP_NB

PR237
@51_0402_1%
1
2
PR241
@51_0402_1%
1
2

RBIAS

TON_NB

PR208
100K_0402_1%
1
2

OCSET

PC234
@0.01U_0402_25V7K

45 VR_ON

GND

PU201

PR245
110K_0402_1%
1
2

TON

2
1

ISN0

ISP0

TON

OCSET

PC230
0.1U_0402_25V6

PR254
@10K_0402_1%

PC246
@4.7U_0805_25V6-K
2
1

PR247
1_0402_5%

ISN1

ISP1

+3VS

PL205
HCB2012KF-121T50_0805
2
1

PR256
10K_0402_1%
1

PC253
@0.01U_0402_25V7K

PR253
7.15K_0402_1%

+5VS

Document Number

Rev
0.1

LAXXXX
Friday, February 18, 2011

Sheet
1

43

of

44

EN_VGA

PL902

TRIP_VGA

VDDP

10

LGATE

1
PR923
0_0402_5%

1
2

+5VALW

2
PR905
11K_0402_1%

1
2

1
2

1
2

1
+

PR912
@4.7_1206_5%

PC911
4.7U_0805_10V6K

1SNUB_VGA

LG_VGA

RT8209BGQW _W QFN14_3P5X3P5
PQ906
TPCA8059-H_PPAK56-8-5

(14A, 560mils, via no = 28)

VGA_PW RGD 12,23,41,42

+VGA_CORE

11

PL901
0.56UH +-20% PCMC104T-R56MN 25A
1
2

CS

3
2
1

LX_VGA

PC913
@680P_0402_50V7K

12

NC

7
PR911
100K_0402_1%

PC912
0.1U_0402_10V7K

2
1

+VGA_CORE

PR902
10K_0402_1%

PR914 pin2 trace need to close VGA chipset


MLCC.(remote sense)
PC912 pin1 trace need to close PC901. (local
sense.)

+3VS
PR917
15K_0402_1%
2
1

2
1
PR919

0.9V

1.05V

1.1V

PR904
30.1K_0402_1%
1
2 N_VGA_006 3

PQ904B
SSM6N7002FU_US6

18 GPU_VID0

+VGA_CORE

PC915
PQ904A
0.022U_0402_16V7K
SSM6N7002FU_US6

GPU_VID0

N_VGA_005

1
1

PR920
15K_0402_1%
2

10K_0402_5%
N_VGA_002

PQ903B
SSM6N7002FU_US6

PR903
10.5K_0402_1%
1
2 N_VGA_004 3

1
1
PR918
10K_0402_5%

GPU_VID1

PC914
0.022U_0402_16V7K

PQ903A
SSM6N7002FU_US6

18 GPU_VID1

N_VGA_003

N_VGA_001

PR916
10K_0402_5%
1
2

GCORE_SEN

PHASE

3
2
1

20 GCORE_SEN

UG_VGA

PGOOD

13

FB

14

15

BOOT

VDD

PGND

+3VS

PR914
100_0402_5%

EN/DEM

VOUT

4
NTMS4816NR2G_SO8

UGATE

PR907
PC909
2.2_0402_1%
0.1U_0402_10V7K
<BOM Structure>

PC902
4.7U_0805_6.3V6K

PC910
1U_0603_10V6K

FB_VGA

1
2
PR901
2K_0402_1%

+VGA_COREP1

TON

B+

PC901
390U_2.5V_M

V5FILT_VGA

GND

PR909
255K_0402_1%
1
2 TON_VGA

Need to close PC901


+VGA_CORE

1
5
6
7
8

1+5VALW
2

PU901

PC907
2200P_0402_50V7K

PR908
316_0402_1%

2BST1_VGA

PC904
4.7U_0805_25V6K

PQ901
BST_VGA 1

PC903
4.7U_0805_25V6K

+5VALW

PC906
0.1U_0402_25V6

VGA_B+

PC905
@0.1U_0402_10V7K

HCB1608KF-121T30_0603
1
2

PC908
@680P_0402_50V7K

23,34 1.5_VDDC_PWREN

PR922
0_0402_5%
1
2

PR921
10K_0402_5%

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


VGA_CORE

Size

Document Number

Rev
0.1

LAXXXX
Date:

Sheet

Friday, February 18, 2011


D

44

of

44

POWER SEQUENCE

ACIN/BATT-IN
+5VALW/+3VALW/+1.1VALW
D

EC_RSMRST#

T>20ms

PBTN_OUT#

EC to FCH

FCH to EC

SLP_S5#

SLP_S3#

FCH to EC

Delay SLP_S5# 10ms

SYSON

+1.5V
Delay SLP_S3# 10ms

SUSP#
+5VS/+3VS/+1.8VS

+1.05VS/+0.75VS

VLDT_EN

Delay SUSP# 10ms

+1.1VS

Delay SUSP# 10ms

VGA_ON
1.5_VDDC_PWREN

AND from VGA_ON & PX_EN

+VGA_CORE/+1.5VSG

+1.8VSG/+1.0VSG

T<20ms

+3VSG to +1.0VSG power up

VGA_PWRGD
VR_ON

VGA_ON Delay 20ms

+APU_CORE/+APU_CORE_NB

VGATE

EC_PWROK

PLT_RST#

AND from PLT_RST# & PE_GPIO0

VGA_RST#

Security Classification
Issued Date

Compal Secret Data


2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Power Sequence
Size

Document Number

Rev
1.0

LA-7322P
Date:

Thursday, February 17, 2011


1

Sheet

45

of

47

Version change list (P.I.R. List)


Item

Fixed Issue

Page 1 of 1 for HW
Reason for change

Rev.

PG#

Modify List

Date

Phase

TP FFC error

0.11

PG#31

Swap JTP1 pin define

12/15

ER

SW5 SW6 footprint error

0.11

PG#31

Update SW5 SW6 footpint

12/15

ER

FAN module connecter pin define error

0.11

PG#33

Swap JFAN1 pin define

12/15

ER

DFB request to update footprint

0.11

PG#26
PG#33

Update JBTN1& JSPK1 footprint

12/15

ER

LID issue

0.11

PG#13

R930 change to pop

12/15

ER

LID issue

0.11

PG#30

LID_SW# added a pull up 10Kohm. (R35)

12/15

ER

Update Broad ID

0.11

PG#30

Change R1606 from 26.1Kohm to 34.8Kohm

12/15

ER

Double component

0.11

PG#34

Del Q54 & R1102

12/15

ER

Update PW schematic

0.11

12/16

ER

10

APU_THERMTRIP# of FCH SPEC

0.11

PG#05

R424 & Q79 change to unpop, R427 change to pop

12/17

ER

11

EC release note

0.11

PG#30

Add C125 & R138

12/17

ER

12

Crasis circuit

0.12

PG#14

Add UH6,R512,R513,R514

12/20

ER

13

DDR3 SPD

0.12

PG#08

Reserve R155 R152

12/21

ER

14

Update PW schematic

0.13

12/23

ER

15

Clear CMOS

0.13

R865 change to CLRP1

12/23

ER

16

Procurement recommend

0.13

D4,Q97,Q29 change PN & footprint

12/23

ER

17

WLAN PW spec

0.13

PG#28

Reserve Q31 ,Q32 circuit

12/24

ER

18

EMI request

0.13

PG#26

R1544 change to L121

12/24

ER

19

EMI request

0.13

PG#30

R1631 change to FBMA-10-100505-101T

12/24

ER

20

EMI request

0.13

PG#30

R516 change to 33ohm, C1535 change to 22P

12/24

ER

21

LAN power

0.13

PG#25

Add R553 & J8

12/27

ER

22

EMI request

0.13

PG#25

R549,R552,R1529,R1530 change to 0603

12/27

ER

23

Update PW schematic

0.13

12/27

ER

24

Crystal EA

0.2

PG#18

C35,C36 change to 18P from 20P

12/29

ER

25

Crystal EA

0.2

PG#25

C1634 change to 10P from 27P


C1633 change to 12P from 27P

12/29

ER

26

Crystal EA

0.2

PG#12

C66 change to 8.2P from 22P


C67 change to 10P from 22P

12/29

ER

27

PE_GPIO1 pull down

0.2

PG#12

Add R109 for PE_GPIO1

12/29

ER

PG#12

Compal Secret Data

Security Classification
Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


HW-PIR

Size Document Number


Custom
Date:

Rev
1.0

LA-7322P

Thursday, February 17, 2011

Sheet
1

46

of

47

Version change list (P.I.R. List)


Item

Fixed Issue

Page 2 of 2 for HW
Reason for change

Discharge time fail.

28

Rev.
0.21

PG#

Modify List

Date

Phase

PG#34

Change R1110, R1101 from 470 ohm to 300 ,150 ohm.

01/11

ER

01/11

ER

01/11

ER

01/11

ER

29

For frequency matching.

0.21

PG#12

Change Y4 from 12.5pF to 7 pF


Change C64,C65 from 22p to 10pF.

30

For CRT EA.

0.21

PG#10

Change C1572,C1573,C1574,C1575,C1576,C1577 from


10p to 6.8p.
Change bead value.

31

Change the strap for RAM.

0.21

PG#08
PG#09

Pop R153 and R155, un-pop R961,R150.

32

Correct HDMI audio strap pin.

0.21

PG#18

Un-pop R21,R22 for DIS skew.

01/11

ER

33

Reserve for S3 can't be resume issue of some APU.

0.21

PG#06

Add R1705,R1706.

01/21

PR

34

For PR phase ME assemble.

0.21

PG#33

Del SW3 ,Unpop Sw4.

02/09

PR

35

For PR phase board ID.

0.22

PG#30

Change BID R1603 from 34.8k to 46.4k.

02/14

PR

36

For S3 resume fail issue.

1.0

PG#18

Add R75 1M ohm.

02/15

PR

37

For frequency matching.

1.0

PG#12

Change C66,C67 from 8.2pF 10pF p to 10pF 12pF.

02/16

PR

38

For frequency matching.

1.0

PG#25

C1634 change from 10P


C1633 change from 12P

02/16

PR

39

For EMI test.

1.0

PG#32

Add C1508, C1505 220p.

02/17

PR

40

For EMI test.

1.0

PG#33

Add C1523 220p.

02/17

PR

41

For EMI test.

1.0

PG#26

Add C1506 220p.

02/17

PR

42

For only footprint.

1.0

PG#11

Del L11, L12, L13, L14

02/17

PR

43

For CRT EA.

1.0

PG#10

Change L116,L117,L118

02/17

PR

1.0

PG#10

Change R606 from 2.2k to 150 ohm.

02/17

PR

02/17

PR

02/17

PR

44

to 12P
to 15P

45

For LAN EMI test.

1.0

PG#25

Change TS1 from

XXXXXX

to SP050005L00

46

For EMI request.

1.0

PG#30

Add C126 10 pF,change R516 to 39 ohm, C1535 to 33 pF.

47

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


HW-PIR

Size Document Number


Custom
Date:

Rev
1.0

LA-7322P

Thursday, February 17, 2011

Sheet
1

47

of

47