Mosfet Notes

ECEN 325
Electronics
MOS Field-Effect Transistors
Dr. Aydn Ilker Kar
slayan
Texas A&M University
Department of Electrical and Computer Engineering
NMOS Physical Structure

Source (S)
W
Gate (G)
ta
e
M
Drain (D)
p
n+
1111111111111
0000000000000
Polysilicon
0000000000000
1111111111111
0000000000000
1111111111111
00000000000
11111111111
0000000000000
1111111111111
00000000000
11111111111
0000000000000
1111111111111
00000000000
11111111111
0000000000000
1111111111111
00000000000
000000000000011111111111
1111111111111
00000000000
11111111111
0000000000000
1111111111111
00000000000
11111111111
0000000000000
1111111111111
00000000000
11111111111
0000000000000
1111111111111
00000000000
11111111111
L
al
0000000000000
1111111111111
t
00000000000
e
000000000000011111111111
1111111111111
00000000000
11111111111
M
0000000000000
1111111111111
00000000000
000000000000011111111111
1111111111111
n+
Body (B)
ECEN 325 Electronics - Aydn I. Kar

slayan - MOS Field-Effect Transistors
CMOS Physical Structure
Cross-section
NMOS
S
1111
0000
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
SiO
2
0000
1111
0000
1111
0000
1111
0000
1111
n+
G
11111111
00000000
PMOS
D
n+
D
11111111
00000000
00000000
11111111
00000000
11111111
00000000
11111111
00000000
11111111
00000000
11111111
SiO2
00000000
11111111
00000000
11111111
00000000
11111111
00000000
11111111
p+
G
11111111
00000000
nwell
S
11111
00000
00000
11111
00000
11111
00000
11111
00000
SiO2
p+ 11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111

Physical Operation
NMOS
VGS
S
VGS > Vtn
111111111111
000000000000
n+
n+
VDS = 0
VGS
S
VDS
G
VGS > Vtn
111111111111
000000000000
n+
n+
VDS : very small

Physical Operation
NMOS
VGS
S
VDS
G
VDS < Vov
111111111111
000000000000
n+
n+
Vov = VGS Vtn
VGS
S
VDS
G
n+
VGS > Vtn
VDS > Vov
111111111111
000000000000
VGS > Vtn
n+
Vov = VGS Vtn

ID-VDS Characteristics
NMOS
ID
VDS <Vov VDS >Vov
Triode
Active
VGS4
VGS3
ID
VDS
VGS
VGS2
VGS1
VDS

ID-VSD Characteristics
PMOS
ID
VSD <Vov VSD >Vov
Triode
Active
VSG4
VSG3
VSG
VSD
ID
VSG2
VSG1
VSD

NMOS DC Operation
Cutoff: VGS < Vtn , ID = 0
D
IG =0
Triode (linear) region: VDS < Vov
ID
VGS
S
Vov = VGS Vtn
W
V
ID = k0n
ov VDS
2
VDS
Active (saturation) region: VDS > Vov

k0n W 2
ID =
Vov
2 L

PMOS DC Operation
Cutoff: VSG < |Vtp| , ID = 0
S
VSG
ID
G
IG =0
Triode (linear) region: VSD < Vov
D
Vov = VSG |Vtp|
W
V
ID = k0p
ov VSD
2
VSD
Active (saturation) region: VSD > Vov

k0p W 2
ID =
Vov
2 L

MOSFET DC Biasing
Resistive
VDD
RG1
RG2
V2
VDD
RD
RG1
RS
RG2
VSS
V2 =
V1 =
RG1 + RG2
V2 = VGSn + RSIDn
IDn =
2 L
RD
VSS
RG2(VDD + VSS)
k0n W
RS
V1
RG1(VDD + VSS)
RG1 + RG2
V1 = VSGp + RSIDp
2
(VGSn Vtn)
IDp =
k0p W
2 L
(VSGp Vtp)2

MOSFET DC Biasing
NMOS Current Mirror
Assuming VGS1 > Vtn

VGS1 = VDS1 VDS1 > VGS1 Vtn
M1 is ACTIVE
k0n W
(VGS1 Vtn)2
ID1 =
2 L 1
ID1
M1
ID2
M2
Assuming M2 is ACTIVE
0
k W
ID2 = n (VGS2 Vtn)2
2 L 2
Since VGS1
=
VGS2
ID1
L
= W 1
ID2
L 2

10
NMOS Current Mirror
Example
VDD
R
ID1
ID2
ID3
ID4
ID5
ID6
M1
10/0.5
M2
2/0.5
M3
20/0.5
M4
5/0.5
M5
30/0.5
M6
15/0.5
VSS

11
NMOS Current Mirror
Example
VDD + VSS = R1ID1 + VGS1

ID1 =
k0n 10
2 0.5
(VGS1 Vtn)2
Find ID1
Assuming that all transistors are ACTIVE:

ID2 =
ID1
5
ID5 = 3ID1
ID3 = 2ID1
ID6 =
3
2
ID4 =
ID1
2
ID1

12
MOSFET DC Biasing
PMOS Current Mirror
Assuming VSG1 > |Vtp|

VSG1 = VSD1 VSD1 > VSG1 |Vtp|
M1
ID1
M2
ID2
M1 is ACTIVE
k0p W
(VSG1 |Vtp|)2
ID1 =
2 L 1
Assuming M2 is ACTIVE
0
k W
ID2 = p (VSG2 |Vtp|)2
2 L 2
Since VSG1
=
VSG2
ID1
L
= W 1
ID2
L 2

13
PMOS Current Mirror
Example
VDD
M1
10/1
M2
20/1
ID1
ID2
M3
2/1
ID3
M4
5/1
ID4
M5
40/1
M6
30/1
ID5
ID6
VSS

14
PMOS Current Mirror
Example
VDD + VSS = R1ID1 + VSG1

ID1 =
k0p 10
2
(VSG1 |Vtp|)2
Find ID1
Assuming that all transistors are ACTIVE:

ID1
ID2 = 2ID1
ID3 =
ID5 = 4ID1
ID6 = 3ID1
ID4 =

ID1
2
15
Current Mirror Biasing
Example 1
VDD
M8
10/0.5
R
VI
M1
10/1
M3
15/1
M2
20/1
M5
5/0.5 VB
M4
30/1
M10
5/0.5
M12
20/0.5
M7
5/1
M6
20/0.5
M9
30/2
M11
15/1
VSS

16
Current Mirror Biasing
Example 2
VDD
M2
5/0.5
M6
25/0.5
M10
10/0.5
M4
10/1
VI
M1
40/1
M3
10/0.5
M8
25/1
M5
20/0.5
M7
15/0.5

M9
5/0.5
17
MOSFET Small-Signal Operation
iD =
k0n W
2 L
(VGS + vgs Vt) =
k0n W 2
W
=
Vov + k0n Vov vgs +
2 L
L
k0n W
2 L
(Vov + vgs)2
k0n W 2
vgs
2 L
Assume vgs 2Vov , then
iD
VGS
vgs
iD
VDS
W
0
ID + kn Vov vgs
L
= ID + gmvgs
= ID + id
W
0
gm = kn Vov
L

18
Small-Signal Model
v
u
u
u
u
t
NMOS
W
W
0
0
gm = kn Vov = 2kn ID
L
ro =
VA
ID
nID
is
G
D
vgs
gm vgs
S
model
ro
ro
1
gm
is
S
T model

19
Small-Signal Model
v
u
u
u
u
t
PMOS
W
W
0
0
gm = kp Vov = 2kp ID
L
ro =
|VA|
ID
|p|ID
1
gm
is
ro
G
is
vsg
gm vsg
ro
D
model
D
T model

20
MOS Node Resistances
AC, ro =
RD
Rgate =
Rgate
RS
Rdrain
Rdrain =
RG
RS
RD
RG
Rsource
Rsource =
1
gm

21
Common-Source Amplifier
Discrete
VDD
RG1
Rx
RD
Ro
vo
VG
RL
vi
Ri
RG2
In
RS
VSS
ID = I n ,
VG = VSS +
RG2
RG1 + RG2
(VDD + VSS)

22
Rx
AC equivalent, ro =
vo
vg
RD
vi
Ro
RG
RL
RS
Ri
Ri = RG k Rgate = RG1 k RG2 k Rgate

Ro = RD k Rdrain
vg
vi
Ri
Rx + Ri
RD k RL
=
1
vg
+ RS
gm
vo

23
Common-Drain Amplifier
Discrete
VDD
RG1
Rx
VG
vo
vi
Ri
RG2
In
Ro
RL
VSS
ID = I n ,
VG = VSS +
RG2
RG1 + RG2
(VDD + VSS)

24
Rx
AC equivalent, ro =
vg
vi
Ro
RG
vo
Ri
RL
Ri = RG k Rgate = RG1 k RG2 k Rgate

Ro = Rsource
vg
vi
Ri
Rx + Ri
vo
vg
RL
1
gm
+ RL

25
Common-Gate Amplifier
Discrete
VDD
RG1
RD
Ro
vo
VG
RL
RG2
Rx
In
VSS
ID = I n ,
VG = VSS +
vi
Ri
RG2
RG1 + RG2
(VDD + VSS)

26
AC equivalent, ro =
vo
RG
RD
RL
Ro
vs
vi
Rx
Ri
Ri = Rsource
Ro = RD k Rdrain
vs
vi
Ri
Rx + Ri
vo
vs
RD k RL
Rsource

27
MOSFET Amplifiers - Summary
RD
RD
vo
vo
vi
1
gm
+ RS
RS
RG
RS
RD
vo
vi
vi
vi
vo
AC, ro =
vo
vi
RD
Rsource
vo
vi
RS
1
gm

+ RS
28
MOS Node Resistances
AC, ro finite
RD
Rgate
Rgate =
RS
Rdrain
RG
Rdrain = gmroRS + ro + RS
RS
RD
RG
Rsource
Rsource =
k ro 1 +
gm

RD
ro
29
Integrated
VDD
M3
M2
VD3
R
ID3 =
k0p W
2
L 3
vO
vI
M1
(VDD VD3 |Vtp|) =
VD3
R
ID2
L
= W 2 ,
ID3
L 3
ID1 = ID2

30
ro2
M1
ro1 k ro2
=
1
vi
gm1
vo
vo
vi
AC equivalent
Ri =
Ro
Ro = ro1 k ro2
Ri

31
Integrated
VDD
R
vI
M1
vO
VD3
M3
ID3 =
k0n W
2
L 3
M2
(VD3 Vtn) =
VDD VD3
R
ID2
L
= W 2 ,
ID3
L 3
ID1 = ID2

32
AC Equivalent
vo
vi
M1
Ro
vi
ro1 k ro2
1
gm1
vo
Ri
+ (ro1 k ro2)
Ri =
ro2
Ro =
1
gm1
k ro1 k ro2

33
Two-Port Modeling of Amplifiers
Twoport
Vi
Network
Vo
vi
Ri
vi
Gm vi
vo
vi
Rn
vo
= GmRn

34
vi
Ri
vi
Gm =
Gm vi
isc
Gm & Rn
Rn
vo
isc
vi vo=0
io
Ri
vi
Gm vi
Rn =
vo
Rn
vo
io vi=0

35
#1
v1
#2
v2
v3
#3
Multistage
vN1
vo
#N
vi
Ri
vi
ii
#1
#2
#3
#N
Ro
#1
vo
#2
v1 v 2
vo
=
vi
vi v 1
vN 1
#3
#N
Ri =
vi
ii
Ro =

io
vo
vo
io
36
#1
v1
v2
#2
v3
#3
Multistage
vN1
vo
#N
vi
#1
vi
#2
#3
#N
#2
#3
#N
isc1
#1
Rn1
Gm1 =
isc1
v1
vi
vi
= Gm1Rn1

37
#1
v1
#2
v2
v3
#3
Multistage
vN1
vo
#N
vi
#2
v1
#3
#N
#3
#N
isc2
#2
Rn2
Gm2 =
isc2
v2
v1
v1
= Gm2Rn2

38
#1
v1
v2
#2
v3
#3
Multistage
vN1
vo
#N
vi
#N
vN1
iscN
#N
RnN
GmN =
iscN
vo
vN 1
vN 1
= GmNRnN

39
Integrated
VDD
M3
M2
VD3
R
vO
VB
M1
vI
ID3 =
k0p W
2
L 3
(VDD VD3 |Vtp|) =
VD3
R
ID2
L
= W 2 ,
ID3
L 3
ID1 = ID2

40
AC Equivalent
Ri =
k ro1 1 +
gm1
ro2
ro1
ro2
Gm = gm1 +
vo
M1
vi
1
ro1
Rn = ro1 k ro2
Ri
vo
vi
= GmRn

41
Common-Source Amplifier - SD
Integrated
VDD
M3
M2
vO
VD3
Rx
vI
M1
Rs
ID3 =
k0p W
2
L 3
(VDD VD3 |Vtp|) =
VD3
Rx
ID2
L
= W 2 ,
ID3
L 3
ID1 = ID2

42
Common-Source Amplifier - SD
AC equivalent
Ri =
ro2
vo
vi
Gm =
gm1
1 + gm1Rs + (Rs/ro1)
M1
Rn = ro2 k (Rs + ro1 + gm1Rsro1)
Ri
Rs
vo
vi
= GmRn

43
MOSFET Amplifiers- Summary
AC, ro finite
RD
vo
vo
vi
RS
vi
vo
vi
RD k ro
1
gm
vo
vi
RS k ro
1
gm
+ (RS k ro)

44
MOSFET Amplifiers - Summary
AC, ro finite
RD
RD
vo
vo
vi
vi
RG
RS
gm
Gm =
1 + gmRS +
RS
ro
Rn = RD k (gmroRS + ro + RS )
vo
vi
= GmRn
Gm = gm +
1
ro
Rn = RD k ro
vo
vi
= GmRn

45

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ECEN 325

NMOS Physical Structure

ECEN 325 Electronics - Aydn I. Kar

CMOS Physical Structure

ECEN 325 Electronics - Aydn I. Kar

VGS > Vtn

VGS > Vtn

VDS : very small

ECEN 325 Electronics - Aydn I. Kar

VDS < Vov

Vov = VGS Vtn

VGS > Vtn

VDS > Vov

VGS > Vtn

Vov = VGS Vtn

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

Cutoff: VGS < Vtn , ID = 0

Triode (linear) region: VDS < Vov

Active (saturation) region: VDS > Vov

ECEN 325 Electronics - Aydn I. Kar

Cutoff: VSG < |Vtp| , ID = 0

Triode (linear) region: VSD < Vov

Active (saturation) region: VSD > Vov

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

NMOS Current Mirror

Assuming VGS1 > Vtn

ECEN 325 Electronics - Aydn I. Kar

NMOS Current Mirror

ECEN 325 Electronics - Aydn I. Kar

NMOS Current Mirror

VDD + VSS = R1ID1 + VGS1

Assuming that all transistors are ACTIVE:

ECEN 325 Electronics - Aydn I. Kar

PMOS Current Mirror

Assuming VSG1 > |Vtp|

ECEN 325 Electronics - Aydn I. Kar

PMOS Current Mirror

ECEN 325 Electronics - Aydn I. Kar

PMOS Current Mirror

VDD + VSS = R1ID1 + VSG1

Assuming that all transistors are ACTIVE:

ECEN 325 Electronics - Aydn I. Kar

Current Mirror Biasing

ECEN 325 Electronics - Aydn I. Kar

Current Mirror Biasing

ECEN 325 Electronics - Aydn I. Kar

MOSFET Small-Signal Operation

(VGS + vgs Vt) =

Assume vgs  2Vov , then

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

MOS Node Resistances

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

Ri = RG k Rgate = RG1 k RG2 k Rgate

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

Ri = RG k Rgate = RG1 k RG2 k Rgate

ECEN 325 Electronics - Aydn I. Kar

ECEN 325 Electronics - Aydn I. Kar

Assume vgs 2Vov , then