A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers Amr N. Hafez. and M, I. Elmasry VLSI Research Group University of Waterloo, ON N2L 3G1, Canada, {amrhafer, clmasry}@vlsi.uwaterloo.ca Abstract A sample-and-hold stage placed in the feedback path of a PLL frequency synthesizer reduces the division m= tio, and hence the phase-detector phase-noise, without the need of multiple loops. When used in conjunction with a DDS, this architecture simplifies the DDS design leading to a low-power architecture. Furthermore, this ‘architecture allows for a large loop banduridth thus sup- pressing the VCO phase-noise. The advantages of this architecture are highlighted and system and cincuit- level simulations presented. 1. Introduction ‘The frequency synthesizer is one of the most criti- cal blocks in a wireless transceiver. On one hand its performance directly affects the transceiver's noise fig- ‘ure image rejection and spurious emission, and on the other hand, the VCO is very sensitive to interference, especially in systems that transmit a high power such, as the narrowband-PCS network of Mobitex (2W). In a classical PLL-based frequency synthesizer for ‘a wireless transceiver, the reference frequency to the PLL is equal to the channel spacing. This often leads to-a large division ratio causing the close-in phase-noise to be deminated by the noise from the phase detector. ‘Thus the loop bandwidth must be reduced to attenuate this noise in the range of interest ‘The bandwidth must also be small for adequate spi rious suppression. Whether a classical or afractional-N PLL is ased, a spurious signal appears at a frequency ‘equal to the channel spacing. ‘The bandwidth in both architectures is usually one decade below the channel spacing in order to sufficiently attenuate the spurs. ‘Since the PLL has a small bandwidth, the loop does not attenuate the VCO phase-noise in the range of in- 306 0-7696-0104-499 $10.00 © 1999 IEEE terest. ‘Thus the stringent phase-noise requirements ‘cau be met only by resorting to an off-chip high-Q oscil- lator. This results in higher power consumption, large size and more importantly, greater interference prob- lems. una ‘itt a Dos PD or Le = 1 : 1 st LP Ae Figure 1. Proposed PLL architecture. ‘One technique to solve these problems is to use a digital frequency synthesizer (DDS) to drive a PLL (2). By operating the DDS at a high frequency, the division ratio is reduced and hence the contribution of the PD to the phase-noise, Also, the spurious siguals will be lo- cated at the high frequency of the DDS output, Thus, the bandwidth can be increased in order to inhibit the phase-noise of the VCO, while maintaining good spu- rious rejection. ‘The problem with this architecture is that the high frequency of operation of the DDS results in higher power consumption and greater difficulty in designing the DAC at the DDS output. Another prob- lem with this architecture isthe large resolution needed in the DDS, Regardless of the division ratio sed, the resolution of the DDS will be determined by the ratio fof the output frequency to the channel spacing. For Mobitex, the channel spacing is 12.5kHis and an 18-bit DDS would be necessary. In this paper we propose a novel architecture thatreduces the division ratio while using a low-frequency, low-resolution (and thus low-power) DDS [1]. In ad- dition, the bandwidth of the architecture is relatively large allowing for the integration of the VCO, and nificantly reducing interference problemas 2. PLL architecture ‘The proposed architecture is shown in Fig. 2 ‘The specific frequency bands selected where designed for Mobitex, which has a transmission band of 896- ‘902MEis with a channel spacing of 12.8kHz. The phase- noise requirement is-96dBc/Fls at 10KFIs oft ‘The VCO output is divided down to aa inter ate frequency using a simple, low-power ixed-modulus counter. ‘The output of the divider then samples a fixed-frequeney sinusoidal signal f,, and the beat fre quency is filtered by a low-order LPP. By placing the sampling mixer after the feequeney divider, the refer fence signal needed (f,) is ofa low frequency and thus could be derived from a crystal oxlllator. This allevi- ates the need of an extra PLL/VCO or mixers ike the doubleloop PLL architecture [3 ‘The significant advantage of ths architecture is the reduction of the division ratio while maintaining slow operating frequency for the DDS. The division ratio in Fig. [is only 22 versus 644 if the sampling mixer vwaa not used. ‘This provides more than 20dBe atten- tiation of the phase-noise from the phase-detector and DDS signal. This will also influence the number of bits needed for the DAC of the DDS, since the quantization noise of the DAC translate into phasesnoise [2]. ‘This significantly reduces the DAC power consurption. ‘Another important advantage ofthis architecture is the DDS size and power consumption. The VCO out- put ia converted down tothe 1.4MHe range with a divi- sion ratio of only 22, Thus the DDS will have to provide a resolution of §68.18He with a clock of approximately 3.5MHz, Hence ouly 13 bits of resolution will be suf ficint versus 18 bits if uo mixing was employed. ‘This leads to a significant reduction in the DDS size and power consumption. In addition to reducing the divi- sion ratio, this architecture has a relatively high zefer cence frequency (1-1.4MHt as opposed to 12.5kHs in a classical PLL). This allows for a large bandwidth while ‘maintaining low spurious. A bandwidth of 100kHz will still be one decade less than the spurious frequency while providing nearly 40dBe attenuation of the VCO phase-noise at 10kHE [4], This makes the use of on-chip ‘VOOs, which usually have low quality factors, possible and thus greatly reduces the interference problems as well as avoiding the extra buffers needed to drive ex ternal 50-Ohm terminations. ‘The large bandwidth is 307 ~—") —+ Figure 2. Ring VCO stage. also beneficial in that it provides a fast switching time. 3. Circuit Design ‘The proposed architecture, apart from the DDS, was implemented in 0.35m CMOS technology. ‘The VCO used was a three stage ring oscillator shown in Fig. 2 Both the tail bias current and the load current sources are a function of the control voltage. This yields an amplitude that is fairly constant over fre quency. The center frequency was 1GHz, the gain approximately 80MHe/V and the power consumption 2.8mA. The sampler and filter combination are shown Figure 3. Samplerifilter circuit diagram. in Fig. 3. A passive sampler architecture consisting of capacitors and switches was used. This architecture ‘consumes very little power and is adequate for our ap- plication. Since the sampled signal has a relatively low frequency (less than 100MHz), the capacitor, C, canbbe made large while maintaining an adequate track- ing bandwidth. ‘This results in low clock feedthrough and charge injection. To reduce these effect farther, dummy switches were also added. The filter is realized by simply cascading two opamps. The finite gain-bandwidth product, 1, of each opannp results ina first-order filtering action, with the BWaan determined by the load capacitance. If the sain of the opamp is A, then the filter transfer function 1 1+ 1/A+ 1/A? a Foran opamp with single domintpale 1 4° aioe . Asining Ae >>, \ (3) vy TF afar + (aod Note that due to the fashion the opamps are connected, the Q of the transfer function is equal to 1 as opposed to 1.5 in the case of a cascaded RC sections, Fig. 4 shows the outputs of the sampler and filter for 8 40MHe sinn- soide sarapled at 38MHz. The filter consumes 570A from a 3.3V supply. Sample Filter output 1 Sompler sutput Figure 4. Output of sampler and filter. 4, Simulations ‘The system of Fig. 1 was simulated using Simulink from Matlab. The loop bandwidth was set to 67.5kH2 ‘aud the damping factor 0.707. The transient response of the loop, for a 6MHE frequency step, is shown in Fig. 08 Figure 5. Matlab simulations of the VCO input for a 6MHz frequency step. 5. As shown, the response follows that of a second. order system with the expected natural frequency. ‘The spectrum of the VCO outpnt is shown in Fig. 6. In this case, a simple I-st order LPF was used after the sampling mixer to reject the harmonies. As shown, the spurs are approximately -55dBe down. These spurs could be further reduced by using a higher-order LPF, or by reducing the loop bandwidth. ‘The suppression of the VCO phase noise was also simulated, For a bandwidth of 67.5KHs, it is noces- sary to use an excessively large number of points for FFT in order to get a sufficient resolution, ‘Thus the loop parameters where changed in order to increase the loop bandwidth. ‘The VCO output was 899MHs ‘and sampled at 80MHz. ‘The reference to the phase- detector wat 9.9MHz and the bandwidth was set to ‘2M. Inorder to simulate the VCO phase-noise, three ‘equal tones were injected in the VCO phase at 0.8MELz, 2MHs and 7.83MEHz. Fig. 7 shows the VCO output when configured in the loop. As shown the tone within the loop bandwidth was attenuated by approximately 184B, while the one outside the bandwidth was not attenuated. The tone at 2MHz increased by approxi- mately 34B. This ie attributed to the peaking of the transfer function around the bandwidth, Hspice post-layout simulations were conducted on the complete circuit design. ‘The loop natural fee= quency was sot to 285kHs, and the reference input to the phase detector was at 3MHz. The transient re- sponse of the charge-pump output, for a 32MH fre- ‘quency step, is shown in Fig, 8. The complete circuit consumes 8.6mA from a 3.3V supply,1 a(t Mh le ae ae ae a Figure 6. VCO output spectrum. lag, | ae ae Figure 7. Loop suppression of the VCO noise. Conclusion ‘A novel PLL architecture in which the divided VCO ‘output samples a fixed-frequeney signal was proposed. ‘This architecture greatly reduces the division ratio, tins attenuating the phase-noise due to the phase de- tector and input reference, without the use of extra loop of mixers. Also, if'a DDS is used to provide the reference, it will have a significantly fewer number of bits, In addition, the reference frequency to the PLL is relatively high allowing for a large loop BW and thus ower VCO phase-noise contribution. The architecture ‘was designed in a 0.35m CMOS process and consumes only 8.6mA from a 3.3V supply. Figure 8. Hspice simulation of the VCO con- trol for a 32MHz frequency step. References [A] Patent pending [2) B. Goldberg, Digital Techniques in Frequency Sim- thesis, McGraw Hill, 1996. [3] J. Crawford, "Synthesizer designs minimize phase- noise in cellular systems,” Microwaves and RF, Jan. 93, pp. 69-78. [4] D. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, 1991.