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Design
Dr. S. L. Pinjare
Electrical Design
Physical Design
Fabrication and Testing
Product
30 April 2011
Idea Concept
Define the Design
Redesign
Implementation
Simulation
Physical
Design
Fabrication
Testing and Product
Development
30 April 2011
Idea Concept
Define the Design
Redesign
Implementation
Simulation
Physical
Design
Physical Implementation-Layout
Physical Verification-DRC,ERC,LVS,Antenna
Parasitic Extraction and Back Annotation
Fabrication
Testing and Product
Development
30 April 2011
Idea Concept
Define the Design
Redesign
Implementation
Simulation
Physical
Design
Physical Implementation-Layout
Physical Verification-DRC,ERC,LVS,Antenna
Parasitic Extraction and Back Annotation
Fabrication
Testing and Product
Development
30 April 2011
Fabrication
Idea Concept
Define the Design
Redesign
Implementation
Simulation
Physical
Design
Physical Implementation-Layout
Physical Verification-DRC,ERC,LVS,Antenna
Parasitic Extraction and Back Annotation
Fabrication
Testing and Product
Development
30 April 2011
Fabrication
Testing
Nitte Meenakshi Institute of Technology
PRODUCT
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Matching:
Layout techniques to minimize the errors introduced by
process variations.
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Passives
Resistors
Capacitors
Inductors
Implemented using existing layers and masks
Possibly adding a few extra layers
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Process variability
Parameter variation across the chip
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Design rules
Minimum width
The minimum width of polygon defines the limits of a fabrication process.
A violation of the minimum width rules potentially results in an open
circuit in the offending layer.
An open circuit may be created during fabrication.
A narrow path may be created during fabrication
large currents passing through a narrow path cause the path to act
like a fuse.
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Design rules
Minimum spacing:
To avoid an unwanted short circuit between two polygons
during fabrication,
S1 > Smin, where Smin is set by process.
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Design rules
Minimum enclosure:
Apply to polygons on different layers.
Misalignment between polygons may result in either
unwanted open or short circuit connections.
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Design rules
Minimum extension:
Some geometries must extend beyond the edge of others by a
minimum value.
Eg. Gate poly must have a minimum extension beyond the
active area to ensure proper transistor action at the edge.
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Design Rules
Example of the design rules applying to the POLY layer
C3.4 POLY:
Gate Structures and resistors are defined by the poly layer. Minimum design rules
are used for the polylayer. i.e. this is the minimum feature size for this process.
A 1.5 m,(minimum polywidth /Length).
B 1.5 m,(minimum poly to poly distance).
C 1.5 m,(minimum poly-over-oxide overlap).
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Unit Matching
Two electrically equivalent components.
Draw them identically
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Unit Matching
Two electrically equivalent components.
Draw them identically
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Common-centroid layout
Process variations can locally be approximated with a
linear gradient.
(a): A1 + A2 < B1 + B2
(b): A1 + A2 = B1 + B2 (common-centroid)
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Resistors
All materials have a resistivity
Typical resistivities
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Poly-Resistors
Poly Resistors
Silicidated poly resistors: 1 10 Ohm/sq.
30%
Non-silicidated poly resistors: 50-1000 Ohms per unit area .
Small parasitic capacitances to substrate.
Superior linearity.
High cost due to the extra mask needed to block silicide
layer.
20%
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Diffusion Resistors
1k Ohm/sq
N-well
Large parasitic capacitance between n-well and substrate.
Resistance is strongly terminal voltage-dependent and
highly nonlinear.
Depletion width varies with terminal voltages.The
cross-section area varies with terminal voltages
Large error : 40%
noisy as all disturbances/noise from substrate can be
coupled directly onto the resistors
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Resistor Layout
Standard Resistors: Avoid 90 degree angle. 45 degree is
recommended
Recommended resistor
layout
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Resistor Layout
Dummy resistors are added to
minimizes the effect of
process variation
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Shielded Resistors
Shielding resistors
Connected to a constant voltage
source
Prevent self-coupling of the
resistor R/inter-coupling
with others.
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Capacitors
There are naturally capacitors between each layer of
metal, poly silicon or silicon
Dielectrics between different metal layers have a
thickness of 0.5-1 micron, which gives a rather large
area for a given capacitance.
Key Parameters
Linearity
Parasitic capacitance to substrate
Series resistance - resistance of capacitor plates
Capacitance per unit area
Larger specific capacitance (capacitance per unit area)
gives smaller area
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Types of IC Capacitors
Poly-diffusion capacitors
Nonlinear bottom-plate parasitic
capacitance.20% of inter-plate
capacitance.
.6-.8 fF/m2(5%). Matching
0.2%
MOS capacitors
Stable capacitance in strong
inversion
Non-negligible channel
resistance lowers the quality
factor (Q) of the capacitor
0.6 - 0.8 fF/m2; (5%).
Matching 0.5%
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Poly-poly capacitors
Not available in standard
CMOS processes
0.3 - 0.5 fF/m2; (10%).
Matching 0.5%
Metal-poly capacitors
Capacitance is small, area
consuming.
0.03-0.05 fF/m2. (25%).
Matching 0.5%
Metal-metal capacitors
Capacitance is small, area
consuming
0.02-0.04 fF/m2; (25%).
Matching 0.1%
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Case 1
1:4
1:4
Perimeter
1:2
1:4
1:4.46
1:4
P erimeter
1:2.1
1:4
Case 2
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Current is spread
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No of fingers:
Gate resistance < 0.1 to .5(1/gm)
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Another layout
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Antenna Effect
There will be charge accumulation on Metal1 during plasma
etching (of metal1) causing damage to thin gate oxide (Large
metal area)
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a.
b.
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Matching - Summary
To achieve both common-centroid and PLI matched
transistors has to be split into 4 fingers.
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Matched Transistors
Matched transistors require elaborated layout techniques
Use inter-digitized layout style
Averages the process variations among transistors
Common terminal is like a serpentine
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Differential Amplifier
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Summary
Use large area to reduce random error
Common Centroid layout to reduce linear gradient
errors
Use unit element arrays
Interdigitize for matching
Use of symmetry (photolithographic invariance)
Dummy device for similar vicinity
Guard rings for isolation
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References
A. Hastings, The Art of Analog Layout, PrenticeHall,2002.
B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw-Hill, 2001.
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Thank You
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Simulation
To fully describe the function of a MOS transistor the
fundamental electro-magnetic equations are set up in 2D/3D.
Coupled non-linear partial deferential equations take long time to
solve.
Compact models are desired.
Simple mathematical relations that describes the relation between currents
and voltages.
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Simulation
Devices are characterized for a parameter window
where the model becomes valid.
Validity outside defined parameter window:
Physical: Good validity.
Empirical: Have difficulties outside the window and can in
some cases give preposterous results.
Table based Same or worse than empirical models.
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SPICE
Simulation Program with Integrated Circuit Emphasis
There are two sides of SPICE:
The simulator
The models
The simulator
A circuit is described with nodes and elements between nodes.
For linear circuits the matrix is solved using nodal admittance
analysis.
Non-linear circuits are solved using iterative methods.
The basic simulation types are OP, DC, AC and transient
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SPICE simulations
OP Operating Point analysis.
Solves the currents and voltages in a circuit at one bias condition.
DC
Same as OP but does it for one or more swept parameters, e.g. IDS vs.
VDS
AC
Linearizes all elements at the bias point. Then a sinusodial signal is
applied on one or more inputs and the frequency is swept.
Note: since the circuit is linearized no saturation effects will occur
using AC.
Transient
One or more time varying signals (e.g. sinusodial, pulses, square waves)
are applied and the time is swept. This simulation does not linearize the
circuit so here saturation effects are present.
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Latchup
Latchup may begin when Vout drops below GND due to a noise spike or an
improper circuit hookup (Vout is the base of the lateral NPN Q2). If sufficient
current flows through Rsub to turn on Q2 (I Rsub > 0.7 V ), this will draw
current through Rwell. If the voltage drop across Rwell is high enough, Q1
will also turn on, and a self-sustaining low resistance path between the power
rails is formed. If the gains are such that b1 x b2 > 1, latchup may occur. Once
latchup has begun, the only way to stop it is to reduce the current below a
critical level, usually by removing power from the circuit.
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SPICE netlist
*** Top Level Netlist ***
M1 5 5 2 2 CMOSNB L=5u W=15u
M2 6 5 2 2 CMOSNB L=5u W=15u
R1 4 5 380k
VDD 3 0 DC 2.5v AC 0 0
Vout 1 0 DC 0
VSS 2 0 DC -2.5v AC 0 0
*** Control Statements ***
.DC VOUT -2.4 2.5 .1
.PRINT DC ALL
**** Spice models and macro models ****
.MODEL CMOSNB NMOS LEVEL=4 VFB=-9.73E-01
+LVFB=3.67E-01, WVFB=-4.72E-02, PHI=7.46E-01
+LPHI=-1.92E-24, WPHI=8.064E-24
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SPICE models
The first MOS-models came in the begining of the 70's.
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