LOOK UP TABLE BASED POWER AWARE ANALOG

AND MIXED SIGNAL CIRCUIT TESTING

Dissertation submitted to
National Institute of Technology, Agartala
for the award of the degree
of

Master of Technology
by

Laxmana Maharana (Enrolment No: 14PEC030)

Supervisor

Dr.Sambhu Nath Pradhan

ELECTRONICS & COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY, AGARTALA
MAY- 2016
2016 Laxmana Maharana. All rights reserved
i

ii

Dedicated
To
My Guide & My Family

iii

iv

National Institute of Technology, Agartala

Barjala, Jirania, Agartala, Tripura (West), 799055
Department of Electronics & Communication Engineering

CERTIFICATE OF APPROVAL

This dissertation entitled Look up Table Based Power Aware Analog and Mixed Signal
Circuit Testing by Mr. Laxmana Maharana is approved for the degree of M.Tech in
VLSI & NANOTECHNOLOGY specialization.
Examiners
________________________
________________________
________________________
Supervisor
________________________
________________________
________________________
Chairman
________________________
Date :____________
Place :____________

vi

DECLARATION

I, declare that this written submission represents my ideas in my own words and where
others' ideas or words have been included, I have adequately cited and referenced the
original sources. I also declare that I have adhered to all principles of academic honesty
and

integrity and

have

not

misrepresented

or

fabricated

or

falsified

any

idea/data/fact/source in my submission. I understand that any violation of the above will

be cause for disciplinary action by the Institute and can also evoke penal action from the
sources which have thus not been properly cited or from whom proper permission has not
been taken when needed.
_________________________________
(Signature)
________________________________
(Laxmana Maharana)
_________________________________
(14PEC030)
Date: __________

vii

viii

National Institute of Technology, Agartala

Barjala, Jirania, Agartala, Tripura (West), 799055
Department of Electronics & Communication Engineering

CERTIFICATE

It is certified that the work contained in the dissertation titled Look up Table Based
Power Aware Analog and Mixed Signal Circuit Testing by Mr.Laxmana Maharana,
has been carried out under my supervision and that this work has not been submitted
elsewhere for a degree.

Signature of Supervisor
Dr. Sambhu Nath Pradhan
Electronics & Communication Engineering
N.I.T. Agartala
May, 2016

ix

PREFACE

The trend of scaling down the ICs is become an inherent design step in the arena of low
power VLSI circuit design.IC fabrication in a Nano space wafer expects a high failure
rate due to redundant device addition, device missing and short and opening of
conduction paths. Therefore circuit testing and diagnosis is a vital step in the field of
VLSI design and fabrication. The testing procedure also alters according to the variant
design technology and design architecture which attracts and motivates the researcher
towards it. In this dissertation new method of testing for analog and mixed circuits has
been adopted to enhance the quality of testing. Since the Operational amplifier is the
basic building block of many analog circuits, it is taken as the circuit under test or this
project. As we know the power optimization is a major concern for the low power VLSI
circuit, therefore here power aware testing technique is centralized. Method like sleepy
stack along with a current correlator has been applied to the testing circuit to minimize
the test power during testing. This power aware testing is implemented for operational
amplifier and the necessary simulation is carried out in the virtuoso environment of
Cadence tool using 45nm technology.
Chapter 1 Describe the testing, its need and different methods of testing
Chapter 2 describes all referred techniques as Literature Review
Chapter 3 Explains steps for analog and mixed circuits
Chapter 4 Power reduction techniques during testing
Chapter 5 Proposed methods for analog circuit testing has been discussed.
Chapter 6 Proposed methods for Mixed circuit testing has been included.
Chapter 7 Result and discussion for analog circuit testing
Chapter 8 Conclusion and future scope has been detected.
xi

xii

ACKNOWLEDGEMENT

I would like to express my gratitude to Dr.Sambhu Nath Pradhan, the Head of

Department, and NIT Agartala, department of Electronics & Communication Engineering
who has always been a constant motivation, continuous guiding factor and support
throughout this project work. I am extremely grateful to have the opportunity to work
with him.
Next, I wish to express my gratitude to Mrs.Trupa Sarkar, PHD scholar, Electronics
and Communication Engineering, Mr. Manik Bhowmik, Assistant professor, PG
coordinator, Department of Electronics and Communication Engineering and the entire
faculty as well as staff of the Department who devoted their valuable time and helped me
in all possible ways towards successful completion of this work.
I would also like to thank Ms. Debanjali Nath, Mr. Suman Bhowmik,Abhishek
Nag,Apangshu .. Ph.D. Scholar, my friend Mr. Krishna Rudrapal, Mr. Manish
Singh M.Tech Student and my all other friends who have patiently extended all sorts of
help for accomplishing this undertaking.
Lastly, I would like to thank my parents, my family for their years of unyielding love and
encourage. They have always wanted the best for me and I admire their determination and
sacrifice.

LAXMANA MAHARANA
(ROLL NO-14PEC030)
xiii

xiv

LIST OF FIGURES

Fig. 1.1

Basic Testing Approach

Fig.1. 2

BIST Testing Approach

Fig. 1.3

Mixed Circuits (Analog-Digital)

Fig.1. 5

Cause of Faults

Fig.2. 1

OBIST Technique

13

Fig. 3.1

Flowchart of analog testing

18

Fig. 3.2

Fault Modeling

19

Fig.3.3

Mixed signal testing circuit

22

Fig. 4.1

Gate without stacked NMOS

28

Fig. 4.2

Gate with stacked NMOS

28

Fig. 4.3

Gate without stacked

28

Fig. 4.4

Gate with stacked

28

Fig. 4.5

Current correlator

30

Fig. 5.1

Flowchart of proposed testing hierarchy

35

Fig. 5.2

Stuck at short model of an Op-Amp

38

xv

Fig.5.3

Stuck at open model of an Op-Amp

38

Fig.5.4

Circuit diagram of single fault injection for an Op-Amp

41

Fig.5.5

Block diagram of testing circuit for all injected faults

42

Fig.5.3

Current correlator circuit

45

Fig.5.4

Testing Op-Amp circuit with current correlator

45

Fig. 6.1

Mixed circuit for testing

50

Fig 7.1

Fault coverage for different parameters

57

Fig 7.2.

% power saving

58

LIST OF TABLES

Table 5.1

Fault Models due to different faulty nodes

40

Table 7.1

Look up Table of fault simulation(no power Min.)

55

Table 7.2

Look up Table of fault simulation with power Min.

56

Table 7.3

Fault Coverage

57

xvi

LIST OF ABBREVIATIONS
VLSI

Very Large Scale Integration

SoCs

System-on-Chips

ICs

Integrated Circuits

NMOS

N type Metal Oxide Semiconductor

NMOS

P type Metal Oxide Semiconductor

CUT

Circuit under Test

BIST

Built in Self Test

ADC

Analog to Digital Converter

DAC

Digital to Analog Converter

OBIST

Oscillation-based Built-in Self-Test

TDM

time-division multiplexing

LUT

Look up Table

DUC

Device Under Test

xvii

LIST OF NOTATIONS
power supply current
dv

Change in voltage
Change in power supply current
Deviation in Parameter
Drain to source current
Transistor gate voltage
Source voltage
Drain Voltage

If4

Forward component of current

Ir4

Reverse component of current

Output Current
Output voltage after cross correlation
Thermal Voltage

Trans conductance

Current gain
Correlators output Trans resistance

xviii

ABSTRACT

In a Nano space wafer, it is a hard task to integrate a circuit having millions of transistors
with perfection. High frequency of device scaling increases the density of components in
an IC .This Miniaturization of the circuits increases the complexity and probability of
faults. Therefore testing is a vital step in VLSI circuit fabrication. The testing is the
technique to sort out the faults in an IC and diagnosis the fault to find out the fault
location. The objective is to realize through detailed testing, that the manufactured
products are free from defects. It may ultimately help in increasing the product yield and
reducing the product cost. The broad specifications of analog circuits require detailed and
long performance tests. This results in lengthy time consuming and very expensive test
procedures. These factors have resulted in ample research being channeled in the
direction of mixed signal testing. The applications of analog and mixed-signal,
embedded-core-based, system-on-chip in recent years have motivated system designers
and test engineers to direct their research to develop methodologies in effective very
large-scale integrated circuits and systems testing. Mixed signal hardware systems have
digital cores, very often interconnected with analog filters, analog and digital converters
for digital processing. Due to the continuous dimensional modulation, the circuit
geometry shrinks which increases the sensitivity of circuit performance. Therefore, a
prototypic testing for Analog and Mixed Signal (AMS) circuits is essential before going
to the production cycle.
The increasing transistor count with in a constant wafer space increases the power density
and temperature. During testing the testing circuit consumes nearly double power as
compared to that of a normal circuit. Therefore power acts as an important constraint
during testing. Power should be reduced to its optimal value to catalyze the success rate
of testing.
xix

In this project, An Operational Amplifier, which is the building block for the analog
circuit, has been designed in CADENCE tool using 45nm technology. Fault coverage of
testing is achieved to nearly 93% even also to 100% for some parameter testing. Since
analog testing prefaces the challenge of power dissipation during testing, some power
minimization techniques like sleepy stack method, current correlation method have
adhered during the testing process .A mixed signal testing is also carried out for a circuit
containing a second order filter followed by a C-17 test bench circuit with an ADC
interface.

Keywords: Oscillation-Based Built-In Self Test (OBIST), Analog and Mixed Signal
(AMS), System-on-Chips (SoCs), Operational Amplifier (Op-Amp), Circuit under Test
(CUT)

xx

CONTENTS
Title Page

Dedication

iii

Certificate of Approval

Declaration

vii

Certificate

ix

Preface

xii

Acknowledgements

xiii

List of Figures

xv

List of Tables

xvi

List of Abbreviations

xvii

List of Notations

xxiii

Abstract

xix

Contents

xxi

Chapter 1

INTRODUCTION

1.1 Need of Testing

1.2 Testing

1.3 Testing Approach

1.4 Types of Testing

1.5 Faults and Types of Faults

xxi

1.5.1 Hard Fault

1.5.2 Soft Fault

References
Chapter 2

LITERATURE REVIEW

11

2.1 Fault and its cause

12

2.2 Testing Techniques for Fault Detection

12

References

Chapter 3

16

ANALOG AND MIXED SIGNAL TESTING

3.1 Analog circuit Testing procedure
3.1.1 Fault list and Fault Model

18
19

3.1.1.1 Stuck at open fault Model

19

3.1.1.2 Stuck at short fault Model

20

3.1.2 Fault Injection

20

3.1.3 Fault Simulation and comparison

21

3.1.4 Fault Coverage calculation

21

3.2 Mixed Signal Testing Procedure

21

References

Chapter 4

17

23

POWER MINIMIZATION OF LOW POWER CIRCUITS

DURING TESTING

25
xxii

4.1 Sources of Power Dissipation

4.1.1 Dynamic Power Consumption

26
26

4.1.2 Short Circuit Current

27

4.1.3 Leakage Current

27

4.2 Leakage Reduction Methods

27

4.2.1 Stack Effect Based Technique

4.2.2 Current Correlator Circuits

28
29

References

Chapter 5

23

PROPOSED METHOD FOR ANALOG CIRCUIT TESTING BASED ON

LOOK UP TABLE

33

5.1 Operational Amplifier as the Circuit under Test

5.2 Fault list and fault Model

37

5.3 Fault injection and comparison

Chapter 6

36

41

5.4 Fault coverage

42

References

47

PROPOSED METHOD FOR MIXED SIGNAL TESTING BASED ON

LOOK UP TABLE

49

6.1 Fault Activation (step 1)

51

References

51
xxiii

Chapter 7

RESULTS AND DISCUSSIONS

53

Chapter 8

CONCLUSION AND FUTURE SCOPE OF STUDY

61

8.1 Conclusion

61

8.2 Future Scope

61

xxiv

CHAPTER 1

INTRODUCTION

Testing is a critical step in the semiconductor production process. IC testing is used

for debugging, diagnosing and repairing in their new environment. The test should be carried
out to indicate the desired perfection. The objective is to realize that the manufactured
products are free from defects. It may ultimately help in increasing the product yield and
reducing the product cost. The broad specifications of analog circuits require detailed and
long performance tests. This results in lengthy time consuming and very expensive test
procedures. These factors have resulted in streamline the research in the direction of mixed
signal testing. The applications of analog and mixed-signal in system-on-chip in recent years
have motivated system designers and test engineers to work out their research to develop
methodologies in effective VLSI circuits and systems testing.

The revolution and evolution in System-on-Chips (SoCs) design increases the complexity of
circuit due to increase in transistor count according to the Moores law. In a Nano space
wafer, it is harder to integrate a circuit having millions of transistors with precision and

Chapter 1
perfection. Transistors are being fabricated in SOCs as per the prototypic model which is
prepared by an industry for a particular technology after going through a process of VLSI
Design flow consisting of logical and physical testing using designing and testing tools like
XILINX and Cadence respectively. Even after a proper modular design of the VLSI circuits,
the probability of circuit failure is still there due to continuous modulation of the circuit
parameters as a consequence of geometrical scaling. Therefore, prototypic testing for circuits
is essential before going to the production cycle.

1.1 Need of Testing

Especially for advanced semiconductor technologies, it is expected some of the chips

on each manufactured wafer contain defects that render them non-functional. The primary
objective of testing is to find and separate those non-functional chips from the fully
functional ones, meaning that one or more responses captured by the tester from a nonfunctional chip under test differ from the expected response. The percentage of chips that fail
test, hence, should be closely related to the expected functional yield for that chip type. In
reality, however, it is not uncommon that all chips of a new chip type arriving at the test floor
for the first time fail (so called zero-yield situation). In that case, the chips have to go through
a debug process that tries to identify the reason for the zero-yield situation. In other cases, the
test fall-out (percentage of test fails) may be higher than expected/acceptable or fluctuate
suddenly. Again, the chips have to be subjected to an analysis process to identify the reason
for the excessive test fall-out.

The exponential growth of transistor count for an IC in conjunction with the variations in the
design technology, the flawlessness of the design is affected due to incremental component
density. The mixed SOCs contains both analog and digital blocks which takes inputs as
analog signals and digital signals respectively along with a converter in between them as
shown in Fig. 1. But these blocks and converters are made up of same type of NMOS or
PMOS which shows different behaviors for the different inputs. Hence the circuit needs an
error free verification at structural level as well as behavioral level. Besides this a quantified
yield depends on the customer satisfaction which is only possible by a successful testing
technique either at the manufacturer ends with in an optimum cost. Testing is required to sort

Introduction
out a fault-free circuit after the batch process of IC design and before packaging. There may
be a chance of transistor missing or redundant device addition at the time of circuit
fabrication. Since ICs are manufactured in a batch process, the same type of error can be
detected and rectified at the structural level. Base level testing would save time, improve
quantification of cost and yield along with customer satisfaction.

1.2 Testing

Testing is the process in which behavior and response of the testing circuit is checked
according to the given input. It is the process of realization to ensure whether the circuit is
free from defects or not. Different circuit imperfections may lead to Failure of individual
IC(integrated

circuits).The

main

objective

of

testing

is

to

guarantee

whether a circuit meets all the required specifications or not. If the circuits response is
according to its specification then it is said to be fault free else it is faulty. Consider the case
of an Op-Amp, if it is in sync with the device specifications like Gain, Bandwidth, Slew Rate,
CMMR etc then we can say the particular device is fault free with respect to that particular
parameter.

1.3 Testing Approach

Vital information about the nature of the underlying problem may be hidden in the
way the chips fall during test. To facilitate better analysis, additional fail information beyond
a simple pass/fail is collected into a fail log. The fail log typically contains information about
when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., logic value) the
test failed. Diagnostics attempt to derive from the fail log at which logical/physical location
inside the chip the problem most likely started. By running a large number of failures through
the diagnostics process, called volume diagnostics, systematic failures can be identified.

Testing typically processes a set of test stimuli to the inputs of the CUT (Circuit under Test)
during analysis of the output responses by an output response analyzer (ORA) as shown in
Fig. 1.The CUT that shows the correct output responses with respect to the input stimuli is

Chapter 1
said to be pass the test and considered as fault free. Otherwise if the circuit fails to produce
correct response at any point of testing then it is said to be faulty. Testing is carried out at
different stages of the life cycle of the VLSI device. In this section the testing is performed at
the developmental stage of the VLSI device.

Fig. 1.1 Basic Testing Approach

In BIST (Built in Self Test) design process provides the capability of solving many of the
problems encountered in testing analog, mixed-signal or digital systems. Test generation, test
application and response verification is through Built-in hardware. It allows different parts of
the chip tested in parallel thereby reducing the required testing time [2]. It eliminates the
necessity for external test equipment. BIST circuitry is located in the digital portion of the
mixed-signal circuitry to minimize area overhead. The basic principle of BIST is explained in
the Fig.1.2.

STIMULUS

CUT

TEST RESPONSE

BIST METHOD
TEST CONTROLLER

Fig.1. 2 BIST Testing Approach

1.4 Types of Testing

ICs consist of both analog and digital blocks interfaced by an intrinsic mixed signal circuit
like ADC or DAC on a single semiconductor die as shown in Fig. 1.3 [8]. Since the required
supply voltage and the output voltage of analog and digital blocks are different, testing

Introduction
should be held separately for the individual blocks as the signal processing is not same for
both the blocks. Therefore testing is classified as:-Digital signal Testing, Analog Signal
Testing and Mixed Signal Testing. In this Project work analog testing and mixed signal

Primary Outputs

Digital Block

ADC

Analog Block

Primary inputs

testing has been focused.

Fig. 1.3 Mixed Circuits (Analog-Digital)

In the case of digital testing the output has two probable values like VDD (logic 1) or GND
(logic 0') irrespective of the type of faults or inputs. Therefore, test pattern generation is
quite simple. Digital circuit testing, very crudely, consists in checking that the pattern of 1s
and 0s at the outputs corresponds to the pattern expected. The input output test pattern is
generated by different pattern generator tools like ATALANTA, FSIM for benchmark
circuits. But for the analog module, a range of output can be possible due to high sensitivity
and varying tolerance of analog parameters. So test pattern generation is difficult for analog
testing. In some testing approach like Oscillation-based Built-in Self-Test (OBIST) [1] there
is no such pattern generator or pattern analyzer which is present in digital testing.

In case of Mixed circuit testing, both the analog and digital testing are combined together by
either applying digital signals, such as serial bit streams to drive analog circuits, or by using
analog signals to drive digital circuits as discussed in [9]. Mixed circuit testing is known to be
a very difficult task. This is due to the difficulty in testing the analog part of the circuit.
Testing is done by controlling the digital signal from the analog outputs, observing the analog
outputs in the digital circuit or controlling the analog circuit from the digital outputs and
observing the digital signals in the analog circuit.

Chapter 1

1.5 Faults and Types of Faults

If the Circuit under Test is not performing its normal operation then we can say that
the malfunctioning of the circuit is due to presence of fault or faults in the circuit during
fabrication. The faults are classified as-Hard fault or Soft fault.

1.5.1 Hard Fault

Defects can occur during the manufacturing process. If defects alter the circuit
schematics then they are categories as hard faults. Dust particles during the metallization
process can cause an opening or a short of metal wires. Fig.1.5 shows the hard faults like
open, short, extra device, and missing device.

Fig.1. 5 Cause of Faults

1.5.2 Soft Fault

Soft faults are those faults in which defect are too minor to cause hard faults. Device
parameters may get change in soft faults. For example dust can block the poly silicon gate

Introduction
hence shorts the channel length of transistor. Soft faults are also classified into parametric
faults and deviation faults. Parametric faults are used to model the variation in the parameter
and Deviation faults refer to changes in the overall performance of the entire circuit.

Chapter 1

References
[1]

K. Arabi, B. Kaminska,Oscillation built-in self-test (OBIST) scheme for functional

and structural testing of analog and mixed-signal integrated circuits.Proc.IEEE ITC,
1997, 786 795.

[2]

Vaishali Dhare and Usha Mehta, SAF analyses of analog and mixed signal VLSI
Circuit: digital to analog Converter, International Journal of VLSI design
&Communication Systems (VLSICS) Vol.6, No.3, June 2015.

[3]

Ms. Harshal Meharkure, Mr.Swapnil Gourkar,Fault Testing of Analog Circuits

Using Combination of Oscillation Based Built-In Self-Test and Quiescent Power
Supply Current Testing Method, IJAIEM,Volume 2, Issue 12, December 2013.

[4]

Amrita Oza, PoonamKadam, Techniques for Sub-Threshold Leakage Reduction in

Low Power CMOS Circuit designs, Volume 97 No.15, July 2014.

[5]

Chris Winstead, Nhan Nguyen, Vincent C. Gaudet and Christian Schlege, LowVoltage CMOS circuits for Analog decoders .

[6]

Jacob A. Abraham and Jeongjin Roh,A Comprehensive Signature Analysis Scheme

for Oscillation Test, IEEE Transactions on Computer Aided Design, vol. 22, no.10,
pp. 1409-1423, Oct. 2003.

[7]

Daniel Arbet and Viera Stopjakova, Libor Majer and Gabriel Nagi, New OBIST
using On-chip Compensation of process variations toward increasing Fault
Delectability in Analog ICs, IEEE Transactions On Nanotechnology, vol.12, no. 4,
pp. 486-497, July 2013.

[8]

Bechir Ayari, Naim Ben Hamida and Bozena Kaminska, Automatic Test Vector
Generation for Mixed-Signal Circuits Ecole Polytechnique of the University of
Montreal P.O. Box 6079, Station Centre-ville, Montreal, PQ, Canada, H3C 3A7.

Introduction

[9]

J. Roh and J. A. Abraham, A comprehensive signature analysis scheme for

oscillation-test, IEEE Trans. Comput.-Aided Design, vol. 22, no. 10, pp. 14091423,
Oct. 2003.

[10]

Sunil R. Das, Jila Zakizadeh, Satyendra Biswas , Testing Analog and Mixed-Signal
Circuits With Built-In HardwareA New Approach , IEEE transactions on
Instrumentation and measurement, vol. 56, no. 3, June 2007.

Chapter 1

10

CHAPTER 2

LITERATURE REVIEW

Since so many research works have been done for analog and mixed signal
circuit, the testing is still in premature stage. Day to day new techniques is being
implemented to improve the quality of testing. Better testing emphasizes on the proper
technical verification at a lower cost in the least time durability. Here, in this project
we are going to develop one advanced technique to improve the quality of testing by
referring some IEEE papers and journals to get the traditional steps of testing. We
have followed some previous working methods related to analog and mixed signal
testing and then made some required modifications which may either fulfill the
lacunas of the current testing methods or catalyze the creativity of the researchers
further.

11

Chapter 2

2.1 Fault and its cause

Miniaturization of the VLSI circuits with the variant design technology

expects an excellent and 100% error free fabrication process. But in the practical
world, it is not always feasible. There is always a probability of finding a circuit faulty
due to human, instrumental or environmental errors during manufacture. The reasons
for the creation of the fault are detailed in[2].In this paper the author has stated the
common and frequently observed causes of the fault as shown in fig. 5.During batch
processing of ICs on a silicon wafer the following causes create the circuit to be a
failure one.

Missing of any device/devices at the time of fabrication.

Addition of redundant components during manufacturing.
Short or open of any electrical node/nodes which results in violation of the
electrical properties and makes the circuit fatal.

2.2 Testing Techniques for Fault Detection

The affluent occurrence of circuit failure has been paved the way for testing.
Therefore many testing techniques have been adopted for digital, analog and mixed
environment. Digital testing is considered as an easier and successful testing while
analog and mixed signal testing is a challenging job. For this project which includes
analog and mixed signal testing, the papers [1-4] and [7-10] are referred to develop a
suitable testing technique. The papers are dealt with different of same procedural
techniques but with different testing circuits and different testing parameters. Here in
this section the testing steps are retrieved from all above stated papers which are being
explained briefly one by one.

In [3] an Oscillation based Built in Self Test (OBIST) method has

been implemented for testing the analog circuit. In this testing
approach, each building block (CUT) is converted into an oscillator

12

Literature Review
by adding the proper feedback circuitry in order to achieve sustained
oscillation. The oscillation parameters are then evaluated. A faulty
circuit is detected from a deviation of its oscillation parameters under
fault free conditions. The oscillation parameters are independent of
the CUT type and analog testing. The block diagram of OBIST
strategy is explained in Fig

Several fault-based test strategies have been proposed in the literature for
testing analog and mixed-signal circuits. The OBIST deserves special
mention because it is conceptually simple and does not require extensive
modifications of the CUT for testing [2]. The oscillation-based-test
(OBIST) strategy is a defect-oriented technique and can be applied either
for online or for offline testing. In this test method, there is no need for
either test generators or test specifications, which are very costly.

Fig.2.1 OBIST Technique

13

Chapter 2
An overview of the different steps of the procedure is given as follows:-

A complex analog circuit is partitioned into smaller blocks

like Op- Amps, Comparators, Filters, PLLs etc or any
combinations. In [3] Op-Amp is taken as the Device under
Test (DUT).

Each building block (Op-Amp in [3]) is converted into an

oscillator by adding the proper circuitry in order to get
sustained oscillation by adding a feedback circuit.

The oscillation parameters are then evaluated after

simulation. For Op-Amp the testing parameters can be Gain,
Output Voltage, Bandwidth, Slew Rate etc, .Output Voltage
is taken as testing parameter for Op-Amp.

Similarly the fault free block is simulated by converting it

into an oscillator circuit.

Both the testing parameters are compared on a display. if

the output wave form of fault free block matches with the
faulty block then DUT is said to be fault free else faulty.

Fault Coverage is calculated for each test parameters.

In [2], a Digital to Analog Converter has been taken for testing of mixed
signal testing. Stuck open and stuck short faults are illustrated. The same
procedures are being followed similar to [3].Digital inputs are given to the
DAC and then the output response is calculated. Here the Differential Non
Linearity (DNL) and Integral Non Linearity are introduced to find out the
percentage of error to sort out the circuit is fault or fault free.
In [6], Built in Self Test method is adopted to check the functionality of analog
and mixed signal circuit. Unlike the OBIST method here a time-division
multiplexing (TDM) comparator to analyze the response of a circuit under test
with minimum hardware overhead. TDM comparator can be used to measure
the frequency and amplitude. In this technique also the CUT is converted into
an oscillator.
In [7], an extra Schmitt trigger is used as the on chip frequency reference to
compensate the influence of process parameter variations. However this

14

Literature Review
solution can be also implanted in OBIST method for analog and mixed signal
integrated circuits. The proposed OBIST strategy has been experimentally
applied to verify various circuits like filters. It is applicable to determine
catastrophic faults of the mixed circuit.
Reference [10] is just similar to that of [3].Here many analog circuits like
Inverter, Op-Amp and phase shift oscillator are taken for testing. In this
method the CUT is converted into an oscillator by adding extra
circuit

as

feedback.

If

the

circuit

is

faulty,

the

converted

circuit either will not oscillate or the oscillation frequency and

voltage will differ from those of the fault-free conditions.

As we know that the testing circuit consumes more power as compared

to a normal circuit and in low power VLSI design power dissipation plays a
major controller for a better and relevant design. Therefore power reduction
during testing is a necessary step for a successful testing. In [6] many leakage
reduction techniques are discussed like- Stack Effect Based Technique, Power
Gating, Body Biasing Technique.

Leakage reduction in [6] includes adding a sleep transistor between actual ground
terminal and circuit ground (termed as the virtual ground). In sleep mode to cut-off,
the leakage path the sleepy transistor is turned off. High threshold sleep transistor is
used that cuts-off Vdd from the circuit when no switching activity is going on. Here a
NMOS is connected between virtual GND and actual GND.

a current correlator as discussed in [5] can also be used to minimize the power
dissipation. The work presented in this paper includes a type of structural testing of
the decoder based on the observation of the cross-correlation between the output
voltage and the power supply current. The circuits power supply current (

) and the

output signal (in this case a voltage, v), are taken for cross-correlation. The deviations
of either or both V and

(dv and

respectively) are compressed or canceled out

after the cross-correlation. In above case if the deviation terms are canceled then the
correlation output will be equal to that of a fault-free one and the power dissipation
will be as same as that of fault free power dissipation.

15

Chapter 2

References
K. Arabi, B. Kaminska,Oscillation built-in self-test (OBIST) scheme for

[1]

functional and structural testing of analog and mixed-signal integrated

circuits.Proc.IEEE ITC, 1997, 786 795.
Vaishali Dhare and Usha Mehta, SAF analyses of analog and mixed signal

[2]

VLSI Circuit: digital to analog Converter, International Journal of VLSI

design &Communication Systems (VLSICS) Vol.6, No.3, June 2015.
Ms. Harshal Meharkure, Mr.Swapnil Gourkar,Fault Testing of Analog

[3]

Circuits Using Combination of Oscillation Based Built-In Self-Test and

Quiescent Power Supply Current Testing Method, IJAIEM,Volume 2, Issue
12, December 2013.
Amrita Oza, PoonamKadam, Techniques for Sub-Threshold Leakage

[4]

Reduction in Low Power CMOS Circuit designs, Volume 97 No.15, July

2014.
Chris Winstead, Nhan Nguyen, Vincent C. Gaudet and Christian Schlege,

[5]

Low-Voltage CMOS circuits for Analog decoders.

Jacob A. Abraham and Jeongjin Roh,A Comprehensive Signature Analysis

[6]

Scheme for Oscillation Test, IEEE Transactions on Computer Aided Design,

vol. 22, no.10, pp. 1409-1423, Oct. 2003.
Daniel Arbet and Viera Stopjakova, Libor Majer and Gabriel Nagi, New

[7]

OBIST using On-chip Compensation of process variations toward increasing

Fault Delectability in Analog ICs, IEEE Transactions On Nanotechnology,
vol.12, no. 4, pp. 486-497, July 2013.
Bechir Ayari, Naim Ben Hamida and Bozena Kaminska, Automatic Test

[8]

Vector Generation for Mixed-Signal Circuits Ecole Polytechnique of the

University of Montreal P.O. Box 6079, Station Centre-ville, Montreal, PQ,
Canada, H3C 3A7.

16

CHAPTER 3

ANALOG AND MIXED SIGNAL TESTING

As we know that the mixed circuit contains both analog and digital blocks
interfaced by a converter circuit (ADC, DAC), the testing of the circuit is also classified
into analog and digital signal testing respectively. The digital testing is quite simpler and
popular than the analog testing due to the structuralism nature and adaptive nature to the
computer tools. The disparity between these two testing approaches is acute in the sense
of test pattern generation. In digital testing, the BIST technique [3] has been implemented
from the primitive stage of testing. In addition, fault simulation is often used to access the
effectiveness of a set of test vectors in detecting faults that might occur during
manufacture. In contrast, the analog circuit design is less structured and lacking proper
design for testability method. Therefore in this project we are going for analog testing that
confront a general solution.

17

Chapter 3

3.1 Analog circuit Testing procedure

Purely analog ICs usually consist of few basic primitive circuits such as
amplifiers, comparators etc. To check functionality many parameters must be considered
for test. The test parameters are specified by designers and can be gain, offset voltage,
slew rate, signal-to-noise ratio, bandwidth, and so on. Testing methods which have been
adopted till now are noting but the traditional ones due to lack of standard fault models
for the analog circuits.

The basic steps which are being followed for analog circuit testing have been represented
by a flow-char t as given below Fig.3.1 [10].

Fig. 3.1 flowchart of analog testing

18

The above testing procedure is a generalized method of testing which almost similar to
that of OBIST method. Here there is no requirement of oscillatory circuit for the CUT
which is complex and lengthy one.

3.1.1 Fault list and Fault Model

In this project work two types of fault are being discussed such as Stuck at Open
and stuck at short which are predominant among all the faults and can be realized. These
are also called as catastrophic faults. The fault list contains two types of faults discussed
above. These two types of faults can be observed at each nodes of the IC therefore fault
list is prepared by considering all types possible short or open circuits in the ICs.

3.1.1.1 Stuck at open fault Model

In this fault model is prepared by connecting a high resistance in between the open
nodes/terminals as shown in Fig. Here the open circuit is realized by connecting high
resistance value nearly equal to Mega ohms in between the nodes.

Fig. 3.2 Fault Modeling

19

Chapter 3

3.1.1.2 Stuck at short fault Model

If there is any unnecessary shorting is present among the terminals of the devices
in the ICs fault model is prepared by connecting a low resistance (nearly 10 ohm) in
between the open terminals as shown in the above Fig.

3.1.2 Fault Injection

In this step all possible faults are being injected one by one in a sequence but
limitation is that only one fault can be injected at a time it is because we need to find out a
particular faulty node that is responsible for the fault if more than one fault is being
inserted at same time then it would be difficult to mark the single faulty node. Since the
structural elements that are present in the analog circuit are PMOS, NMOS and some
passive elements, the circuit is going to be faulty due to defects of the components only.
The defects may be due to:-

i.

Open or short circuit of the terminals (gate,source,drain)of either

PMOS or NMOS.

ii.

Open or Short circuit of the passive elements (resistor, capacitor)of the

circuit.

From the first step that is fault modeling, after all the faults being modeled, each fault are
injected for simulation.

20

3.1.3 Fault Simulation and comparison

The faults injected from above steps are simulated to find out the testing
parameters. Simultaneously the same parametric responses are being evaluated for a fault
free analog circuit after simulation for the given analog input signal which is also given to
the faulty circuits during simulation. Cadence tool is used to do the simulation. After
simulation the results of the particular testing parameter are compared. If the results are
same then the circuit under test (CUT) is said to be fault free else faulty.

3.1.4 Fault Coverage calculation

Fault coverage is the main indicator to check the quality of testing. It is expressed
in percentage. More fault coverage means better testing. if number of fault found for a
particular test is more than the fault coverage is also more. It is given by the formula:

of Fault Coverage

No. of faults found for a particular faulty

100
Total No. of faults

Better coverage gives better testing.

3.2 Mixed Signal Testing Procedure

As we know that SoCs contain both analog and digital blocks interfaced by a
converter, testing should be done to verify all the blocks and the input signals are
different for analog and digital blocks. Therefore the entire circuit testing is carried out in
the similar way of either analog testing or digital testing. If we follow the way of analog
testing then a particular fault is inserted in analog block and is propagated to the digital

21

Chapter 3
block to check the response in digital block. Similarly if we follow the way of digital
testing then a particular fault is inserted in digital block and is propagated to the analog
block to check the response in analog block. All the steps those are mentioned in the
flowchart of the analog testing remains same for mixed signal testing.

Suppose consider the mixed circuit [2] consists of analog filter followed by a
digital circuit with an ADC interface as shown in the Fig 3.3.

Fig.3.3 Mixed signal testing circuit

In mixed signal testing instead of fault modeling, fault activation process is being
introduced. If we apply a signal in the analog primary input, all the primary inputs of the
digital part controlled by this analog input will have either a logic value 0 or 1.Here if we
want to generate test vectors for the analog parts of the mixed, first we have consider an
element of the analog circuit to be faulty. Then the fault is propagated to the digital part
through the ADC.Due to the elemental faulty, at least one output of ADC is being
affected and would show a deviation which becomes the input to the digital block. In this
case choosing the input signal i.e. the amplitude and the frequency is very important as
while considering the tolerance of elements in analog circuits, the parameters to be tested
should have different values for inside boundary limits as well as outside boundary limits
of the faulty element. In this way fault is being activated.

22

To test a parameter P, the deviation is calculated as ( ).Taking tolerance as

variance the upper and lower bound of the parameter is evaluated. After simulation if the
parameter value of the testing circuit remains within the boundary[P )] values i.e the
output parameter value of the fault free circuit then the circuit is said to be fault free else
faulty.

The fault coverage of the mixed signal may be equal or less than that of analog
and digital testing fault coverage because as per the circuit given in Fig 3.3 only some of
the inputs to the digital block are controlled by analog block. There may be chance of
fault due to the rest inputs of the digital part.

References
[1]

K. Arabi, B. Kaminska,Oscillation built-in self-test (OBIST) scheme for

functional
and structural testing of analog and mixed-signal integrated circuits.Proc.IEEE
ITC, 1997, 786 795.

[2]

Vaishali Dhare and Usha Mehta, SAF analyses of analog and mixed signal VLSI
Circuit: digital to analog Converter, International Journal of VLSI design
&Communication Systems (VLSICS) Vol.6, No.3, June 2015.

[3]

Ms. Harshal Meharkure, Mr.Swapnil Gourkar,Fault Testing of Analog Circuits

Using Combination of Oscillation Based Built-In Self-Test and Quiescent Power
Supply Current Testing Method, IJAIEM,Volume 2, Issue 12, December 2013.

[4]

Amrita Oza, PoonamKadam, Techniques for Sub-Threshold Leakage Reduction

in Low Power CMOS Circuit designs, Volume 97 No.15, July 2014.

23

Chapter 3
[5]

Chris Winstead, Nhan Nguyen, Vincent C. Gaudet and Christian Schlege, LowVoltage CMOS circuits for Analog decoders .

[6]

Jacob A. Abraham and Jeongjin Roh,A Comprehensive Signature Analysis

Scheme for Oscillation Test, IEEE Transactions on Computer Aided Design, vol.
22, no.10, pp. 1409-1423, Oct. 2003.

[7]

Daniel Arbet and Viera Stopjakova, Libor Majer and Gabriel Nagi, New OBIST
using On-chip Compensation of process variations toward increasing Fault
Delectability in Analog ICs, IEEE Transactions On Nanotechnology, vol.12, no.
4, pp. 486-497, July 2013.

[8]

Bechir Ayari, Naim Ben Hamida and Bozena Kaminska, Automatic Test Vector
Generation for Mixed-Signal Circuits Ecole Polytechnique of the University of
Montreal P.O. Box 6079, Station Centre-ville, Montreal, PQ, Canada, H3C
3A7.

[9]

J. Roh and J. A. Abraham, A comprehensive signature analysis scheme for

oscillation-test, IEEE Trans. Comput.-Aided Design, vol. 22, no. 10, pp. 1409
1423, Oct. 2003.

[10]

Sunil R. Das, Jila Zakizadeh, Satyendra Biswas , Testing Analog and MixedSignal Circuits With Built-In HardwareA New Approach , IEEE transactions
on Instrumentation and measurement, vol. 56, no. 3, June 2007.

24

CHAPTER 4

POWER MINIMIZATION OF LOW POWER

CIRCUITS DURING TESTING

With respect to the changing trend of technology the transistor count increases
within the chip having constant area. Therefore power density increases which results in
temperature increment in the circuit and can burn the device. High frequency applications
of analog devices also consume more energy. In mixed signal circuits as the converter
responds to both digital as well as analog signals which consumes different power. This
variation in power may change the temperature of the circuit and as a consequence the
circuit performance is being affected. Therefore power management is also important for
the proper functionality of the circuit.

25

Chapter 4
Scaling of technology node increases power-density more than expected. CMOS
technology beyond 65nm node represents a real challenge for any sort of voltage and
frequency scaling Starting from 120nm node, each new process has inherently higher
dynamic and leakage current density with minimal improvement in speed. Between 90nm
to 65nm the dynamic power dissipation is almost same whereas there is ~5% higher
leakage/mm2.Low cost always continues to drive higher levels of integration, whereas
low cost technological breakthroughs to keep power under control are getting very scarce.

Power Management matter in System on Chip due to following concerns-

i. Packaging and Cooling costs.

ii. Digital noise immunity.
iii. Battery life (in portable systems)
iv. Environmental concerns.

4.1 Sources of Power Dissipation

The power dissipation in low power VLSI circuits can be classified into three
categories as described below-

4.1.1 Dynamic Power Consumption

It is due to the logic transitions causing logic gates to charge or discharge of load
capacitance.

26

4.1.2 Short Circuit Current

In CMOS logic P-branch and N-branch are momentarily shorted as logic gates
changes state resulting in short circuit power dissipation.

4.1.3 Leakage Current

This is the power dissipation that occurs when the system is in standby mode or not
powered. There are many sources of leakage current in MOSFET like Diode leakages
around transistors and n-wells, Sub threshold Leakage, Gate Leakage, Tunnel Currents
etc. These leakage currents increases 20 times for each new fabrication technology and
turns from insignificant to a dominating factor. Moreover thinner gate oxide layer also
increases leakage current.

To curb the problem of power dissipation here in this paper, a special attention has
been given to reduce the leakage power, miniaturaization in feature size, short channel
lengths and low threshold voltage tends to increase the sub threshold leakage current.
Therefore the transistor doesnt turn off completely when it is off thereby increasing static
power dissipation.

4.2 Leakage Reduction Methods

The stand by duration of microelectronic circuits leads to leakage power

dissipation. Various leakage reduction techniques are being adopted [4] such as-

27

Chapter 4

4.2.1 Stack Effect Based Technique

Some NMOS and PMOS can be added in series with gates to increase the stack
effect and reduce the leakage.

Fig. 4.1 Gate without stacked NMOS

Fig. 4.2 Gate with stacked NMOS

In Fig.4.1 and Fig.4.3 the output of the gate is high in standby mode that is the pull
down network is off .Hence putting an off transistor in series with the pull down network
in standby mode will not change the output value. This increases the resistance between
supply and ground. Thereby reducing leakage of logic as shown in Fig.4.2

Fig. 4.3 Gate without stacked PMOS

Fig. 4.4 Gate with stacked PMOS

28

From Fig.4.4 the insertion of a leakage control transistor which can shared by
multiple gates, by dividing the circuit and stacking into two half width of the total
transistor size which reduces the sub threshold current. Here stacked transistors turns ON
and OFF simultaneously. A positive potential is gets generated at the stacked transistor
node due to which gate to source voltage becomes negative and hence sub threshold is
minimized.

4.2.2 Current Correlator Circuits

A current correlator can also be used to minimize the power dissipation.Low

voltage analog circuits are the extension of the well known current correlator circuit.In
Fig. M4 transistor is not in saturation.The behaviour of a nonsaturated NMOS in weak
inversion is given by,

(4.1)

Where

the transistor gate voltage is

is source voltage and

is drain voltage.

The transistor model from the equation has been simplified to ignore body effect and
transistors output resistance. The current

are split into forward and reverse

components.
(4.2)
(4.3)

(4.4)

29

Chapter 4
The forward and reverse components from figure are represented by If4 and Ir4
respectively. The sum of voltages in Kirchhoffs loop is as same as to the product of
currents along that loop.

Fig. 4.5 current correlator

From the loops in the circuit, Thus in close loop traversing gate-source voltage, the
product of currents in clock wise current equals to the anti clock wise. i.e
(4.5)
(4.6)
(4.7)

30

Finally,

(4.8)

For number of inputs and outputs as shown in Fig. the formula can be derived as,

(4.9)

31

Chapter 4

32

CHAPTER 5

PROPOSED METHOD FOR ANALOG CIRCUIT

TESTING BASED ON LOOK UP TABLE

After the study of different analog and mixed signal research work, it is found out
that analog testing still faces many challenges during testing. Realization of analog signal
testing at the structural level is a difficult task since in an analog circuit there exists either
a range of outputs for a given input or a range of input possesses a common output.
Therefore there would be chance of collision among the input output patterns generated
by the system. Therefore there is no such pattern generator for analog testing circuits. The
Fuzzy nature of the output response is due to dynamic tolerance levels of the analog
circuit elements. Hence in this proposed work only parametric testing is taken into
consideration.

33

Chapter 5
In literature review, for analog testing, it has been discussed to check whether the analog
module is faulty or fault-free. For a qualitative and quantitative product marketing it is
important for the manufacturer to separate the fault chips from that of fault free chips. On
the other side as per the manufacturing point of view, it is necessary to find out the faulty
circuit and the fault node or nodes those are responsible for a particular kind of fault of
the faulty circuit. If the manufacturer is able to find out the defect and reason behind it
then the particular error can be resolved during further fabrication process ahead.

As we know, the testing circuit consumes nearly double power than the standard circuit.
While testing we are taking two circuits (one is fault free circuit and the other is the
Circuit under Test) .Therefore the testing circuit consumes almost twice power than that
of a normal one. So if power dissipation increases in the circuit, the temperature of the
circuit will also increase in a proportion. As a result, the components in the circuit may
burn out which may indicate the testing circuit as faulty though it is fault free. Therefore,
power dissipation should be minimized during testing. Injecting faults one by one and
checking the outputs accordingly is a time taking and a manual process. Therefore to
make the testing process easier there should be a classification of faults as per their
similarity behavior and according to their priority. It would be better to test the faults as
per the priority of occurrence. Most frequently observed faults should be tested first as
compared to the faults having low priority. All the above issues have been addressed in
the proposed approach of analog testing. An operational Amplifier of inverting type is
taken as the Circuit under Test (CUT) for analog testing. After fault modeling each fault
is injected and simulated sequentially as explained in subsequent section. In this work, a
programming approach has been adopted to find out the faulty circuit and also the fault
part of the circuit.The flowchart of the proposed method is given in Fig.5.1.

34

Faulty outputs in file(LUT)

output
Insert the output to be tested
output
Check with
fault-free o/p

Yes
O/p==fault
free o/p?

Stop
testi
ng

Insert
faults
Equal=?

Check o/p with LUT

Yes
All faults
injected?

Type of fault
found

Fault coverage calculation

Fig. 5.1 flowchart of proposed testing hierarchy

An LUT is prepared for the testing parameter (here output voltage) of the fault models
and fault free model of Operational Amplifier. LUT is used to store the output voltage
values for an analog input (here 5mV peak to peak)after the simulation in virtuoso
cadence tool using 45nm technology. The outputs those are stored in LUT as reference is
taken for same time samples. While testing the output response (output voltage) of the
CUT is stored in a file for the same analog input and same time samples. The results of
the faulty circuit stored in a file are then compared with the fault-free circuit output of
LUT. While comparing the outputs, a range of output is considered for fault free one
because due to tolerance level of passive elements, a band of outputs could be possible for
a given input. To sort out this issue, only the MAX and MIN values are being taken and
stored in LUT. Then the output voltage of CUT is compared with LUT .After comparison
if result matches then we can say that it is the fault-free circuit. But to find out the faulty
node, the entire fault should be stored in files as reference. That is termed as the Look up
Table for the testing. Then while finding the fault type the output of the circuit to be

35

Chapter 5
tested is compared with the faulty reference data of LUT. The node at which a match is
found after comparison, we can say that particular node is faulty. After completion of all
the comparisons, the fault coverage has been calculated.

The flowchart given in Fig.5.1 is somewhat similar to that of flowchart as mentioned in

OBIST [3] method. There is some modification has been done for this new programming
approach. The steps followed in the programming approach are described below-

Step1: First Fault list is prepared which contains all possible combinations of
Faults.

Step2: According to fault list all types of faults are modeled. Besides this in this
Step one fault free model is also prepared.

Step3: All the models are simulated in virtuoso cadence tools.

Step4: the simulated outputs are exported to a file in .txt format.

Step5: The CUT is now simulated similar to the fault models.

Step6: By using C-programming the output result of fault free and CUT are
Compared. If Values are equal then the CUT is said to be fault free else
Faulty.

Step7: If circuit is faulty then we need to know the Type of fault due to which
Circuit becomes dysfunctional.

Step 8: This above process is continued till all the faults are being inserted.

Step9: Fault Coverage is calculated.

Step10: Step 1-9 are being followed for different testing parameters.

5.1 Operational Amplifier as the Circuit under Test

Operational Amplifier normally consists of four stages. But here for simplicity of
testing, a two stage op-amp is designed i.e. a differential amplifier in the first stage and a
gain stage as the second stage. To design it by Cadence tool using 45nm technology, the
width to length ratios for PMOS and NMOS are derived from the circuit specifications

36

given for the design. The particular design consists of eight MOS transistors (2 PMOS
and 6 NMOS), a current source and two resistors. Since we have considered only two
stages, the gain is less than that of a typical four-stage Operational Amplifier. The design
is havingi.

Gain=43dB.

ii.

The two PMOS have width to length ratio of 20:1.

iii.

Two NMOS of the differential amplifier having a width to length ratio of 15:1.

iv.

The gain stage is a common drain stage consists of two NMOS having a width to
length ratio 20:1 and 2:1 respectively.

v.

A current source of 20 micro Amps.

vi.

The power supply of +1.8 and -1.8 volts used as Vdd and Vss.

After designing an Op-Amp that is fault free, stuck at open and stuck at short fault models
are being designed. After designing, faults are injected into test circuit one by one until all
faults are being covered. Steps are as follows.

5.2 Fault list and fault Model

Two types of faults are considered - stuck at open and stuck at short as shown in
the Fig. 5.3 and Fig 5.4.

37

Chapter 5

Fig. 5.2 stuck at short model of an Op-Amp

Fig.5.3 stuck at open model of an Op-Amp

38

In this proposed work all possible and frequently observed faults are being listed
and are represented by a particular fault model. If the gate terminal of a PMOS is opened
or shorted then both the faulty are modeled separately. In this way almost all fault models
are designed by a fault number as shown in the fig.54.e.g.Fault 5 indicates that the
Source(S), Gate (G), Drain (D) of the PMOS (PM1) is opened. Here taking 8 transistors
and 2 resistors into consideration, 32 fault models are prepared for simulation. By taking
tolerance of resistors is nearly about 5% all the fault models are designed and simulated.

39

Chapter 5
Fault model
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Cause of the particular fault

Fault free Op-Amp ckt
PM2(S,G,D) open of diff_part of Op-Amp
PM2(G) open of diff part of Op-Amp
PM2(S,D) open of diff part of Op-Amp
PM2(S,D) shot differential part of Op-Amp
PM1(S,G,D) open of diff_part of Op-Amp
PM1(G) open of diff Op-Amp
PM1(S,D) open_diff Op-Amp
PM1(S,D) shot of diff Op-Amp
NM0(S,D,G) open of diff Op-Amp
NM0(G) open of diff Op-Amp
NM0(S,D) open of diff Op-Amp
NM0(S,D) short of diff Op-Amp
NM1(S,G,D) open of diff Op-Amp
NM1(G) open of diff Op-Amp
NM1(S,D) open of diff Op-Amp
NM1(S,D) short of diff Op-Amp
NM2(S,G,D) open of diff Op-Amp
NM2(G) open of diff Op-Amp
NM2(S,D) open of diff Op-Amp
NM2(S,D) short of diff Op-Amp
NM3(S,G,D) open of diff Op-Amp
NM3(G) open of diff Op-Amp
NM3(S,D) open of diff Op-Amp
NM3(S,D) short of diff Op-Amp
NM2(S,G,D) open of CS of Op-Amp
NM2(G) open of CS part of Op-Amp
NM2(S,D) open of CS part of Op-Amp
NM2(S,D) short of CS part of Op-Amp
NM0(S,G,D) open of CS part of Op-Amp
NM0(G) open of CS part of Op-Amp
NM0(S,D) open of CS part of Op-Amp
NM0(S,D) short of CS part of Op-Amp
Table 5.1 Fault Models due to different faulty nodes

40

5.3 Fault injection and comparison

After fault modeling, each fault is injected and simulated sequentially by a

multiplexor. The simulated outputs of the fault models are compared with the simulated
output of fault free model. Here two comparators are used to check the fault model output
with the upper and lower threshold of fault free one as shown in Fig 5.5.The threshold
value is considered because in the analog circuit the output possesses a range of values
depending upon the tolerance of electrical elements like a resistor, inductor, and
capacitor. For the case of inverting Op-Amp two resistors, R1 and R2 having a tolerance
of 5% can vary the inverting gain (R2/R1). Accordingly we got a maximum output limit
and minimum output limit. If the output of the fault model is within the maximum and
minimum range, then the comparator will give a pulse signal. If the two pulse signals are
same then the circuit does not have the particular fault, it then jumps for next fault test.

Fig.5.4 circuit diagram of single fault injection for an Op-Amp

41

Chapter 5

Fig.5.5 Block diagram of testing circuit for all injected faults

5.4 Fault coverage

The simulated output like output voltage, gain and average power has been
checked with the fault-free output. Fault coverage is calculated for individual parameters
using the formula-.

Fault Coverage

No. of fault found after testing

Total No. of faults

42

Fault coverage is expressed in percentage. Fault coverage x % means out of 100 possible
faults,x number of faults can be tested for a circuit and (100-x) number of faults cant be
detected though those are defective. Therefore more fault coverage gives better testing.

5.4 Power Minimization during testing

From the testing point of view, the testing power is nearly double to that of the
normal mode of operation. Leakage current is the major contributor of total power
consumption in the integrated devices in todays submicron technology. For example, in
circuit of Fig. 2 if the circled resistor is short circuited then high current will flow and
during testing of stuck at short fault of this element leads to high power dissipation due to
high current flow. This leads to leakage current during testing. Leakage reduction
techniques are used to minimize leakage current.

Leakage reduction includes adding a sleep transistor between actual ground

terminal and circuit ground (termed as the virtual ground) as shown in Fig.8. In sleep
mode to cut-off, the leakage path the sleepy transistor is turned off. High threshold sleep
transistor is used that cuts-off Vdd from the circuit when no switching activity is going on.
The circuit diagram for leakage reduction is shown in Fig 7. Here a NMOS is connected
between virtual GND and actual GND.

In this testing, a current correlator can also be used to minimize the power
dissipation. The work presented here is a type of structural testing of the op-Amp based
on the observation of the cross-correlation between the output voltage and the power
supply current. The circuits power supply current (

) and the output signal (in this case

a voltage, v), are taken for cross-correlation. Before the cross-correlation, the faulty signal
is modeled as the sum of the good one and the deviation.

43

Chapter 5
(5.1)

I and is equal to,

The cross correlation can be expressed as V

( )

( )

( ))(

( )

The deviations of either or both V and

) )

( )

(dv and

(5.2)

(5.3)

respectively) are

compressed or canceled out after the cross-correlation. In above case if the deviation
terms are canceled then the correlation output will be equal to that of a fault-free one and
the power dissipation will be as same as that of fault free power dissipation. For the above
testing current correlator used as shown in Fig.5.3 and the testing circuit is shown in Fig
5.4.

44

Fig.5.3 Current correlator circuit

Fig.5.4 Testing Op-Amp circuit with current correlator

45

Chapter 5
In Fig 5.3, transistors are assumed to operate in the sub-threshold region.

Where,

is the transistors specific current,

(5.4)

, and

are respectively the

transistors gate, source, and drain voltages, K0.7 is the back-gate coefficient, and the
voltages are given in units of the thermal voltage (

= kT/q 26 mV at 300K). From

Fig. 8 by developing the sum of voltages in the Trans linear loop it can be shown that
(VGSNM1 + VGDNM2 VGSNM3 + VGSNM0 = 0), and assuming that all transistors except NM2
are saturated, the output current can be derived as,

(5.5)

Where,

(5.6)

is the resultant of the self-normalized correlation of currents

and

. It is symmetric in

the two input currents. The final output voltage V is obtained from the cross-correlation
of power supply current
output voltage (

and output voltage v.

is converted into an integrated

), that is

(5.7)

46

Where the Trans conductance gain g is defined by ,

is defined by ,

and

, and

and V, the current gain h

is the correlators output Trans resistance.

References
[1]

K. Arabi, B. Kaminska,Oscillation built-in self-test (OBIST) scheme for

functional
and structural testing of analog and mixed-signal integrated circuits.Proc.IEEE
ITC, 1997, 786 795.

[2]

Vaishali Dhare and Usha Mehta, SAF analyses of analog and mixed signal VLSI
Circuit: digital to analog Converter, International Journal of VLSI design
&Communication Systems (VLSICS) Vol.6, No.3, June 2015.

[3]

Ms. Harshal Meharkure, Mr.Swapnil Gourkar,Fault Testing of Analog Circuits

Using Combination of Oscillation Based Built-In Self-Test and Quiescent Power
Supply Current Testing Method, IJAIEM,Volume 2, Issue 12, December 2013.

[4]

Amrita Oza, PoonamKadam, Techniques for Sub-Threshold Leakage Reduction

in Low Power CMOS Circuit designs, Volume 97 No.15, July 2014.

[5]

Chris Winstead, Nhan Nguyen, Vincent C. Gaudet and Christian Schlege, LowVoltage CMOS circuits for Analog decoders .

[6]

Jacob A. Abraham and Jeongjin Roh,A Comprehensive Signature Analysis

Scheme for Oscillation Test, IEEE Transactions on Computer Aided Design, vol.
22, no.10, pp. 1409-1423, Oct. 2003.

[7]

Daniel Arbet and Viera Stopjakova, Libor Majer and Gabriel Nagi, New OBIST
using On-chip Compensation of process variations toward increasing Fault
Delectability in Analog ICs, IEEE Transactions On Nanotechnology, vol.12, no.

47

Chapter 5
4, pp. 486-497, July 2013.

[8]

Bechir Ayari, Naim Ben Hamida and Bozena Kaminska, Automatic Test Vector
Generation for Mixed-Signal Circuits Ecole Polytechnique of the University of
Montreal P.O. Box 6079, Station Centre-ville, Montreal, PQ, Canada, H3C
3A7.

[9]

J. Roh and J. A. Abraham, A comprehensive signature analysis scheme for

oscillation-test, IEEE Trans. Comput.-Aided Design, vol. 22, no. 10, pp. 1409
1423, Oct. 2003.

[10]

Sunil R. Das, Jila Zakizadeh, Satyendra Biswas , Testing Analog and MixedSignal Circuits With Built-In HardwareA New Approach , IEEE transactions
on Instrumentation and measurement, vol. 56, no. 3, June 2007.

48

CHAPTER 6

PROPOSED METHOD FOR MIXED SIGNAL

TESTING BASED ON LOOK UP TABLE
Mixed circuit is a conjunction of both analog and digital circuits which are
interfaced by an ADC or DAC. Though there are many paper works have been proposed
for digital and analog signal testing separately, mixed signal testing still faces challenges.
From [2] the basic steps have been adopted for mixed signal circuits which are almost
similar to that of analog and digital testing techniques. In case of mixed signal circuit, the
entire circuit testing is carried out in the similar way of either analog testing or digital
testing as discussed in chapter 3. If we follow the way of analog testing then a particular
fault is inserted in analog block and is propagated to the digital block to check the
response in digital block. Similarly if we follow the way of digital testing then a particular
fault is inserted in digital block and is propagated to the analog block to check the
response in analog block.

49

Chapter 6
For mixed signal testing the first step is fault activation instead of fault modeling. The rest
steps are similar to analog signal testing like-fault injection, simulation, comparison and
fault coverage calculation. Due to limited time here in this project the fault activation part
has been covered, the further steps can completed in future.

Here the mixed circuit consists of a digital bench mark circuit(C-17) followed by an
analog circuit(2nd order filter) interfaced by a converter(ADC) as shown in the fig 6.1.In
this circuit some of the inputs(here 4) for C-17 circuit are coming from ADC but one
input is coming from the primary input.

Fig. 6.1 Mixed circuit for testing

50

6.1 Fault Activation (step 1)

In order to check the response of an analog signal at the digital part , first we have
to give some fault models in analog part. Here if we want to generate test vectors for the
analog parts of the mixed, first we have consider an element of the analog circuit to be
faulty. Then the fault is propagated to the digital part through the ADC.Due to the
elemental faulty, at least one output of ADC is being affected and would show a deviation
which becomes the input to the digital block. In this case choosing the input signal i.e. the
amplitude and the frequency is very important as while considering the tolerance of
elements in analog circuits, the parameters to be tested should have different values for
inside boundary limits as well as outside boundary limits of the faulty element. In this
way fault is being activated.

References
[1]

K. Arabi, B. Kaminska,Oscillation built-in self-test (OBIST) scheme for

functional
and structural testing of analog and mixed-signal integrated circuits.Proc.IEEE
ITC, 1997, 786 795.

[2]

Vaishali Dhare and Usha Mehta, SAF analyses of analog and mixed signal VLSI
Circuit: digital to analog Converter, International Journal of VLSI design
&Communication Systems (VLSICS) Vol.6, No.3, June 2015.

[3]

Ms. Harshal Meharkure, Mr.Swapnil Gourkar,Fault Testing of Analog Circuits

Using Combination of Oscillation Based Built-In Self-Test and Quiescent Power
Supply Current Testing Method, IJAIEM,Volume 2, Issue 12, December 2013.

51

Chapter 6
[4]

Amrita Oza, PoonamKadam, Techniques for Sub-Threshold Leakage Reduction

in Low Power CMOS Circuit designs, Volume 97 No.15, July 2014.

[5]

Chris Winstead, Nhan Nguyen, Vincent C. Gaudet and Christian Schlege, LowVoltage CMOS circuits for Analog decoders .

[6]

Jacob A. Abraham and Jeongjin Roh,A Comprehensive Signature Analysis

Scheme for Oscillation Test, IEEE Transactions on Computer Aided Design, vol.
22, no.10, pp. 1409-1423, Oct. 2003.

[7]

Daniel Arbet and Viera Stopjakova, Libor Majer and Gabriel Nagi, New OBIST
using On-chip Compensation of process variations toward increasing Fault
Delectability in Analog ICs, IEEE Transactions On Nanotechnology, vol.12, no.
4, pp. 486-497, July 2013.

[8]

Bechir Ayari, Naim Ben Hamida and Bozena Kaminska, Automatic Test Vector
Generation for Mixed-Signal Circuits Ecole Polytechnique of the University of
Montreal P.O. Box 6079, Station Centre-ville, Montreal, PQ, Canada, H3C
3A7.

[9]

J. Roh and J. A. Abraham, A comprehensive signature analysis scheme for

oscillation-test, IEEE Trans. Comput.-Aided Design, vol. 22, no. 10, pp. 1409
1423, Oct. 2003.

[10]

Sunil R. Das, Jila Zakizadeh, Satyendra Biswas , Testing Analog and MixedSignal Circuits With Built-In HardwareA New Approach , IEEE transactions
on Instrumentation and measurement, vol. 56, no. 3, June 2007.

52

CHAPTER 7

RESULTS AND DISCUSSIONS

As discussed above in chapter (3) an Operational Amplifier is taken as Circuit
Under Test (CUT) for analog testing. A two stage Op-Amp is designed in Virtuoso
analog environment of Cadence Tool using 45nm technology as per the Specifications
discussed in chapter (3). In[3] during testing the DUT is converted into an oscillator
circuit which is little bit compex as it is not easier to convert a circuit into an oscillator
and the component requirement also increases in this testing method.As discussed in
chapter(4), first different fault models are designed in cadence Tool. Then the simulation
outputs are saved in the LUTs after fault injection.Here output voltage, dc gain and
average power are taken as testing parameters. After simulation of the fault free circuit
the outputs are stored in different files with respect to using C-programming.Since
analog signal is continuous, if we consider a input signal of 5mV for a time period
suppose 10nS then while exporting the output in a file there exists infinite number output
values with respect to time.There for in order to decrease the execution time,the time is
sampled to a finite number of samples(here 50 samples has been taken).The data stored in

53

Chapter 7
the files in the form of LUTs. The data stored in .txt files are considered as the references
for fault free model and 32 fault models.While testing, the measured output of the
particular device to be tested is then compared with the faultfree output which is already
stored in .txt file. If the output matches with the referred value then we can say that our
test as P (i.e circuit is fault free w.r.t that parameter) otherwise test F (circuit is faulty
w.r.t that parameter).Likely the target circuit output is then compared with 32 fault results
sequentially and when there is an equality found then we can say that the testing circuit
has a particular fault according to the matching result. For example if after simulaton of
an Op-Amp the output voltage is in the rage of 161~224mv( as per entry in row no 2 of
the table (fault no 0) )then there exists no fault in the circuit but if not then the circuit is
considered as faulty.The next aim of the project is find out the fault location.For that
again the output results are compared with the individual fault results(from fault 1 to fault
32) from the Look up Table.Lets assume after simulation the output voltage of the DUT is
in the range of 175~198.8mV then the fault location is found at the gate node of
PM1(PMOS of the Op-Amp).

54

Chapter 7

Fault
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Vout(mv)
161-224
789-797
855-864
-249~-221
-249..-221
-249..-221
175~198.8
153~217
800~808
-249~-221
167-211
-249~-221
800~808
800~808
173~192
800~808
206~233
206~233
735~741
303~338
-348~-314
-182~-136
174~202
-171~-126
635~665
135~201
113~131
-175~-165
135~201
205~251
114~167
139~193
~7869

Remark
NA
F
F
F
F
F
P
F
F
F
P
F
F
F
P
F
F
F
F
F
F
F
P
F
F
F
F
F
P
F
F
F
F

Gain(dB)
-43.1 ~-43.4
-46.3~-46.3
~-46.02
-59.7~-59.7
-6.4K
-46.3~-46.3
-6.4k
-6.4k
-58.3 ~-59.3
~46.36
-46.3~-59.6
-59.7~ -59.7
-59.39
-72.7~-58.7
-46.3~-46.3
~-58.74
-46.3~-46.3
-46.3~-46.3
-46.3~-46.3
-46.3~-46.3
~46.36
-64.6~-66.6
~46.33
-64~-66.9
~-46
~46.36
~46.36
-46.21
-46.35
-46
-46.23
-46
-49.9~-50.2

Remark
NA
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

P(avg)(w)
212.9-213.5
315-325
237-248
3769-3774
139 to 139.1
~141
217.7~218.2
214.6~215.2
323-333
56.1~56.4
218.7~219.2
56.3~56.4
348~358
320~330
~215
320~330
~21
~21
~125
151~153
~6712
2865~6231
~218
~81080
104~108
217~218
244~245
~125
217~218
~134
178~179
125.5
4509~4501

Remark
NA
F
F
F
F
F
F
P
F
F
F
F
F
F
P
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

Table 7.1. Look up Table of fault simulation(no power Min.)

Table 2 is the Look up Table for parameters like output voltage, gain and
average power. The Simulation outputs of both fault free and faulty circuit have been
stored prior to the testing process.

55

Chapter 7
Fault
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Vout(mv)
884~897
991.8~992.4
994~995
922~923
872~873
872.8~873.3
882~887
879-890
992.4~992.9
871.6~871.8
~872
872.8~873.2
992.5~993
992.4~992.9
881~886
992.4~992.9
~873
913~922
880~891
915~923
872~886
~987
880~891
~987
~984
~887
~887
873-875
874
~875
876
887-883
~972

Remark
NA
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
P
F
P
F
F
F
F
F
F
F
F
F

P(avg)(w)
191.5-194
313-323
239-250
667-671
176-177
178~179
207~210
202~206
321-332
97.3-98.6
211~221
97.4~98.6
349~359
319~329
202~206
319~329
180~181
180~181
152~153.5
153~154
552~555
720~730
208~211
730
113~120
201~206
164~167
155~157
201~206
133~165
~168.5
1~25
721~728

Remark
NA
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F

Gain(dB)
-59.75 ~ -59.8
-59.73~-59.77
-59.22
-59.73~-59.77
-6.4k
-59.73~-59.77
-6.4k
-6.4k
-72.03~-72.66
-59.83
-59.74~-59.78
-46.34~-46.36
-59.33~72.7
-72.69~-72.05
-59.77~-59.74
-72.69~-72.06
~59.77
~59.77
~59.77
-46.34~59.77
-~59.84
-95~-93
~59.7
-94~96
~-59.2
~59.8
-59.9
-59.55~-59.5
-59.77~-59.8
~-59.23
-59.6
-46
-106~112

Remark
NA
P
F
F
F
F
F
F
F
F
F
F
F
F
F
F
P
P
P
F
F
F
F
F
F
F
F
F
F
F
F
F
F

Table 7.2. Look up Table of fault simulation with power Min.

In Table 2 is the Look up Table for the same parameters like table 1 have been
considered. In the second case the power minimization technique like sleepy stack and
current correlator has been added to the normal testing circuit to reduce the power during
testing. From Table 1 and Table 2 the fault coverage has been calculated as-

56

Chapter 7

Parameter

Total Faults

Vout
Pavg
Gain(dc)

32
32
32

Fault Coverage
Without Power Min.
Detected
% Coverage
27
84.375
30
93.75
32
100

With Power Min.

Detected
% Coverage
30
93.75
32
100
28
87.5

Table 7.3.Fault Coverage

Fig 7.1. Fault coverage for different parameters

In OBIST Method [3] the outputs waveform of both fault free and faulty circuits have
to be visualised and compared on the display. But as per the proposed programming
method the discrete values(50 samples) of the outputs are being taken for comparison. It
is better to take the time sample for a single period.Fault coverage in manual method is
84.375%. In the proposed method fault coverage of output voltage has been enhanced to
93.75% in power minimization technique as compared to that of 84.375% (normal mode).
More coverage gives a better testing approach. If fault coverage is 100% then the testing
is said to be the best testing. Here fault coverage for average power is better than other
two parameters (output voltage). Here only 32 fault models have been designed if we
increase the no. of fault models then fault coverage will also increase.
i.

Though in OBIST method we can increase the fault coverage by injecting more
no. of faults, the exact fault coverage can be calculated by following an
algorithmic approach.

ii.

It has better fault coverage than the OBIST method.

57

Chapter 7
iii.

For a faulty block here we can predict the particular faulty node.

iv.

Testing power is also minimized to some extent using sleepy stack and current
correlation method. The percentage of power saving is as given in Fig.

150

Power Saving

% Power
saving

100

% power saving

Fault No.

50
0

-50

-100

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

Fault No.

Fig 7.2. % power saving

Here power minimization is taken into priority because it has been observed from
Look up Table that in case of some particular faults the circuit average power reaches to a
high value which is hundred time greater than that of a normal circuit (consider the case
of fault no 20, 23) due to open and short circuit of the terminals which can burn the
testing kit or increase the temperature of the testing kit which would lead to a wrong
testing. But by using the power minimization technique like sleepy transistor and current
correlator simultaneously, the power has been minimized that is made comparable to that
of a normal circuit (consider the Look up Table 2 for fault 20 and 23).
In this proposed method three parameters(output voltage,gain,average power) are
considered as testing parameter which has been increased the quality of testing as
compared to OBIST method where only one parameter is being tested. Multiple
parametric testing is more better because it may also happen that one circuit is fault free
w.r.t one parameter and could be faulty w.r.t other parameters and testing of more
parameters will make the testing more relevant.Threrefore this technique has more
accuracy than OBIST. In OBIST only one fault is being tested at once by comparing the
outputs, but in this proposed method all the possible faults are being tested sequentially.
Previously there was no such power reduction techniques are being applied which now
one of the major issues that is found during testing. Instead of comparing infinite points

58

Chapter 7

here no of testing points are reduced by sampling the simulation time into finite number
of time instants. Here LUT based programming approach improves hardware complexity
and reduces testing time.

59

Chapter 7

60

CHAPTER 8

CONCLUSION AND FUTURE SCOPE OF STUDY

8.1 Conclusion

Fault analysis has been carried out for an Operational Amplifier in Virtuoso
analog environment of the cadence tool using 45nm technology. The stuck open and stuck
short transistor fault model is used for the fault analysis.Characteristics Parameter has
been observed for stuck open and stuck short faults. By observing the variations in the
characteristics parameter, the respective faults are identified.

In the first part we have calculated the Fault Coverage of OBIST method is 84.37%
without power reduction technique and that is improved to 93.45% by the proposed

61

Chapter 8
programming approach along with the power reduction technique. Here along with the
improved fault coverage, the particular faulty node can be detected. In OBIST method the
faults are injected one by one manually but in programming or algorithmic approach all
faults are tested sequentially according to the algorithm and the analog circuit is tested
with exact fault coverage with in a lesser time. It has been also found that among all
parametric testing; average power and dc gain test has shown better fault coverage than
output voltage testing for same number of fault models. During testing power
minimization techniques are applied. Sleepy stack approach with a current correlator is
able to reduce the testing power of the circuit as shown in the result section. The main
advantage of the minimization technique is that the power is reduced at the fault levels at
a high percentage (~80%) whenever the circuit consumes a high power.

8.2 Future Scope

Successful implementation of analog and mixed signal testing would reduce the cost and
testing time and would increase the yield of the SOCs.The power reduction techniques
applied in this dissertation can be applicable to all the low power VLSI circuits where
power optimization is highly essential to compromise the device scaling. Though the
testing process is carried out for 45nm technology, but the concept and steps followed
here would pave a path for future research works and upcoming technology.

62

CURRICULUM VITAE

Vil-Bhimpur
Post-Chattamundali
Ganjam,Odisha.
Pin-761043
Email-laxmana.maharana331@gmail.com
Phone-9089508085, 7085662995
LAXMANA MAHARANA
CARRIER OBJECTIVE:
To become a successful professional in a leading corporate and to work in an innovative and Competitive
world.

PROFESSIONAL EXPERIENCE:

Organization:
Nokia Siemens Networks Pvt. Ltd, Pune
Designation:
GNSC Coordinator (Network Planning and Optimization).
Work Experience: 2 year 7 Months (from May, 2010 to DEC 2013)
Organization
Designation
Client
Project
Working Place
Duration

:
:
:
:
:
:

Nokia Siemens Networks Pvt. Ltd

GNSC Coordinator
Nokia Siemens Networks Pvt. Ltd
UNINOR and AIRTEL
PUNE
DEC 2010 to JUNE 2012

Organization
Designation
Client
Project
Working Place
Duration

:
:
:
:
:
:

Nokia Siemens Networks Pvt. Ltd

Graduate Engineer Trainee
Nokia Siemens Networks Pvt. Ltd
UNINOR
PUNE
May 2010 to DEC 2010

Organization
Designation
Client
Project
Working Place
Duration

:
:
:
:
:
:

Manpower India Pvt. Ltd

4G MIS Coordinator
Ericsson India Pvt. Ltd
4G project Reliance
PUNE
JUNE 2013 to DEC 2013

WORK PROFILE:

Supporting the Global Network Support Center (GNSC) as well as circle team (BSS, NPO ,NSS) for
implementation of different Change Requests at BTS,BSC and MSC Level.
Verification of different Change Request Forms(CRFs) especially the Outage related CRFs and get it
approved by Team Lead-Manager-Circle Head Customer) in hierarchy.(Verification :: Checking of
Network Parameters).
Daily CRF Monitoring (BSS, NPO, NSS) and Checking the pre -post impact on the Site or Network.
Daily KPI Trend preparation, checking KPI thresholds and sharing with concern optimizers for
improvement of worst cases.
Daily sharing top 10 worst cells with circle team and work on it for KPI improvement.
New sites planning and creation support.(Different issue resolve from site planning to site On-air).
BSC dump compilation and parameter audit (Frequency, MO-MS, SYN, GENA, EGENA, FRL, FRU,
EDAP etc.).
Supporting planning team for Capacity planning, SD-Dimensioning etc.
Different Non-Outage Parameter Checking at local end. (By log in with different BSCs at local OMCR).
Almost i was related with all circle teams (Project,BSS,NPO,NSS) for any Major or Minor activity.
Knowledge & Skills:
Operating Systems: Windows XP/7/8.1/10,LINUX(Red hat 6.1)
Programs :C,C++,MATLAB
Trainings : CCNA(not certified),VLSI
Tools:

Cadence (Virtuoso)
Xilinx ISE
MapInfo Professional 8.5 & 10
Google Earth.
ATOLL.

Educational Qualification:
M.Tech in VLSI & Nano Technology (2014-2016) from NIT Agartala with present CGPA 8.69 up to 3rd
semester.
B.Tech in Electronics & Telecommunication Engineering(2005-2009)from National Institute of Science and
Technology, Berhampur, Odisha with CGPA8.1.
Passed +2 from Khallikote junior College, Berhampur with 74%.
Passed class 10th from Odisha board with 88%.
M.tech Project:
Low power Analog, Digital and Mixed signal testing with some power reduction techniques using Genetic
Algorithm in cadence tool in NIT Agartala Supervised by Dr. Sambhu Nath Pradhan.
This is both a frontend and a backend testing process using: Cadence tool 45nm technology.
C-programming based on Genetic algorithm.
Optimize the power during testing

Telecom Training:
Telecom Training at ALTTC (BSNL) Ghaziabad by NSN .
Course covered:
GSM Basics.
2G.
GPRS/EDGE
3G
Special Traits:
Adjustable to any environment, willingness to learn and work in team.
Personal Information:
Date of Birth
Fathers Name
Mothers Name
Language Proficiency
Nationality
Hobbies

05th Mar 1987

Mr. Sudam Maharana
Mrs. Indumati Maharana
English, Hindi,Odia
Indian
Listening songs, Swimming, playing Comp. games

Declaration:
I hereby declare that all the details given above are true to the best of my knowledge and belief.
Place: Agartala
Date:

Laxmana Maharana