SECOND ORDER EFFECTS

IN
MOSFETS

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Contents
Channel Length Modulation / Velocity Saturation
Threshold Voltage
Vt Variation:

SCE / RSCE
NCE / RNCE
Body bias
Leakage current mechanisms in MOSFETs
PN junction reverse bias leakage
Subthreshold leakage
Gate oxide tunneling
Injection of hot carrier
Drain Induced barrier Lowering(DIBL)
Gate induced drain leakage(GIDL)
Punchthrough

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Channel Length Modulation

Actual Length of channel decreases with increase in V
. DS
Result in non zero I D /V DS

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Channel Length Modulation

The resultant expression for I D is

I D =K

W
V GSV T 2 1 V DS [1]
L

Where, we have

L
L
Thus the modulation parameter has higher value for short channels.
=

Effect of channel length modulation can be observed as in the simple current

mirror

VDD
ID2

ID1

M2 VDS2
M1

VGS

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I D2 12 V GS
=
I D1 12 V DS2
R OUT =

1
I D2
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Velocity Saturation
At higher V DS velocity of charge carrier saturates.
The results in linear dependence of the drain current on V GS V T
The value of transconductance(g m) becomes constant
Thus the Value of VDSAT< VGS- VT

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Threshold Voltage
Threshold Voltage:

The value of gate to source voltage required to cause surface inversion for
channel formation is called threshold voltage.

Components of Threshold Voltage:

The work function difference b/w gate and channel (MS)

The component of gate voltage to change the surface potential (2F)
Gate voltage component to offset the depletion region charge (Q B).
The voltage component to offset the fixed charges in the gate oxide and in
silicon oxide (Qox)
Q B Q OX
V th= MS 2 F

C OX C OX
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Threshold Voltage

VG=0

Vt>VG>0(Depletion)

VG>Vt(Strong Inversion)
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Vt variation in an MOS
There are various trends seen in threshold voltage variation with scaling of MOS

transistors.
Various secondary effects leading to Vt variation in MOSFETs can be:
Body Bias
Short Channel effect(SCE)
DIBL
Reverse short channel effect(RSCE)
Narrow channel effect(NCE)
Reverse narrow channel effect(RNCE)
VDD

M2
M1

ID2

ID1

VDS

I D2 V GS V T1
=
I D1 V GS V T2 2

VGS

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Body bias
Body bias or back gate effect is the name given to the change in threshold

voltage with change in the voltage Vsb.

For a NMOS we have.

Where,
VTN is the threshold voltage with substrate bias.
VTO is threshold voltage with substrate bias zero.
is the body effect parameter.
2 is the surface potential parameter.

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Short channel effect (SCE)

It is phenomenon in scaled transistors whereby threshold voltage of a device

reduces with decrease in L.

This dependence of Vt on length of the device is because of the protrusion of
source and drain regions.
Part of the channel is already depleted because of source and drain junction
depletion.

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Drain Induced Barrier Lowering

DIBL is the phenomena which results in reduced threshold voltage and hence

higher subthreshold current.

The reduction in threshold is due to the band bending caused by Drain to

source voltage.

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Reverse short channel effect

To reduce short channel effects, depletion region widths need to be reduced.
For this channels are highly doped near the source and drain terminals (halo

doping).
In short channels halo doping of source and drain overlaps.
Threshold voltage is high as channel doping is higher.

Fig:Halo doped channel

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Narrow channel effect

Narrow channel effect is phenomenon by virtue of which, Vt increases as

channel width is reduced.

NCE is more prominent in LOCOS.
In LOCOS gate MOSFET, existence of fringing field causes the gate induced
depletion region to spread, thus higher Vt.

Fig:Channel spreading in LOCOS process MOSFET

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Reverse Narrow channel effect

Prominent in Shallow trench isolation(STI) MOSFETS.
Depletion layer cannot spread under the isolation oxide.
So, no increase in Vt.
2-D field induced edge fringing effect at the gate edge makes formation of

inversion layer at the edges becomes easier.

Vt thus reduces

Fig:STI MOSFET
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Leakage mechanisms
Leakage Currents result in higher power consumption
Various Leakage current mechanisms in MOSFETs are:

PN junction reverse bias leakage

Subthreshold leakage
Gate oxide tunneling
Injection of hot carrier
Gate induced drain leakage(GIDL)
Punchthrough

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PN junction reverse bias leakage

Drain and source diffusion regions form a reversed biased diode with substrate.
Reverse biased current has two component:

Minority carrier diffusion near the edge of the depletion region.

Electron-hole pair generation in the depletion region.
If both P and N side are heavily doped the BTBT tunneling dominates the pn
junction leakage.

Fig:PN junction reverse bias leakage

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Fig: BTBT tunneling

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Subthreshold Leakage
Subthreshold or weak inversion conduction current is a mechanism of current

leakage in subthreshold gate bias region.

In weak inversion region minority carrier concentration is not zero.
Subthreshold leakage current varies exponentially with Vgs.
The subthreshold current is due to diffusion.

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Gate Oxide Tunneling

With scaling oxide thickness is also reduced.
The high electric field coupled with low oxide thickness results in tunneling of

electrons from substrate to gate.

There may be two types of tunneling possible:
FowlerNordheim (FN) tunneling
Direct tunneling.

Fig: FN tunneling
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Fig:Direct Tunneling
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Injection of Hot Carriers

In short channel transistors electric field is very high.
Electrons or holes can gain sufficient energy from the electric field to cross the

interface potential barrier and enter into the oxide layer

The injection from Si to SiO is more likely for electrons than holes.

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Gate Induced Drain Leakage

Seen when gate is biased for accumulation in the substrate.
Due to accumulation, depletion layer at the surface to be much narrower than

elsewhere.
When the negative gate bias is large, the n+ drain region under the gate can be
depleted or even inverted
This causes more crowding and hence effects like avalanche multiplication and
BTBT.
Thinner Gate,Higher VDD, Moderately doped Drain has more GIDL.

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Punchthrough
In Short channel devices the source and drain depletion regions extend into the

channel.
Increase in reverse bias also pushes the depletion regions closer.
Punchthrough occurs when both the depletion regions touch each other.
Even if the channel is heavily doped, punchthrough may occur below it.
Due to punchthrough subthreshold current increases

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Leakage reduction techniques

Fig:Aspects of well engineering for leakage reduction

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Leakage reduction techniques

Constant Field Scaling

Reduce voltages and dimensions by same factor K(>1) .

Constant field assures higher reliability.
Retrograde Well
Channels have nonuniform vertical doping profile.
Lower surface concentration,for higher surface mobility.
Highly doped subsurface to avoid punchthrough.
Halo doping:
Non Uniform channel doping in lateral direction.
Substrate is highly doped at source and drain junctions.
Reduces depletion width in the drain-substrate and source-substrate regions.
Reduces DIBL,Punchthrough
Enhances BTBT and GIDL.

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Leakage reduction techniques

Constant Field Scaling

Drain extended by adding a drift region with similar doping between drain
and the intended channel.
Traps the majority of the lateral electric field,limiting the hot carrier effect to
this region,instead of the channel.
This improves the V DS breakdown voltage.
Increases the channel resistance.

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References
[1] Sung-Mo Kang, Yusuf Leblebici, Cmos Digital
Circuits.Reading,Tata Mcgraw Hills, 2003, ch. 3, pp. 107109.

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Integrated

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Thank You

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BACKUP SLIDES

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EB diagram VG = 0
Assumptions:

P-type Substrate.
M=Si (Work function of metal & Semiconductor are Same)
No Trapped Charges in Oxide.

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EB diagram VG<0
Accumulation:

EF goes up in the metal .

An electric field is observed in the oxide

Concentration of holes increases at the surface.

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Eb diagram VG>0
Depletion:

EF of the metal goes down

Because of positive voltage at gate, equivalent negative charge is observed at

oxide-semiconductor interface.
Negative charge is due to the depletion of holes.

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EB diagram VG>>0
Inversion,Strong Inversion:

EF of the metal goes further down

Number of electrons at surface exceeds the number of holes at

surface(Inversion)
Concentration of electrons at surface equals concentration of holes in
substrate(Strong inversion)
Condition for strong inversion S=2F.Semiconductor is n-type at the surface

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Beyond strong inversion

When we further increase voltage at the gate:

Electrons at surface move into conduction band.

Results in the formation of a conducting channel

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Threshold Voltage expression

QB
V th=2 F
C OX
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EB for MS0 and QOX0

When we further increase voltage at the gate:

Surface may get inverted with VG=0

To achieve Flat band condition equivalent voltage is to be applied at gate

This is known as the Flat band voltage

V th= MS 2 F

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Q B Q OX

C OX C OX

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DRAIN eXTENDED MOS

(DEMOS)

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ESD APPLICATION PROBLEMS

At lower technologies say in 180nm (gate oxide

thickness ~ 7nm) the voltage requirement is still the
same as in higher technologies.
Clamping is not allowed to power supply so as to
prevent the fail-safe problem.

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(DENMOS)

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THE SOLUTION (DEMOS)

A drain is created within a well of same type dopant

but the density is far less.

The increase in the drain-substrate junction area and
the reduced number of dopants of drain allow
increment in the junction breakdown voltage.
This permits high voltage operations on the mos and
prevents the drain from voltage excursions in absence
of a clamp.

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THE SOLUTION Contd.

A great advantage with DEMOS is that they allow

fabrication of very thin gate oxide.

As there is a less doped well surrounding the actual
drain hence the actual seen voltage at the drain
decreases and so does the electric field.
This reduces the creation of hot carriers which
affects the gate oxide thickness.
Hence mos with lesser Vth can be easily fabricated.

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PROBLEMS with the SOLUTION

DEMOS is inherently susceptible to ESD protection.
Practically for an L of 640nm and W of 50u the

avalanche breakdown of drain substrate happens at

Vds ~13 V .
But the actual breakdown happens over 17 V.

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