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Data Sheet No.
PD60240 revA
IRS20124S(PbF)
DIGITAL AUDIO DRIVER WITH DISCRETE DEAD-TIME AND PROTECTION
Features
Product Summary
200V high voltage ratings deliver up to 1000W
output power in Class D audio amplifier

applications
Integrated dead-time generation and bi-directional
over current sensing simplify design
Programmable compensated preset dead-time for
improved THD performances over temperature
High noise immunity
Shutdown function protects devices from overload
conditions
Operates up to 1MHz
3.3V/5V logic compatible input
VSUPPLY
200V max.
IO+/-
1A / 1.2A typ.
Selectable Dead Time

15/25/35/45ns typ.
Prop Delay Time
70ns typ.
Bi-directional Over
Current Sensing
Package
14-Lead SOIC
Typical Application Diagram

<20V
<200V
IN
<20V
OC
SD
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IN
NC
OCSET1
NC
DT/SD
VB
OCSET2
HO
OC
VS
COM
NC
LO
VCC
IRS 20124
IRS20124S(PbF)
Description
The IRS20124S is a high voltage, high speed power MOSFET driver with internal dead-time and shutdown
functions specially designed for Class D audio amplifier applications.
The internal dead time generation block provides accurate gate switch timing and enables tight dead-time
settings for better THD performances.
In order to maximize other audio performance characteristics, all switching times are designed for immunity
from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic
inputs are compatible with LSTTL output or standard CMOS down to 3.0V without speed degradation. The
output drivers feature high current buffers capable of sourcing 1.0A and sinking 1.2A. Internal delays are
optimized to achieve minimal dead-time variations. Proprietary HVIC and latch immune CMOS technologies
guarantee operation down to Vs= 4V, providing outstanding capabilities of latch and surge immunities with
rugged monolithic construction.
Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB
Vs
High side floating supply voltage

High side floating supply voltage
-0.3
VB-20
220
VB+0.3
V
V
VHO
VCC
VLO
VIN
High side floating output voltage

Low side fixed supply voltage
Low side output voltage
Input voltage
Vs-0.3
-0.3
-0.3
-0.3
VB+0.3
20
Vcc+0.3
Vcc+0.3
V
V
V
V
VOC
OC pin input voltage

OCSET1 pin input voltage
Allowable Vs voltage slew rate
-0.3
-0.3
-0.3
-
Vcc+0.3
Vcc+0.3
Vcc+0.3
50
V
V
V
V/ns
Maximum power dissipation

Thermal resistance, Junction to ambient
Junction Temperature
Storage Temperature
-55
1.25
100
150
150
W
C/W
C
C
300
VOCSET1
VOCSET2
dVs/dt
Pd
RthJA
TJ
TS
TL
Lead temperature (Soldering, 10 seconds)
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IRS20124S(PbF)
Recommended Operating Conditions

For Proper operation, the device should be used within the recommended conditions. The Vs and COM
offset ratings are tested with all supplies biased at 15V differential.
Symbol
Definition
Min.
Max.
Units
Vs+10
Note 1
Vs
10
Vs+18
200
VB
18
V
V
V
V
VB
VS
VHO
VCC
High side floating supply absolute voltage

High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
VLO
VIN
VOC
VOCSET1
Low side output voltage

Logic input voltage
OC pin input voltage
0
0
0
0
VCC
VCC
VCC
VCC
V
V
V
V
VOCSET2
TA

Ambient Temperature
0
-40
VCC
125
V
C
Note 1: Logic operational for VS equal to -8V to 200V. Logic state held for VS equal to -8V to -VBS.
Dynamic Electrical Characteristics

VBIAS (VCC, VBS) = 15V, CL = 1nF and TA = 25C unless otherwise specified. Figure 2 shows the timing definitions.
Symbol
Definition
Min. Typ.
Max. Units Test Conditions
ton
High & low side turn-on propagation delay
60
80
VS=0V
toff
tr
tf
tsd
High & low side turn-off propagation delay

Turn-on rise time
Turn-off fall time
Shutdown propagation delay
60
25
15
140
80
40
35
200
VS=200V
toc
Propagation delay time from Vs>Vsoc+ to OC
280
OCSET1=3.22V
OCSET2=1.20V
OC pulse width
OC input filter time
100
200
15
40
VDT>VDT1
25
50
VDT1>VDT> VDT2
10
35
60
VDT2>VDT> VDT3
15
45
70
VDT3>VDT> VDT4
twoc min
toc filt
DT1
Deadtime: LO turn-off to HO turn-on (DTLO-HO)

& HO turn-off to LO turn-on (DTHO-LO)
DT2
DT3
DT4

& HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4
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nsec
IRS20124S(PbF)
Static Electrical Characteristics

VBIAS (VCC , VBS) = 15V and TA = 25C unless otherwise specified.
Symbol
Min.
Typ.
Max. Units Test Conditions
Logic high input voltage
2.5
Vcc=10~20V
VIL
VOH
VOL
UVCC+
Logic low input voltage

High level output voltage, VBIAS VO
Low level output voltage, VO
Vcc supply UVLO positive threshold
8.3
9.0
1.2
1.2
0.1
9.7
Io=0A
Io=0A
UVCCUVBS+
UVBSIQBS
Vcc supply UVLO negative threshold

High side well UVLO positive threshold
High side well UVLO negative threshold
High side quiescent current
7.5
8.3
7.5
8.2
9.0
8.2
8.9
9.7
8.9
1
IQCC
ILK
IIN+
IIN-
Low side quiescent current

High to Low side leakage current
Logic 1 input bias current
Logic 0 input bias current
3
0
4
50
10
1.0
Io+
IoVDT1
VDT2
Output high short circuit current (Source)
1.0
Output low short circuit current (Sink)
1.2
DT mode select threshold 1

0.8xVcc 0.89xVcc 0.97xVcc
VIH
Definition
VDT3
VDT4
VSOC+

Positive OC threshold in Vs
VSOC-
Negative OC threshold in Vs

0.75
1.0
1.25
-1.25
-1.0
-0.75
mA
VDT =Vcc
VB=VS =200V
VIN =3.3V
VIN =0V
Vo=0V, PW<10S
Vo=15V, PW<10S
OCSET1=3.22V
OCSET2=1.20
OCSET1=3.22V
OCSET2=1.20V
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IRS20124S(PbF)
Lead Definitions
Symbol Description
VCC
VB
HO
Low side logic Supply voltage

High side floating supply
High side output
VS
IN
DT/SD
COM
High side floating supply return

Logic input for high and low side gate driver outputs (HO and LO), in phase with HO
Input for programmable dead-time, referenced to COM. Shutdown LO and HO when tied to COM
Low side supply return
LO
OC
OC SET1
OC SET2
Low side output

Over current output (negative logic)
Input for setting negative over current threshold
Input for setting positive over current threshold
IN
NC 14
OCSET1 NC 13
DT/SD
VB 12
OCSET2
HO 11
OC
VS 10
COM
NC
LO
VCC
IR20124S 14 Lead SOIC (narrow body)
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IRS20124S(PbF)
Block Diagram
VB
UV
DETECT
UV
Q
LEVEL
SHIFTER
IN
DEAD
TIME
S
R
HO
SD
VS
CURRENT
SENSING
DT/SD
Vcc
UV
DETECT
LO
DELAY
OCSET2
OCSET1
OC
COM
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IRS20124S(PbF)
50%
IN
50%
ton(L)
toff(L)
toff(H)
ton(H)
90%
HO
10%
DTLO-HO
DTHO-LO
90%
LO
10%
Figure 1. Switching Time Waveform Definitions
DT/SD
VSD
HO
LO
90%
TSD
Figure 2. Shutdown Waveform Definitions
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IRS20124S(PbF)
LO
COM
VS
toc filt
VS
VSoc+
COM
VSoc-
Vsoct
COM
OC
HIGH
OC
tdoc
COM
twoc
Figure 4. OC Waveform Definitions
Figure 3. OC Input FilterTime Definitions
IN
NC
OCSET1 NC
DT/SD
10k
VB
OCSET2 HO
__
OC
VS
15V
COM
Vsoc+
Vsoc-
LO
NC
VCC
15V
OC
Vsoc+
VS
COM
Vsoc-
OC
Figure 5. OC Waveform Definitions
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IRS20124S(PbF)
200
Turn-on Delay Time (ns)
Turn-on Delay Time (ns)
200
160
120
80
40
0
160
120
80
40
0
-50
-25
25
50
75
100
125
10
12
Temperature ( C)
120
120
Turn-Off Time (ns)
150
Turn-Off Time (ns)
18
20
18
20
Figure 6B. Turn-On Tim e

vs. Supply Voltage
150
Max.
60
Typ.
30
0
-50
16
V BIAS Supply Voltage (V)
Figure 6A. Turn-On Tim e

vs. Tem perature
90
14
Max.
90
60
Typ.
30
0
-25
25
50
75
Temperature (oC)
Figure 7A. Turn-Off Time
vs. Temperature
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100
125
10
12
14
16

Figure 7B. Turn-Off Time
vs. Supply Voltage
IRS20124S(PbF)
60
Turn-On Rise Time (ns)
Turn-On Rise Time (ns)
60
50
40
30
20
10
-50
50
40
30
20
10
-25
25
50
75
100
125
10
Temperature ( oC)
16
18
20
Figure 8B. Turn-On Rise Tim e

vs. Supply Voltage
50
50
Turn-Off Fall Time (ns)
Turn-Off Fall Time (ns)
14
Fiure 8A. Turn-On Rise Tim e

vs.Tem perature
40
30
20
10
0
40
30
20
10
0
-50
-25
25
50
75
100
Temperature ( C)
Figure 9A. Turn-Off Fall Tim e
vs. Tem perature
10
12
125
10
12
14
16
18
20

Figure 9B. Turn-Off Fall Tim e
vs. Supply Voltage
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Input Voltage (V)
Input Voltage (V)
IRS20124S(PbF)
3
Min.
3
2
Min.
1
-50
-25
25
50
75
100
10
125
12
Input Voltage (V)
Input Voltage (V)
2
Max.
1
25
50
75
100
Temperatre ( C)
Figure 11A. Logic "0" Input Voltage
vs. Temperature
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18
20
Figure 10B. Logic "1" Input Voltage

vs. Supply Voltage
Figure 10A. Logic "1" Input Voltage

vs. Tem perature
-25
16
V CC Supply Voltage (V)
Temperature (oC)
0
-50
14
125
2
Max.
1
0
10
12
14
16
18
20

Figure 11B. Logic "0" Input Voltage
vs. Supply Voltage
11
High Level Output Voltage (V)
High Level Output Voltage (V)
IRS20124S(PbF)
3
2
Max.
1
0
-1
-50
-25
25
50
75
100
4
3
2
Max.
1
0
10
125
12
18
20
Figure 12B. High Level Output

vs. Supply Voltage
Figure 12A. High Level Output

vs. Temperature
0.25
0.25
Low Level Output Voltage (V)
Low Level Output Voltage (V)
16
Temperature (oC)
0.20
0.15
Max.
0.10
0.05
0.00
-50
-25
25
50
75
100
Temperature ( C)
Figure 13A. Low Level Output
vs.Temperature
12
14
125
0.20
0.15
Max.
0.10
0.05
0.00
10
12
14
16
18
20
VCC Supply Voltage (V)

Figure 13B. Low Level Output
vs. Supply Voltage
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300
250
200
150
100
50
Max.
0
-50
-25
25
50
75
100
125
Offset Supply Leakage Current (A)
Offset Supply Leakage Current (A)
IRS20124S(PbF)
110
90
70
Max.
50
30
Typ.
10
-10
50
80
Temperature ( oC)
140
170
200
V B Boost Voltage (V)

Figure 14B. Offset Supply Leakage
Current vs. Supply Voltage
Figure 14A. Offset Supply Leakage

Current vs. Temperature V B=200v
3
)
2.5
2.0
V BS Supply Current (
110
1.5
1.0
0.5
2
2
1
1
0
0.0
-50
-25
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25
50
75
100
125
10
12
14
16
18
Temperature (oC)
V BS Supply Voltage (V)
Figure 15A. V BS Supply Current

vs. Tem perature
Figure 15B. V BS Supply Current

vs. Supply Voltage
20
13
IRS20124S(PbF)
10
V cc Supply Current ()
V cc Supply Current (A)
10
8
6
4
Max.
2
0
-50
8
6
Max.
4
2
0
-25
25
50
75
100
10
125
12
18
20
Figure 16B. V CC Supply Current

vs. Supply Voltage
Figure 16A. V CC Supply Current

vs. Temperature
30
)
30
24
Logic "1" Input Current (
16
Temperature (oC)
Logic "1" Input Current (
14
18
12
6
0
-50
-25
25
50
75
100
Temperature (oC)
Figure 17A. Logic "1" Input Current
vs. Tem perature
14
125
24
18
12
6
0
10
12
14
16
18
20

Figure 17B. Logic "1" Input Current
vs. Supply Voltage
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5
Logic "0" Input Current ()
Logic "0" Input Current ()
IRS20124S(PbF)
4
3
2
Max.
1
0
-50
-25
25
50
75
100
4
3
2
Max.
1
0
125
10
12
Temperature (oC)
16
18
20
Figure 18A. Logic "0" Input Current

vs. Temperature
Figure 18B. Logic "0" Input Current

vs. Supply Voltage
11
10
11
14
10
Max.
9
Typ.
Min.
7
6
-50
-25
25
50
75
100
Temperature (oC)
Figure 19. V CC Undervoltage Threshold (+)
vs. Temperature
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125
Max.
Typ.
Min.
7
6
-50
-25
25
50
75
100
125
Temperature ( oC)
Figure 20. V CC Undervoltage Threshold (-)
vs. Temperature
15
IRS20124S(PbF)
11
)
11
10
9
8
7
10
9
8
7
6
6
-50
-25
25
50
75
100
-50
125
-25
100
125
Figure 22. V BS Undervoltage Threshold (-)

vs. Tem perature
1.5
Output Sink Current ()
1.5
Output Source Current ()
75
Temperature ( C)
Figure 21. V BS Undervoltage Threshold (+)

vs. Tem perature
1.3
1.1
0.9
Typ.
0.5
1.3
1.1
0.9
Typ.
0.7
0.5
10
12
14
16
18

Figure 23. Output Source Current
vs. Supply Voltage
16
50
o
Temperature (oC)
0.7
25
20
10
12
14
16
18
20
VBIAS Supply Voltage (V)

Figure 24. Output Sink Current
vs. Supply Voltage
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-5
16
Typ.
-7
Max.
15
VDT 1(V)
VS Offset Supply Voltage (V)
IRS20124S(PbF)
-9
-11
-13
14
Typ.
13
Min.
12
-15
10
12
14
16
18
11
-50
20
-25
125
8
7
Max.
VDT 3(V)
VDT 2(V)
100
Figure 26. DT mode select Threshold (1)

vs. Temperature
11
75
Temperature ( C)
Figure 25. Maximum VS Negative Offset

vs. Supply Voltage
50
o
V BS Floting Supply Voltage (V)
10
25
Typ.
Min.
6
-50
-25
25
50
75
100
125
Temperature ( C)
vs. Temperature
Max.
Typ.
5
4
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Min.
3
-50
-25
25
50
75
100
125
Temperature ( C)
vs. Temperature
17
4.5
60
4.0
52
DTLO-HO (nsec)
VDT 4(V)
IRS20124S(PbF)
3.5
3.0
2.5
2.0
-50
-25
25
50
75
100
44
36
Typ.
28
20
-50
125
-25
2.0
-0.3
1.6
-0.6
Max.
1.2
Typ.
Min.
0.4
0.0
-25
25
50
75
100
125
Temperature ( oC)
Figure 31. Positive OC Threshold(+) in VS
vs. Tem perature
18
75
100
125
Figure 30. DT LO turn-off to HO turn-on (3)

vs. Tem perature
Negative OC TH(V)
Positive OC TH(V)
Figure 29. DT m ode select Threshold (4)

vs. Tem perature
-50
50
Temperature ( C)
Temperature ( C)
0.8
25
Max.
-0.9
Typ.
-1.2
Min.
-1.5
-1.8
-50
-25
25
50
75
100
125
Temperature ( C)
Figure 32. Negative OC Threshold(-) in VS
vs. Temperature
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65
65
55
55
45
140V
70V
0V
35
25
Temperature (oC)
Temperature (oC)
IRS20124S(PbF)
140v
70v
0v
45
35
25
15
15
1
10
100
1000
100
Figure 333.
4 . IRS20124s vs. Frequency (IRFBC30)
Rgate=22 , V CC=12V
Figure 32.
33. IRS20124s vs. Frequency (IRFBC20)
Rgate=33 , VCC=12V
65
75
140V
140V
70V
0V
45
35
25
Temperature (oC)
65
55
1000
Frequency (KHZ)
Frequency (KHZ)
Temperature (oC)
10
70V
0V
55
45
35
25
15
15
1
10
100
1000
Frequency (KHZ)
5. IRS20124s vs. Frequency (IRFBC40)
Figure 334.
Rgate=15 , V CC=12V
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10
100
1000
Frequency (KHZ)
6. IRS20124s vs. Frequency (IRFPE50)
Figure 335.
Rgate=10 , V CC=12V
19
IRS20124S(PbF)
Functional description
90%
Effective dead-time
Programmable Dead-time
The IRS20124 has an internal dead-time generation
block to reduce the number of external components
in the output stage of a Class D audio amplifier.
Selectable dead-time through the DT/SD pin voltage is an easy and reliable function, which requires only two external resistors. The dead-time
generation block is also designed to provide a
constant dead-time interval, independent of Vcc
fluctuations. Since the timings are critical to the
audio performance of a Class D audio amplifier,
the unique internal dead-time generation block is
designed to be immune to noise on the DT/SD
pin and the Vcc pin. Noise-free programmable
dead-time function is available by selecting deadtime from four preset values, which are optimized
and compensated.
How to Determine Optimal Dead-time
Please note that the effective dead-time in an actual
application differs from the dead-time specified in
this datasheet due to finite fall time, tf. The deadtime value in this datasheet is defined as the time
period from the starting point of turn-off on one
side of the switching stage to the starting point of
turn-on on the other side as shown in Fig.5. The
fall time of MOSFET gate voltage must be subtracted from the dead-time value in the datasheet
to determine the effective dead time of a Class D
audio amplifier.
(Effective dead-time)
= (Dead-time in datasheet) (fall time, tf)
20
HO (or LO)
10%
tf
LO (or HO)
Deadtime
10%
Figure 6. Effective Dead-time
A longer dead time period is required for a MOSFET

with a larger gate charge value because of the
longer tf. A shorter effective dead-time setting is
always beneficial to achieve better linearity in the
Class D switching stage. However, the likelihood
of shoot-through current increases with narrower
dead-time settings in mass production. Negative
values of effective dead-time may cause excessive
heat dissipation in the MOSFETs, potentially
leading to their serious damage. To calculate the
optimal dead-time in a given application, the fall
time tf for both output voltages, HO and LO, in the
actual circuit needs to be measured. In addition,
the effective dead-time can also vary with
temperature and device parameter variations.
Therefore, a minimum effective dead-time of 10nS
is recommended to avoid shoot-through current
over the range of operating temperatures and
supply voltages.
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IRS20124S(PbF)
DT/SD pin
DT/SD pin provides two functions: 1) setting deadtime and 2) shutdown. The IRS20124 determines
its operation mode based on the voltage applied
to the DT/SD pin. An internal comparator
translates which mode is being used by comparing
internal reference voltages. Threshold voltages for
each mode are set internally by a resistive voltage
divider off Vcc, negating the need of using a precise
absolute voltage to set the mode.
The relationship between the operation mode and
the voltage at DT/SD pin is illustrated in the Fig.7.
Operational Mode
15nS
25nS
Dead-time
35nS
Deadtime
mode
DT1
DT2
DT3
DT4
R1
R2
DT/SD
voltage
<10k
3.3k
5.6k
8.2k
Open
8.2k
4.7k
3.3k
1.0 x Vcc
0.71 x Vcc
0.46 x Vcc
0.29 x Vcc
Table 1. Suggested resistor values for dead-time

settings
Shutdown
Since IRS20124 has internal dead-time generation, independent inputs for HO and LO are no
longer provided. Shutdown mode is the only way
to turn off both MOSFETs simultaneously to protect them from over current conditions. If the DT/
SD pin detects an input voltage below the threshold, VDT4, the IRS20124 will output 0V at both HO
and LO outputs, forcing the switching output node
to go into a high impedance state.
45nS
Shutdown
0.23xVcc
0.36xVcc
0.57xVcc
0.89xVcc Vcc
VDT
Figure 7. Dead-time Settings vs VDT Voltage
Design Example
Table 1 shows suggested values of resistance for
setting the deadIRS20124
time. Resistors with
>0.5mA
Vcc
up to 5% tolerance
can be used if these
R1
listed values are folDT/SD
lowed.
R2
COM
Figure 8. External Resistor
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Over Current Sensing

In order to protect the power MOSFET, IRS20124
has a feature to detect over current conditions,
which can occur when speaker wires are shorted
together. The over current shutdown feature can
be configured by combining the current sensing
function with the shutdown mode via the DT/SD pin.
Load Current Direction in Class D Audio
Application
In a Class D audio amplifier, the direction of the
load current alternates according to the audio input signal. An over current condition can therefore
happen during either a positive current cycle or a
negative current cycle. Fig.9 shows the rela21
IRS20124S(PbF)
tionship between output current direction and

the current in the low side MOSFET. It should be
noted that each MOSFET carries a part of the
load current in an audio cycle. Bi-directional current sensing offers over current detection capabilities in both cases by monitoring only the low
side MOSFET.
Load Current
IRS20124 measures the current during the period

when the low side MOSFET is turned on. Fig.10
illustrates how an excessive voltage at Vs node
detects an over current condition. Under normal
operating conditions, Vs voltage for the low side
switch is well within the trip threshold boundaries,
VSOC- and VSOC+. In the case of Fig.9(b) which demonstrates the amplifier sourcing too much current
to the load, the Vs node is found below the trip
level, VSOC-. In Fig.9(c) with opposite current direction, the amplifier sinks too much current from the
load, positioning Vs well above trip level, VSOC+.
Once the voltage in Vs exceeds the preset threshold, the OC pin pulls down to COM to detect an
over current condition.
Figure 9. Direction in MMOSFET Current and Load

Current
Bi-directional Current Sensing

IRS20124 has an over current detection function
utilizing RDS(ON) of the low side switch as a current
sensing shunt resistor. Due to the proprietary HVIC
process, the IRS20124 is able to sense negative
as well as positive current flow, enabling bi-directional load current sensing without the need for
any additional external passive components.
Since the switching waveform usually contains

over/under shoot and associated oscillatory artifacts on their transient edges, a 200ns blanking
interval is inserted in the Vs voltage sensing block
at the instant the low side switch is engaged.
Because of this blanking interval, the OC function
will be unable to detect over current conditions if
the low side ON duration less than 200ns.
LO
Vs
+
OC SET1
OR
OCSET2
AND
OC
+
-
vs
~
~
~
~
~
~
~
~
~ ~
~
~
~
~ ~
~
~
~
~
~
~
~
Vsoc+
COM
Vsoc-
(a ) Normal Operation
Condition
(b ) Over- Current in
Positive Load Current
(c ) Over- Current in
Negative Load Current
Figure 10. Vs Waveform in Over-current Condition
22
Figure 11. Simplified Functional Block Diagram of

Bi-Directional Current Sensing
As shown in Fig.11, bi-directional current sensing block has an internal 2.0V level shifter feeding
the signal to the comparator. OCSET1 sets the positive side threshold, and is given a trip level at VSOC+,
which is OCSET1 - 2.0V. In same way, for a given
OCSET2, VSOC- is set at OCSET2 2.0V
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IRS20124S(PbF)
>0.5mA
Vcc
R3
OCSET1
R4
OCSET2
R5
COM
Figure 12. External Resistor Network to set OC

Threshold
How to set OC Threshold

The positive and negative trip thresholds for bidirectional current sensing are set by the voltages
at OCSET1 and OCSET2. Fig.14 shows a typical resistor voltage divider that can. be used to set
OCSET1 and OCSET2.
The trip threshold voltages, VSOC+ and VSOC+, are
determined by the required trip current levels, ITRIP+
and ITRIP-, and RDS(ON) in the low side MOSFET.
Since the sensed voltage of Vs is shifted up by
2.21V internally and compared with the voltages
fed to the OCSET1 and OCSET2 pins, the required
value of OCSET1 with respect to COM is
VOCSET1 = VSOC+ + 2.21 = ITRIP+ x RDS(ON) + 2.21
The same relation holds between OCSET2 and VSOC-,
VOCSET2 = VSOC- + 2.21 = ITRIP- x RDS(ON) + 2.21
In general, RDS(ON) has a positive temperature coefficient that needs to be considered when the
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threshold level is being set. Please also note that,

in the negative load current direction, the sensing
voltage at the Vs node is limited by the body diode of the low side MOSFET as explained later.
Design Example
This example demonstrates how to use the external? resistor network to set ITRIP+ and ITRIP- to
be 11A, using a MOSFET that has RDS(ON)
=60m.
VISET1 = VTH+ + 2.21 = ITRIP+ x RDS(ON) + 2.21= 11
x 60m +2.21 = 2.87V
VISET2 = VTH- + 2.21 = ITRIP- x RDS(ON) + 2.21= (-11)
x 60m +2.21 = 1.55V
The total resistance of resistor network is based
on the voltage at the Vcc and required bias current in this resistor network.
Rtotal =R3 + R4 + R5 = Vcc / Ibias
= 12V / 1mA = 12K
The expected voltage across R3 is Vcc- VISET1
= 12-2.87=9.13V. Similarly, the voltages across
R4 is VSOC+ - VSOC- = 2.87-1.55=1.32V, and the
voltage across R5 is VISET2= 1.55V respectively.
R3 =9.13V/ Ibias = 9.13K
R4 =1.32V/ Ibias = 1.32K
R5 =1.55V/ Ibias = 1.55K
Choose R3= 9.09K, R4=1.33K, R5=1.54K
from E-96 series.
Consequently, actual threshold levels are
VSOC+ =2.88V gives ITRIP+ = 11.2A
VSOC- =1.55V gives ITRIP- = -11.0A
Resisters with 1% tolerances are recommended.
23
IRS20124S(PbF)
Voltage in Vs
OC Output Signal
The OC pin is a 20V open drain output. The OC
pin is pulled down to ground when an over current
condition is detected. A single external pull-up
resistor can be shared by multiple IRS20124 OC
pins to form the ORing logic. In order for a microprocessor to read the OC signal, this information
is buffered with a mono stable multi vibrator to
ensure 100ns minimum pulse width.
Because of unpredictable logic status of the OC
pin, the OC signal should be ignored during power
up/down.
Limitation from Body Diode in MOSFET
When a Class D stage outputs a positive current,
flowing from the Class D amp to the load, the body
diode of the MOSFET will turn on when the Drain
to Source voltage of the MOSFET become larger
than the diode forward drop voltage. In such a
case, the sensing voltage at the Vs pin of the
IRS20124 is clamped by the body diode. This
means that the effective Rds(on) is now much
lower than expected from Rds(on) of the MOSFET,
and the Vs node my not able to reach the threshold to turn the OC output on before the MOSFET
fails. Therefore, the region where body diode
clamping takes a place should be avoided when
setting VSOC-.
Body Diode Clamp
Load
Current
Vsoc- should be
set in this region
Figure 13. Body Diode in MOSFET Clamps vs

Voltage
For further application information for gate driver

IC please refer to AN-978 and DT98-2a. For further application information for class D application, please refer to AN-1070 and AN-1071.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 322 3331
Data and specifications subject to change without notice.
9/21/2005
24
www.irf.com
This datasheet has been downloaded from:

www.DatasheetCatalog.com
Datasheets for electronic components.

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Data Sheet No.

200V high voltage ratings deliver up to 1000W

output power in Class D audio amplifier

Selectable Dead Time

Typical Application Diagram

Absolute Maximum Ratings

High side floating supply voltage

High side floating output voltage

OC pin input voltage

Maximum power dissipation

Lead temperature (Soldering, 10 seconds)

Recommended Operating Conditions

High side floating supply absolute voltage

Low side output voltage

OCSET2 pin input voltage

Dynamic Electrical Characteristics

Max. Units Test Conditions

High & low side turn-on propagation delay

High & low side turn-off propagation delay

Propagation delay time from Vs>Vsoc+ to OC

Deadtime: LO turn-off to HO turn-on (DTLO-HO)

Deadtime: LO turn-off to HO turn-on (DTLO-HO)

Static Electrical Characteristics

Max. Units Test Conditions

Logic high input voltage

Logic low input voltage

Vcc supply UVLO negative threshold

Low side quiescent current

Output high short circuit current (Source)

Output low short circuit current (Sink)

DT mode select threshold 1

DT mode select threshold 3

0.32xVcc 0.36xVcc 0.40xVcc

Low side logic Supply voltage

High side floating supply return

Low side output

IR20124S 14 Lead SOIC (narrow body)

Figure 1. Switching Time Waveform Definitions

Figure 3. OC Input FilterTime Definitions

Figure 5. OC Waveform Definitions

Turn-on Delay Time (ns)

Turn-Off Time (ns)

Turn-Off Time (ns)

Figure 6B. Turn-On Tim e

V BIAS Supply Voltage (V)

Figure 6A. Turn-On Tim e

V BIAS Supply Voltage (V)

Turn-On Rise Time (ns)

Figure 8B. Turn-On Rise Tim e

Turn-Off Fall Time (ns)

V BIAS Supply Voltage (V)

Fiure 8A. Turn-On Rise Tim e

V BIAS Supply Voltage (V)

Input Voltage (V)

Input Voltage (V)

Input Voltage (V)

Input Voltage (V)

Figure 10B. Logic "1" Input Voltage

Figure 10A. Logic "1" Input Voltage

V CC Supply Voltage (V)

V CC Supply Voltage (V)

High Level Output Voltage (V)

High Level Output Voltage (V)