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Machine Code
Machine Code
Machine Instructions
Instructions: Computations
The arithmetic and logical operations,
normally carried out by the ALU
(Arithmetic Logic Unit)
What might this include?
add
subtract
increment
invert bits
and more
Instructions: Others
Data transfer
Computations
Flow control
11
10
12
7 Accumulator
Double accumulator D
15
Index register IX
IX
15
Index register IY
IY
15
Stack pointer
SP
15
Program counter
PC
S X H I N Z V C
A:B
mnemonic:
op-code:
operation:
increasing
addresses
13
increasing
addresses
86
dd
LDAA
86 (hex)
Load accumulator A with the
8-bit value immediately
following the op-code
15
96
dd
LDAA
96 (hex)
Load accumulator A with the
contents of memory location
given by 8-bit number
following the op-code
14
16
Endian-ness
17
19
Memory Addressing
Memory consists of addressable locations. A memory
location has 2 components:
address
contents
memory
data bus lines
20
$D000
ADDA
$D001
STAA
$D000
21
Assembler
..
B6
D0
00
BB
D0
01
B7
D0
00
..
LDAA
ADDA $D001
STAA
$D000
23
instruction code
operand
instruction code
..
B6
D0
00
BB
D0
01
B7
D0
00
..
LDAA
$D000
ADDA $D001
instruction code
$D000
operand
operand
22
STAA
$D000
24
LDAA $D000
CPU
IDR
..
$B6
$D0
$00
$BB
$D0
$01
$B7
$D0
$00
..
$19
$37
..
27
25
..
[$C000]
[$C001]
[$C002]
[$C003]
[$C004]
[$C005]
[$C006]
[$C007]
[$C008]
CPU
IDR
[$D000]
[$D001]
MAR
$D0
$00
$BB
$D0
$01
$B7
$D0
$00
..
$19
$37
..
[$C000]
[$C001]
[$C002]
[$C003]
[$C004]
[$C005]
[$C006]
[$C007]
[$C008]
[$D000]
[$D001]
28
CPU
IDR
MAR ACCA
$19 is returned on D-bus and put
into register A (Accumulator A)
..
$B6
$D0
$00
$BB
$D0
$01
$B7
$D0
$00
..
$19
$37
..
[$C000]
[$C001]
[$C002]
[$C003]
[$C004]
[$C005]
[$C006]
[$C007]
[$C008]
[$D000]
[$D001]
29
MAR
30
31
32
Addressing Modes
One instruction, multiple meanings
33
35
Immediate
Addressing Modes
34
36
68HC11 Immediate
68HC11 Direct
LDAA 23
LDAA $FF
37
39
Extended
The address of the argument (16 bit)
follows the op-code
That is, the number which follows the opcode is treated as an address at memory
locations [$0000 - $FFFF], and the CPU
will look there for the actual argument.
Using this addressing mode, memory space
of HC11 can be fully accessed.
38
40
68HC11 Relative
68HC11 Extended
No #, so we know
its not immediate
>255, so it cant be direct,
and must therefore be
extended
BRA $F8
BNE $21
41
Relative
43
Indexed
42
44
Inherent
68HC11 Indexed
45
68HC11 Inherent
68HC11 Indexed
It loads the byte at address [X+offset]to Accu A
LDAA
47
3,X
A0
Offset
(unsigned 8 bit)
0 .. 255
CLRA
INX
Index Register
to be used
X or Y
46
XX+1
48
register
The argument is the current contents of a specific register
register-indirect
The address of the argument is the current value of a
specified register
register-autoincrement/decrement
As register-indirect, but adjust register to point to
next/previous location before or after using its value
Indirect
The number following the op-code is the address of a
memory location that contains the address of the
argument
Week 2: Addressing Modes
49
imm
86 dd
Assemblycode syntax
LDAA #dd
dir
96 dd
LDAA dd
ext
A6 dd dd
Machine codes
ind, X B6 dd
ind, Y 18 B6 dd
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
51
How can we
LDAA dddd
Differentiate
Addressing Modes?
LDAA dd, X
LDAA
dd, Y
Are These
Numbers
Selects Register
A for 0 or B for 1
Chosen Randomly?
Week 2: Addressing Modes
1
1
1
1
1
1
1
1
86
96
A6
B6
C6
D6
E6
F6
50
00
01
10
11
immediate
Direct
Extended
Indexed
52
Conditionals
Bits in Condition Code Register
Other Instructions
55
53
5 status bits.
Certain bits in CCR indicate the situation after
the operation. For instance, if previous
operation yields a zero output, Z flag becomes
one.
54
56
Bit Name
S
X
H
I
N
Z
V
C
Function
Stop disable flag
XIRQ interrupt mask
Half carry from lower 4 bit
Interrupt mask
Negative
Zero
Overflow
Carry
Carry/Borrow (C)
Overflow (V)
Zero (Z)
Negative (N)
Half Carry (H)
59
Example 1
Status Bits
57
#53
#67
MSB
LSB
53
67
120
C
The result fits into
8 bits, therefore no
carry.
Week 2: Addressing Modes
58
60
Example 2
Add 130 and 163, and determine if carry bit is set or not.
LDAA
LDAB
ABA
#130
#163
MSB
130
163
293
LSB
C
The result is 9 bits,
we use C flag as the
9th bit.
Week 2: Addressing Modes
61
LSB
50274
1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0
28712
0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0
78986
63
#50274
#28712
MSB
1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0
C
The result is 17 bits
(exceeds 65535), we use
C flag as the 17th bit.
Week 2: Addressing Modes
62
64
2s Complement Ranges
+3 = 00000011
+26 = 00011010
+40 = 00101000
+102= 01100110
Complement
and add 1
-3 = 11111101
-26 = 11100110
-40 = 11011000
-102= 10011010
16-bit reg.
C flag set to 1 if
Carry out from MSB for addition
Borrow from MSB for subtraction
#56
#-53
MSB
65
LSB
56
-53
C
The result is 8 bits, we don't
use C flag as the 9th bit since
the numbers are taken as
signed
66
68
For subtraction, a
fictitous 9th bit is
assumed.
#56
#-53
MSB
56
-53
3
LSB
1
C
complement
For subtraction 9th
bit is the
complement of carry
The resultant C is 0
Week 2: Addressing Modes
Add 105 and 45, and determine if overflow bit is set or not.
LDAA
ADDA
#33
#-40
MSB
-40
Desired
Value
LSB
33
-7
#105
#45
MSB
+45
-106
how it is
interpreted!
70
LSB
105
150
71
69
Result is
Negative!!
Week 2: Addressing Modes
Add -120 and -10, and determine if overflow bit is set or not.
LDAA
ADDA
#-120
#-10
MSB
LSB
-120
-10
-130
Range Limit
V Flag
Outside
Inside
1
0
73
Negative Flag
#80
#45
MSB
80
45
125
LSB
75
74
76
N Flag
Value
Value of MSB
Value of N-flag
77
79
#50
#-50
MSB
LSB
50
+ -50
80
#50
#-47
MSB
LSB
50
+ -47
81
Picture
Z Flag
1
0
increasing
addresses
Results of operation
Status of
Z Flag
83
82
$C100
$C101
$C102
..
$C105
84
Coding
Design
Clear accumulator A.
A Self contained
instruction.
CLRA
ADDA
ADDA
ADDA
ADDA
ADDA
STAA
A A + [$C100]
$C100
$C101
$C102
$C103
$C104
$C105
A A + [$C101]
A A + [$C102]
A A + [$C103]
A A + [$C104]
[$C105] A
opcodes
Week 2: Addressing Modes
accumulator
ans + [$C100]
ans + [$C101]
ans + [$C102]
ans + [$C103]
ans + [$C104]
ans to $C105
85
87
Implementation
clear
ans =
ans =
ans =
ans =
ans =
store
operands
...
Clear accumulator
(running sum)
CLRA
ADDA
ADDA
ADDA
ADDA
ADDA
STAA
$C100
$C101
$C102
$C103
$C104
$C105
$4F
$BB
$BB
$BB
$BB
$BB
$B7
$C1
$C1
$C1
$C1
$C1
$C1
$00
$01
$02
$03
$04
$05
opcodes operands
Week 2: Addressing Modes
86
$C000
$4F
$C001
$BB
$C002
$C1
$C003
$00
$C004
$BB
$C005
$C1
...
88
Improvement - 1
CLRA
ADDA
ADDA
ADDA
ADDA
ADDA
STAA
LDAA $C100
$C100
$C101
$C102
$C103
$C104
$C105
START
Saves 1 byte,
which may be quite
important for
systems with
limited memory
Clear Accumulator
#$C100
0,X
START
91
CLRA
LDX
ADDA
INX
JMP
#$C100
0,X
Therefore, we need a
comparison
operation and a
conditional branch
We have to use an
Index Register
(Indexed Addressing)
90
We need to
compare X with
$C105
START
Yes, we can!
X $C100
89
Can we iterate
through
the memory
locations?
$C100
$C101
$C102
$C103
$C104
$C105
CLRA
LDX
ADDA
INX
JMP
We need to jump
conditionally to
START to deal
with the infinite
loop
Improvement - 2
LDAA
ADDA
ADDA
ADDA
ADDA
STAA
Improvement :
Using Loops
If X = $C105 then
we continue,
otherwise we jump
to label START
92
CLRA
LDX
#$C100
START ADDA 0,X
INX
CPX
#$C105
............
S X H I N Z V C
Comparison
We need a
branch
instruction that
checks CCR
Compare X
immediately with
value $C105
Jump 8 bytes
backward
PC PC -8
Comparison is a
non-destructive
subtraction
It sets the
appropriate bit in
Condition Code
Register (CCR)
S X H I N Z V C
LDAA
$C100
LDX
#$C101
START ADDA
$F8 = -8
in 2s
complement
form
You must start
counting from the
next instruction
backward or
forward
0,X
INX
CPX
#$C105
BNE
START
STAA
0,X
93
Comparison
CLRA
LDX
#$C100
START ADDA 0,X
INX
CPX
#$C105
BNE
START
...........
$B6
$C1
$00
$CE
$C1
$01
$AB
$00
$08
$8C
$C1
$05
$26
$F8
$A7
$00
95
Example
Checks Z bit in
CCR. If it is 0
jumps to START
If Z bit is 1, then
continues (i.e. exits
loop)
MEMORY
OUTPUT
$D000
$D0
$D001
$D002
$00
$D0
$D003
$02
$D004
$D0
$D005
$04
....
....
$D0FD
$FC
$D0FE
$D0
$D0FF
$FE
96
Example
First Version
We use index register X to point out the beginning
of the memory block. We store the value of X
to the location pointed by X and increment X twice
to move on.
LOOP
....
LDX
STX
INX
INX
CPX
BNE
....
#$D000
$0,X
X Starting address
$33
$D002
$55
$D0FF
$23
$D200
$73
$D201
$33
$D202
$55
$D2FF
$23
XX+1
XX+1
#$D100
LOOP
97
$73
$D001
[X + 0] X
LDAB
LDX
STX
ABX
CPX
BNE
....
$D000
#$02
#$D000
$0,X
B2
X Starting address
[X + 0] X
XX+B
#$D100
LOOP
LOOP
99
98
LDX
LDY
LDAA
STAA
INX
INY
CPX
BNE
....
#$D000
#$D200
$0,X
$0,Y
X source address
Y destination address
A [X + 0]
[Y + 0] A
XX+1
YY+1
#$D100
LOOP
100