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  • Slic Procesor

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    gpuonline
    17 vizualizări4 pagini
    This document describes a sliced processor entity with the following: - It takes in two 8-bit inputs (x, y), a clock, start signal, and control signals. - It contains registers to store input bits and intermediate values. - It has three processes - one to control loading/operations, one to perform operations on the lower bits, and one for the upper bits. - The operations include logic, arithmetic, shifts, and multiplication on the input values. - The results and product are outputted after the operations complete.

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    slic_procesor

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    This document describes a sliced processor entity with the following: - It takes in two 8-bit inputs (x, y), a clock, start signal, and control signals. - It contains registers to store input bits and intermediate values. - It has three processes - one to control loading/operations, one to perform operations on the lower bits, and one for the upper bits. - The operations include logic, arithmetic, shifts, and multiplication on the input values. - The results and product are outputted after the operations complete.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOC, PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    17 vizualizări4 pagini

    Slic Procesor

    Încărcat de

    gpuonline
    This document describes a sliced processor entity with the following: - It takes in two 8-bit inputs (x, y), a clock, start signal, and control signals. - It contains registers to store input bits and intermediate values. - It has three processes - one to control loading/operations, one to perform operations on the lower bits, and one for the upper bits. - The operations include logic, arithmetic, shifts, and multiplication on the input values. - The results and product are outputted after the operations complete.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOC, PDF, TXT sau citiți online pe Scribd
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    din 4

    PROGRAM: (SLICED PROCESSOR)

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity s1 is
    port(x,y:in std_logic_vector(7 downto 0);
    clk: in std_logic;
    start:in bit;
    result:out std_logic_vector(7 downto 0);
    mulout: out std_logic_vector(15 downto 0);
    operation,functionload:in std_logic_vector(3 downto 0));
    end s1 ;

    architecture Behavioral of s1 is
    signal carry1,carry2,borrow1,borrow2: std_logic;
    signal accum1,accum2: std_logic_vector(3 downto 0);
    signal Breg1,Breg2:std_logic_vector(3 downto 0);
    signal m1,m2,i1,i2: std_logic_vector(7 downto 0);
    signal opt: std_logic_vector(15 downto 0);
    signal sum1,sum2:std_logic_vector(4 downto 0):="00000";
    signal control1,control2:std_logic_vector(3 downto 0);
    signal exe1,exe2,add,sub,b:bit :='0';
    signal zout1:std_logic_vector(3 downto 0):="0000";
    signal zout2:std_logic_vector(3 downto 0):="0000";
    begin

    p1:process(x,y,operation,functionload,start,clk)
    begin
    if(clk='1' and clk'event) then
    if(start='1') then
    exe1<='0';
    if (operation="0000") then
    control1<=functionload;
    control2<=functionload;
    elsif(operation="0001") then
    accum1<=x(3 downto 0 );
    Breg1<=y(3 downto 0);
    accum2<=x(7 downto 4);
    Breg2<=y(7 downto 4);
    elsif(operation="0010") then
    exe1<='1';
    exe2<='1';
    elsif(operation="0011") then
    result<=zout2 & zout1;
    mulout<= opt;
    end if;
    end if;
    end if;
    end process p1;

    p2:process(accum1,Breg1,exe1,control1,clk)
    begin
    if(clk='1' and clk'event) then
    if(exe1='1') then
    if(control1="0000") then
    zout1<=accum1 or Breg1;
    elsif(control1="0001") then
    zout1<=accum1 and Breg1;
    elsif(control1="0010") then
    zout1<=accum1 nor Breg1;
    elsif(control1="0011") then
    zout1<=accum1 nand Breg1;
    elsif(control1="0100") then
    zout1<=accum1 xor Breg1;
    elsif(control1="0101") then
    zout1<=not accum1 ;
    elsif(control1="0110") then
    zout1<=not Breg1;
    elsif(control1="0111") then -- shift right acc
    zout1<=accum2(0) & accum1(3 downto 1);
    elsif(control1="1000") then
    zout1<=Breg2(0) & Breg1(3 downto 1); -- shift right breg1
    elsif(control1="1001") then -- shift left acc
    zout1<=accum1(2 downto 0) & '0';
    elsif(control1="1010") then -- shift left breg
    zout1<=Breg1(2 downto 0) & '0';
    elsif(control1="1011") then
    zout1<=accum1(2 downto 0) & accum2(3) ;-- rotate left accum
    elsif(control1="1100") then
    zout1<=Breg2(0) & Breg1(3 downto 1); --rotate right breg
    elsif(control1="1101") then
    sum1<=('0' & accum1) + ('0' & Breg1);
    zout1<=sum1(3 downto 0);
    carry1<=sum1(4);
    add <='1';
    elsif(control1="1110") then
    if(accum1>=Breg1) then
    zout1<=accum1 - Breg1;
    borrow1<='0';
    sub <='1';
    elsif(accum1<Breg1) then
    zout1<=accum1 - Breg1;
    borrow1<='1';
    sub <='1';
    end if;
    elsif(control1 = "1111") then
    m1<=accum1*Breg1;
    end if;
    end if;
    end if;
    end process p2;

    p3:process(accum2,Breg2,exe2,control2,borrow1,carry1,add,sub,clk)
    variable k1,k2:std_logic_vector(15 downto 0);
    begin
    if(clk='1' and clk'event) then
    if(exe2='1') then
    if(control2="0000") then
    zout2<=accum2 or Breg2;
    elsif(control2="0001") then
    zout2<=accum2 and Breg2;
    elsif(control2="0010") then
    zout2<=accum2 nor Breg2;
    elsif(control2="0011") then
    zout2<=accum2 nand Breg2;
    elsif(control2="0100") then
    zout2<=accum2 xor Breg2;
    elsif(control2="0101") then
    zout2<=not accum2 ;
    elsif(control2="0110") then
    zout2<=not Breg2;
    elsif(control2="0111") then
    zout2<='0' & accum2(3 downto 1);
    elsif(control2="1000") then
    zout2<='0' & Breg2(3 downto 1);
    elsif(control2="1001") then
    zout2<=accum2(2 downto 0) & accum1(3);
    elsif(control2="1010") then
    zout2<=Breg2(2 downto 0) & Breg1(3);
    elsif(control2="1011") then
    zout2<=accum2(2 downto 0) & accum1(3) ;
    elsif(control2="1100") then
    zout2<=Breg1(0) & Breg2(3 downto 1);
    elsif(control2="1101" and add='1') then
    sum2<=('0' & accum2) + ('0' & Breg2)+ carry1;
    zout2<=sum2(3 downto 0);
    carry2<=sum2(4);
    elsif(control2="1110") then
    if(accum2>=Breg2 and sub ='1') then
    zout2<=accum2 - Breg2- borrow1;
    borrow2<='0';
    elsif(accum2<Breg2 and sub ='1') then
    zout2<=Breg2 - accum2 - borrow1;
    borrow2<='1';
    end if;
    elsif(control2 = "1111") then
    m2 <=accum2 * Breg2;
    i1<=accum1 * Breg2;
    i2<=accum2 * Breg1;
    k1:="0000"&i1(7 downto 0)&"0000";
    k2:="0000"&i2(7 downto 0)&"0000";
    opt<=(m2 & m1)+ k1+k2;
    end if;
    end if;
    end if;
    end process p3;
    end Behavioral;

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