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PROGRAMMATION VHDL.
ADDITIONNEUR-SOUSTRACTEUR
32-bits
OPTIMISATION ESPACE-TEMPS
Ai Bi
Additionneur
C i+1 Complet Ci
(1-bit)
Si
Block Diagramme
...
Le Programme: c31
A31 1-bit
AC S31
B31
c32=carry_out
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Add_Complet IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END Add_Complet;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Add_Soust_32CP is
Port (
CLK : in std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Add_Soust : in std_logic;
C_R : out std_logic_vector(31 downto 0);
Cout_R : out std_logic);
end Add_Soust_32CP;
COMPONENT Add_Complet
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END COMPONENT Add_Complet;
SIGNAL Co_I :
STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL A_R, B_R, C : STD_LOGIC_VECTOR(31
DOWNTO 0);
SIGNAL Cin_R, Cout : STD_LOGIC;
SIGNAL Bt : STD_LOGIC;
BEGIN
begin
else Bt <= not B;
if (CLK'event and CLK='1') then
End process
A_R <= A;B_R <= Bt;Cin_R <= Cin;
end if; Synthèse Æ Mux2_1 ou XOR
end process IN_REGS;
Logique_Comb_CADDER: block
Begin
c0 : Add_Complet
PORT MAP (a => A_R(0), b => B_R(0), c_in => Add_Soust, sum => C(0),
c_out => Co_I(0));
Add_Soust = C0
B3 B2 B1 B0
A3 A2 A1 A0
C4 S3 S2 S1 S0
c8=carry_in
c32=carry_out
pi(i=8Æ11)
result(i) = pi + ci ET
P2
A11
B11 gi (i=8Æ11) G2
C3 C3 =G2+
gi =Ai.Bi pi= Ai+Bi
A12 P2.C2
B12 P0 = p3.p2.p1.p0
pi(i=12Æ15) P3 result 12-15 G0 = g3+ p3.g2 + p3.p2.p1.g0
gi (i=12Æ15) G3 = pi + ci P1 = p7.p6.p5.p4
A15 C4 =G3+ (i=12Æ15)
G1 = g7+ p7.g6 + p7.p6.p5.g4 … etc.
B15 P3.C3
Ci+1 = Gi.+Pi.Ci
C4
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 18
C4
A16
B16
cin Unité
Look
result 16-19 2eme Étage
Ahead =pi + ci
pi(i=16Æ19) (i=16Æ19)
P4
A19 gi (i=16Æ19)
B19 G4
C5 •Entrees A16-A31, B16-B31
C5 =G4+
A20 P4.C4 result 20-23
B20
•calculer P4-P7, G4-G7 pour chaque
pi(i=20Æ23) P5 groupe
A23 gi (i=20Æ23) G5
B23
C6 C6 =G5+ •Deduire C5-C7 et COUT
P5.C5
A24 result 24-27
B24 •Pour chaque ADD 4-bit calculer ses
results (Æ result 16-31)
pi(i=24Æ27) P7
A27
gi (i=24Æ27) G7
B27
C7
MAIS Les 2 Étages sont
C7 =G6+
A28 P6.C6 Connectés à la
B28 Propagation de Retenue
pi(i=28Æ31) P8 result 28-31
G8 = pi + ci
Avec le C4 qui joue le rôle
gi (i=28Æ31)
A31 C8 =G7+ (i=28Æ31) De c0 du 1er étage.
B31 P7.C7
C8 = COUT
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 19
Retenue Rapide en utilisant le 2eme niveau d’abstraction
P0 = p3.p2.p1.p0
P1 = p7.p6.p5.p4
P2 = p11.p10.p9.p8
P3 = p15.p14.p13.p12
G0 = g3+(p3.g2) + (p3.p2.g1) + (p3.p2.p1.g0)
G1 = g7+(p7.g6) + (p7.p6.g5) + (p7.p6.p5.g4)
G2 = g11+(p11.g10)+(p11.p10.g9) + (p11.p10.p9.g8)
G3 = g15+(p15.g14)+(p15.p14.g3)+(p15.p14.p13.g12)
C1 = G0+(P0•c0)
C2 = G1+(P1•C1)= G1+(P1•G0)+(P1•P0•c0)
C3 = G2+(P2•C2)= G2+(P2•G1)+(P2•P1•G0)+(P2•P1•P0•c0)
C4 = G3+(P3•C3)= G3+(P3•G2)+(P3•P2•G1)+(P3•P2•P1•G0)
+ (P3•P2•P1•P0•c0)
M C5 = G4+(P4•C4)
A C6 = G5+(P5•G4)+(P5•P4• C4)
C7 = G6+(P6•G5)+(P6•P5•G4)+(P6•P5•P4•C4)
I
COUT = G7+(P7•G6)+(P7•P6•G5)+(P7•P6•P5•G4) +
S (P7•P6•P5•P4•C4)
Le Programme:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Add4b_LA IS
PORT
(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_out : OUT STD_LOGIC
);
END Add4b_LA ;
BEGIN
Logique_Comb_LA_ADDER: block BEGIN
h_sum <= x_in XOR y_in;
carry_generate <= x_in AND y_in;
carry_propagate <= x_in OR y_in;
PROCESS (carry_generate,carry_propagate,carry_in_internal) BEGIN
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND carry_in);
inst: FOR i IN 1 TO 2 LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i));
END LOOP;
carry_out <= carry_generate(3) OR (carry_propagate(3) AND carry_in_internal(3));
END PROCESS;
sum(0) <= h_sum(0) XOR carry_in;
sum(3 DOWNTO 1) <= h_sum(3 DOWNTO 1) XOR carry_in_internal(3 DOWNTO 1);
end block Logique_Comb_LA_ADDER;
END COMPORTEMENT;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 25
Solution Hiérarchique I
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Add_Soust_32CPLA_I is
Port (
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Add_Soust : in std_logic;
C_R : out std_logic_vector(31 downto 0);
Cout_R : out std_logic);
end Add_Soust_32CPLA_I ;
COMPONENT Add4b_LA
PORT(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_out : OUT STD_LOGIC
END COMPONENT Add4b_LA ;
BEGIN
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 27
Synthèse Æ Mux2_1 ou XOR
Bt <= B when Add_Soust = ‘0’ else not B;
IN_REGS: process (CLK) begin if (CLK'event and CLK='1') then -- Enregistrer les Entrées avec des FFs
A_R <= A;B_R <= Bt;Cin_R <= Cin end if;
end process IN_REGS;
Logique_Comb_CPLA_ADDER_I: block
Begin
-- On pouvait le faire comme avant avec: Loop_c1to6 : FOR i IN 1 TO 6 GENERATE pour C1 a C6
c0 : Add4b_LA PORT MAP (x_in => A_R(3 downto 0), y_in => B_R(3 downto 0),
carry_in => Add_Soust, sum => C(3 downto 0), carry_out => c4));
c1 : Add4b_LA PORT MAP (x_in => A_R(7 downto 4), y_in => B_R(7 downto 4),
carry_in => c4, sum => C(7 downto 4), carry_out => c8));
c2 : Add4b_LA PORT MAP (x_in => A_R(11 downto 8), y_in => B_R(11 downto 8),
carry_in => c8, sum => C(11 downto 8), carry_out => c12));
c3 : Add4b_LA PORT MAP (x_in => A_R(15 downto 12), y_in => B_R(15 downto 12),
carry_in => c12, sum => C(15 downto 12), carry_out => c16));
c4 : Add4b_LA PORT MAP (x_in => A_R(19 downto 16), y_in => B_R(19 downto 16),
carry_in => c16, sum => C(19 downto 16), carry_out => c20));
c5 : Add4b_LA PORT MAP (x_in => A_R(23 downto 20), y_in => B_R(23 downto 20),
carry_in => c20, sum => C(23 downto 20), carry_out => c24));
c6 : Add4b_LA PORT MAP (x_in => A_R(27 downto 24), y_in => B_R(27 downto 24),
carry_in => c24, sum => C(27 downto 24), carry_out => c28));
c7 : Add4b_LA PORT MAP (x_in => A_R(31 downto 28), y_in => B_R(31 downto 28),
carry_in => c28, sum => C(31 downto 28), carry_out => c32));
end block Logique_Comb_CPLA_ADDER_I;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 28
Enfin enregistrer les Sorties avec des FFs
------- Unite LookAhead Generateur de Retenue (Type : Mixte CP&LA Solution II) -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ULA_GenR_4 is
Port (
P0, P1, P2, P3 : in std_logic;
G0, G1, G2, G3 : in std_logic;
c0 : in std_logic;
C1, C2, C3, C4 : out std);
end ULA_GenR_4 ;
BEGIN
Logique_Comb_ULA_GenR_4: block
Begin
entity LA_GP_4 is
Port (
A, B : in std_logic_vector(3 downto 0);
Pi : out std_logic;
Gi : out std_logic);
end LA_GP_4;
architecture DF of LA_GP_4 is
Signal P, G : std_logic_vector(3 downto 0);
begin
P <= A XOR B;
G <= A XOR B;
End architecture DF
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ULA_16 is
Port (
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
C_in : in std_logic; -- Add_Soust
C_out: out std_logic_vector(3 downto 0));
end ULA_16;
COMPONENT ULA_GenR_4
PORT(
P0, P1, P2, P3 : in std_logic;
G0, G1, G2, G3 : in std_logic;
c0 : in std_logic;
C1, C2, C3, C4 : out std);
END COMPONENT ULA_GenR_4;
COMPONENT LA_GP_4
PORT(
A, B : in std_logic_vector(3 downto 0);
Pi : out std_logic;
Gi : out std_logic);
END COMPONENT LA_GP_4 ;
BEGIN
SIGNAL P0, P1, P2, P3, G0, G1, G2, G3 : std_logic;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 34
Logique_Comb_ULA_16 : block
Begin
GP_0 : LA_GP_4 PORT MAP (A => A(3 downto 0), B => B(3 downto 0),
Pi => P0, Gi =>G0);
GP_1 : LA_GP_4 PORT MAP (A => A(7 downto 4), B => B(7 downto 4),
Pi => P1, Gi =>G1);
GP_3 : LA_GP_4 PORT MAP (A => A(11 downto 8), B => B(11 downto 8),
Pi => P2, Gi =>G2);
GP_4 : LA_GP_4 PORT MAP (A => A(15 downto 12), B => B(15 downto 12),
Pi => P3, Gi =>G3);
ULA_1 : ULA_GenR_4 PORT MAP (P0 => P0, P1 => P1, P2 => P2, P3 => P3, G0 => G0, G1 =>
G1, G2 => G2, G3 => G3, c0 => C_in , C1 =>C1, C2 =>C2, C3 =>C3, C4 =>C4 );
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Add_Soust_32CPLA_II is
Port (
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Add_Soust : in std_logic;
C_R : out std_logic_vector(31 downto 0);
Cout_R : out std_logic);
end Add_Soust_32CPLA_II ;
COMPONENT ULA_16
PORT(
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
C_in : in std_logic; -- Add_Soust
C_out: out std_logic);
END COMPONENT ULA_16;
COMPONENT Add4b_LA
PORT(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_out : OUT STD_LOGIC
END COMPONENT Add4b_LA ;
BEGIN
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 37
Bt <= B when Add_Soust = ‘0’ else not B;
IN_REGS: process (CLK) begin if (CLK'event and CLK='1') then -- Enregistrer les Entrées avec des FFs
A_R <= A;B_R <= Bt;Cin_R <= Cin end if;
end process IN_REGS;
Logique_Comb_CPLA_ADDER_II: block
Begin
CMP1_ ULA_16 : ULA_16 PORT MAP (A => A_R(15 downto 0), B => B_R(15 downto 0),
C_in => Add_Soust, C_out => C1_4));
c0 : Add4b_LA PORT MAP (x_in => A_R(3 downto 0), y_in => B_R(3 downto 0),
carry_in => Add_Soust, sum => C(3 downto 0), carry_out => ‘0’);
-- pas besoin de carry_out dans ce cas puisqu’elles sont generees par la composante ULA_16
c1 : Add4b_LA PORT MAP (x_in => A_R(7 downto 4), y_in => B_R(7 downto 4),
carry_in => C1_4(0), sum => C(7 downto 4), carry_out => ‘0’);
c2 : Add4b_LA PORT MAP (x_in => A_R(11 downto 8), y_in => B_R(11 downto 8),
carry_in => C1_4(1), sum => C(11 downto 8), carry_out => ‘0’);
c3 : Add4b_LA PORT MAP (x_in => A_R(15 downto 12), y_in => B_R(15 downto 12),
carry_in => C1_4(2), sum => C(15 downto 12), carry_out => ‘0’);
CMP2_ ULA_16 : ULA_16 PORT MAP (A => A_R(31 downto 16), B => B_R(31 downto 16),
C_in => C1_4(3), C_out => C5_8));
c4 : Add4b_LA PORT MAP (x_in => A_R(19 downto 16), y_in => B_R(19 downto 16),
carry_in => C1_4(3), sum => C(19 downto 16), carry_out => ‘0’);
c5 : Add4b_LA PORT MAP (x_in => A_R(23 downto 20), y_in => B_R(23 downto 20),
carry_in => C5_8(0), sum => C(23 downto 20), carry_out => ‘0’);
c6 : Add4b_LA PORT MAP (x_in => A_R(27 downto 24), y_in => B_R(27 downto 24),
carry_in => C5_8(1), sum => C(27 downto 24), carry_out => ‘0’);
c7 : Add4b_LA PORT MAP (x_in => A_R(31 downto 28), y_in => B_R(31 downto 28),
carry_in => C5_8(2), sum => C(31 downto 28), carry_out => ‘0’);
(c) Hiver 2003, Rachid Beguenane
end block Logique_Comb_CPLA_ADDER_II;
DSA-UQAC 38
Enfin enregistrer les Sorties avec des FFs