EE303 Digital System - 2010Fall

Unit 12
Registers and Counters

2010. 11. 10.

EE KAIST
Hae-Wook Choi

EE KAIST, Hae-Wook Choi 1 Logic Design-U12-Registers & Counters

 Lecture Contents

¾ Unit 12 Registers & Counters

1. Registers and Register Transfers
2. Shift Registers
3. Design of Binary Counters
4. Counters for Other Sequences
5. Counter Design Using S-R and J-K Flip Flops
6. Derivation of Flip-Flop Input Equations-Summary

EE KAIST, Hae-Wook Choi 2 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers

9 Several D FF are grouped together with a common clock to form a register.

(commonly used to store and shift binary data)
9 Understanding of meaning and role of Load, Clk, ClrN signal
9 Problem in case of AND gating the clock Clk with load signal Load

Data in
(a) Using gated clock
4-Bit D Flip-Flop Registers

EE KAIST, Hae-Wook Choi 3 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers

(a) Using gated clock Data in

4-Bit D Flip-Flop Registers

− (Load=1, Clk ↓) D Æ Q
− (Load=0) Data out is held.
− For Gated Clk, clock delay and timing
problems may happen. Æ they can be
solved by Clock Enable signal.

EE KAIST, Hae-Wook Choi 4 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers

4-Bit D Flip-Flop
Registers with
Data, Load,
Clear, and
Clock Inputs
(fig. 12-1)

EE KAIST, Hae-Wook Choi 5 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers
9 Data Transfer Between Registers (fig. 12-2)
• Using 3-state bus, select one output between A and B registers.
@ (Load=1, En=1, Clk ↑) A Î Q, @ (Load = 1, En=0, Clk ↑) B Î Q
Q) Why 3-state bus?

EE KAIST, Hae-Wook Choi 6 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers

Logic Diagram for 8-Bit Register with Tri-State Output (fig. 12-3)

When En=0, D Æ Out

EE KAIST, Hae-Wook Choi 7 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers
Data Transfer Using a Tri-State Bus (fig. 12-4)

input enable

output enable

Values of registers A, B, C, D
are stored into G or H by E and
F which are Decoder inputs
If EF = 00 , A → G( LdG = 1 ) H ( LdH = 1 )
If EF = 01, B → G( LdG = 1 ) H ( LdH = 1 )
If EF = 10 ,C → G( LdG = 1 ) H ( LdH = 1 )
If EF = 11, D → G( LdG = 1 ) H ( LdH = 1 )

EE KAIST, Hae-Wook Choi 8 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers
N-Bit Parallel Adder with Accumulator (fig. 12-5)

Store a number (xi) in a register and add yn to it and store again the result
to the accumulator (xi)
(xi + yi) Î xi

EE KAIST, Hae-Wook Choi 9 Logic Design-U12-Registers & Counters

 12.1 Registers and Register Transfers
Adder Cell with Multiplexer (fig. 12-6)
xi + yi = si Î xi

(Data Load)
@ Ld =1 , Ad = don’t care, Clk ↑
yi Î Multiplexer Out Î xi
input data is saved at DFF

(addition)
@ Ld =0 , Ad=1, Clk ↑
yi renewed
xi + yi = si

(Data Accumulation)
@ Ld = 0, Ad = 1, Clk ↑
si Î xi
xi + yi = si for each Clk ↑

EE KAIST, Hae-Wook Choi 10 Logic Design-U12-Registers & Counters

 12.2 Shift Registers
9After storing binary data, shift data to the left or to the right at every clock

Right-Shift Register (fig. 12-

7)
@shift=1
shift right for each clock rising
@shift=0
output unchanged
Initial state: 0101
SI(serial in): 1
0101Æ1010Æ1101Æ0110Æ1011

Initially 0101

EE KAIST, Hae-Wook Choi 11 Logic Design-U12-Registers & Counters

 12.2 Shift Registers
9Construct a shift register using an S-R Latch.
9Serial-in : shift data bit by bit into the first FF (cf. parallel in/out)
9Serial-out : Data can be read from the last FF.

8-Bit Serial-in, Serial-out Shift Register (fig. 12-8)

EE KAIST, Hae-Wook Choi 12 Logic Design-U12-Registers & Counters

 12.2 Shift Registers

load to Q7 appear at Q0

width decided by
clock period

Typical Timing Diagram for Shift Register (fig. 12-9)

After Serial in, serial-out at the 8th clock (i.e., 7 clock periods)

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 12.2 Shift Registers

Parallel-in, Parallel-Out Right Shift Register (fig. 12-10)

EE KAIST, Hae-Wook Choi 14 Logic Design-U12-Registers & Counters

 12.2 Shift Registers

falling edge

Parallel-in, Parallel-Out Right Shift Register (fig. 12-10)

Input NextState Action
Load = 1 Load P/I
Sh(Shift) L(Load) Q3+ Q2+ Q1+ Q0+ Shift = 1 shift right
Usage : convert parallel data
0 0 Q3 Q2 Q1 Q0 no change to serial data
0 1 D3 D2 D1 D0 load Q) At Sh=L=0, the reason
why the present state is
1 × SI Q3 Q2 Q1 rightshift maintained?

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 12.2 Shift Registers

Sh=0, no change

initial clear assumed

Timing Diagram for Shift Register (fig. 12-11)

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 12.2 Shift Registers

Input Next State Action

Sh(Shift) L(Load) Q3+ Q+2 Q1+ Q0+
0 0 Q3 Q2 Q1 Q0 no change
0 1 D3 D2 D1 D0 load
1 × SI Q3 Q2 Q1 right shift

Q3+ = Sh ' ⋅ L' ⋅ Q3 + Sh ' ⋅ L ⋅ D3 + Sh ⋅ SI

Q2+ = Sh ' ⋅ L' ⋅ Q2 + Sh ' ⋅ L ⋅ D2 + Sh ⋅ Q3
Q1+ = Sh ' ⋅ L' ⋅ Q1 + Sh ' ⋅ L ⋅ D1 + Sh ⋅ Q2
Q0+ = Sh ' ⋅ L' ⋅ Q0 + Sh ' ⋅ L ⋅ D0 + Sh ⋅ Q1
The Next-state equations for the F/F (Table 12-1)

EE KAIST, Hae-Wook Choi 17 Logic Design-U12-Registers & Counters

 12.2 Shift Registers
Shift Register with Inverted Feedback (Figure 12-12) Æ Johnson Counter

3-bit shift register (fig. 12-12(a)) Successive states (fig. 12-

12(b))

The inverted output of the last FF is fed back into the input of the first FF.
Two loops can exist:
. 000 => 100 => 110 => 111 => 011 => 001 => 000 …
. 010 => 101 => 010 => 101

EE KAIST, Hae-Wook Choi 18 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters
9 Synchronous counter
• A counter whose FF inputs are synchronized by a common clock.
<C> changes <B> changes TA=1
@ <A>=1, <B>=1 @ <A>=1, CLK ↑ <A> changes
and CLK ↑ for each CLK ↑

Synchronous Binary Counter (fig. 12-

13)
Counting sequence
CBA: 000Æ001Æ010Æ011Æ100Æ101Æ110Æ111Æ000

EE KAIST, Hae-Wook Choi 19 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters

Present state Next state

C B A C+ B+ A+
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

EE KAIST, Hae-Wook Choi 20 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters

Present state Next state FF inputs

C B A C+ B+ A+ TC TB TA
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

State Table for Binary Counter (Table 12-

2)

EE KAIST, Hae-Wook Choi 21 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters

FF inputs
TC TB TA
0 0 1
0 1 1
0 0 1
1 1 1
0 0 1
0 1 1
0 0 1
Karnaugh Map for Binary Counter (fig. 12-14)
1 1 1

TC=AB, TB=A, TA=1

EE KAIST, Hae-Wook Choi 22 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters

State Table for Binary Counter using D-FF

Present state Next state FF inputs

C B A C+ B+ A+ DC DB DA
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

EE KAIST, Hae-Wook Choi 23 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters
Karnaugh Map for Binary Counter (fig. 12-16)
FF inputs
DC DB DA
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0 D A = A + = A'
1 1 1 ( A change state every clock cycle)

0 0 0 DB = B + = BA' + B ' A = B ⊕ A
( B change state when A = 1)
DC = C + = C ' BA + CB ' + CA' = C ' BA + C ( BA) '
= C ⊕ BA ( C change state when B = A = 1)
EE KAIST, Hae-Wook Choi 24 Logic Design-U12-Registers & Counters
 12.3 Design of Binary Counters

Binary Counter with D Flip-Flops (fig. 12-15)

EE KAIST, Hae-Wook Choi 25 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters
9 Up/Down Counter
• Up-counting or down-counting by a control signal

State Graph and Table for Up-Down counter (fig. 12-17)

CBA C + B + A+
UP DOWN
000 001 111
001 010 000
010 011 001
011 100 010
100 101 011
101 110 100
110 111 101
111 000 110
When U=1, Up counting
When D=1, Down counting
EE KAIST, Hae-Wook Choi 26 Logic Design-U12-Registers & Counters
 12.3 Design of Binary Counters
Case U=1, D=0 Equivalent to a binary Up-counter

Present Next
FF inputs
state state
C B A D D D
C B A
+ + + C B A

0 0 0 0 0 1 0 DA = A+ = A'
0 0 1 0 1 0 0 DB = B+ = BA' + B' A = B ⊕ A
0 1 0 0 1 1 0
DC = C + = C ' BA + CB' + CA' = C ' BA + C( BA)' = C ⊕ BA
0 1 1 1 0 0 1
1 0 0 1 0 1 1
1 0 1 1 1 0 1
1 1 0 1 1 1 1
1 1 1 0 0 0 0

EE KAIST, Hae-Wook Choi 27 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters
U=0, D=1 Case Equivalent to a binary down counter

Present Next FF
state state inputs
C B A D D D
C B A
+ + + C B A
DA = A+ = A ⊕ 1 = A' ( A change state every clock cycle)
0 0 0 1 1 1 1
DB = B + = B ⊕ A' ( B change state when A = 0)
0 0 1 0 0 0 0
DC = C + = C ⊕ B' A' ( C change state when B = A = 0)
0 1 0 0 0 1 0
0 1 1 0 1 0 0
1 0 0 0 1 1 0
1 0 1 1 0 0 1
1 1 0 1 0 1 1
1 1 1 1 1 0 1

EE KAIST, Hae-Wook Choi 28 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters
Case U=1, D=0
D A = A + = A'
DB = B + = BA' + B ' A = B ⊕ A
DC = C + = C ' BA + CB ' + CA' = C ' BA + C ( BA) ' = C ⊕ BA
Case U=0, D=1
DA = A+ = A ⊕ 1 = A' ( A change state every clock cycle)
DB = B + = B ⊕ A' ( B change state when A = 0)
DC = C + = C ⊕ B' A' ( C change state when B = A = 0)

DA = A+ = A ⊕ (U + D)
DB = B + = B ⊕ (UA + DA' )
DC = C + = C ⊕ (UBA + DB ' A' )

EE KAIST, Hae-Wook Choi 29 Logic Design-U12-Registers & Counters

 12.3 Design of Binary Counters

Binary Up-Down Counter (fig. 12-18)

EE KAIST, Hae-Wook Choi 30 Logic Design-U12-Registers & Counters
 12.3 Design of Binary Counters

Design of a Load possible counter ~ load of initial value by

a Ld signal

Loadable counter (fig. 12-19(a))

ClrN Ld Ct C + B + A+
Ld ~ Load, Ct ~ Count 0 × × 0 0 0
1 1 × DC DB DA (load )
1 0 0 C B A (no change)
1 0 1 present state + 1
(b)
State table (fig. 12-
19(b))
EE KAIST, Hae-Wook Choi 31 Logic Design-U12-Registers & Counters
 12.3 Design of Binary Counters

Circuit for Figure 12-19 (fig. 12-20)

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 12.4 Counters for Other Sequences
The sequence of states of a counter is not in straight binary order.

C B A C+ B+ A+
0 0 0 1 0 0
0 0 1 - - -
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 - - -
1 1 0 - - -
1 1 1 0 1 0

State Graph for Counter (fig. 12-21) State Table for fig. 21.21(Table 12-
3)

EE KAIST, Hae-Wook Choi 33 Logic Design-U12-Registers & Counters

 12.4 Counters for Other Sequences
Next-state maps for Table 12-3 and Derivation of T inputs (fig. 12-22)

Present Next
FF inputs
state state
C B A T T T
C B A
+ + + C B A

0 0 0 1 0 0 1
0 0 1 - - - 0
0 1 0 0 1 1 0
0 1 1 0 0 0 0
1 0 0 1 1 1 0
1 0 1 - - - 1
1 1 0 - - - 1
1 1 1 0 1 0 1

EE KAIST, Hae-Wook Choi 34 Logic Design-U12-Registers & Counters

 12.4 Counters for Other Sequences

TC=C’·B’+C·B TB=C’·A+C·B’ TA=C+B

Counter Using T Flip-Flops (fig. 12-23)

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 12.4 Counters for Other Sequences

Timing Diagram for Figure 12-23 (fig. 12-24)

State Graph for Counter (fig. 12-25)

EE KAIST, Hae-Wook Choi 36 Logic Design-U12-Registers & Counters
 12.4 Counters for Other Sequences
Counter Design Using D Flip-Flop
Present For D F/F, Q+ = D, so D input is
Next state FF inputs
state equal to the value of the next
state.
C
C B A B+ A+ DC DB DA
+
0 0 0 1 0 0 1
0 0 1 - - - x
0 1 0 0 1 1 0
0 1 1 0 0 0 0
1 0 0 1 1 1 1
1 0 1 - - - x
1 1 0 - - - x
1 1 1 0 1 0 0

EE KAIST, Hae-Wook Choi 37 Logic Design-U12-Registers & Counters

 12.4 Counters for Other Sequences
DC = C + = B' DB = B+ = C + BA'
DA = A+ = CA' + BA' = A' (C + B)

Counter of Figure 12-21

Using D Flip-Flops
(fig. 12-26)

EE KAIST, Hae-Wook Choi 38 Logic Design-U12-Registers & Counters

 12.5 Counter Design Using S-R and J-K Flip Flops

S R Q Q+ Q Q+ R
S RS Q Q+ S
R RS
0 0 0 0 0 0 0 0 0 0 0 ×
0 0 1 1 0 1 0 1 1 0
0 1 0 0 0 1 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 1 × 0
1 0 0 1 1 1 0 0
1 0 1 1 1 0
1 1 0 - Inputs not allowed
1 1 1 -
(a) (b) (c)
S-R Flip-Flop Inputs (Table 12-5)

EE KAIST, Hae-Wook Choi 39 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops

Present state Next state FF Inputs

C B A C+ B+ A+ SC RC SB RB SA RA
0 0 0 1 0 0
0 0 1 - - -
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 - - -
1 1 0 - - -
1 1 1 0 1 0

With columns added for the S and R flip-flop inputs (Table 12-6)

EE KAIST, Hae-Wook Choi 40 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops
Counter of Fig. 12-21 using S-R FF and state equation using K-map
Table 12-6 (fig. 12-27 (a) & (b))

EE KAIST, Hae-Wook Choi 41 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops

Design of a counter (Fig. 12-21) of using S-R Flip-Flop (fig. 12-27 (c))

EE KAIST, Hae-Wook Choi 42 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops

J-K Flip-Flop Inputs (Table 12-

7)

J K Q Q+ Q Q+ J K Q Q+ J K
0 0 0 0 0 0 0 0 0 0 0 ×
0 0 1 1 0 1
0 1 1 ×
0 1 0 0 0 1 1 0
0 1 1 0
1 0 × 1
1 1
1 0 0 1 1 0 0 1
1 1 × 0
1 0 1 1 1 1
1 1 0 1 1 1 0 0
1 1 1 0 1 0

(a) (b) (c)

EE KAIST, Hae-Wook Choi 43 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops

With columns added for the J and K flip-flop inputs (Table

12-8)
Present state state Next state
C B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 1 0 0
0 0 1 - - -
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 - - -
1 1 0 - - -
1 1 1 0 1 0

EE KAIST, Hae-Wook Choi 44 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops
Counter of Figure 12-21 Using J-K Flip-Flops (fig. 12-28)

EE KAIST, Hae-Wook Choi 45 Logic Design-U12-Registers & Counters

12.5 Counter Design Using S-R and J-K Flip Flops

Logic Circuit of Counter of Figure 12-21 Using J-K Flip-Flops (fig. 12-28(c))

EE KAIST, Hae-Wook Choi 46 Logic Design-U12-Registers & Counters

12.6 Derivation of Flip-Flop Input Equations-Summary

Figure 12-28
Counter of Figure 12-21
Using J-K Flip-Flops

EE KAIST, Hae-Wook Choi 47 Logic Design-U12-Registers & Counters

 12.6 Derivation of Flip-Flop Input Equations-Summary
Determination of Flip-Flop Input Equations from Next-State Equations
Using Karnaugh Maps (Table 12-9)

Q+ means the next state of Q

X is a don’t-care.
*Always copy X’s from the next-state map onto the input maps first.
**Fill in the remaining squares with 0’s

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12.6 Derivation of Flip-Flop Input Equations-Summary

Example (illustrating the use of Table 12-9)

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12.6 Derivation of Flip-Flop Input Equations-Summary

Figure 12-29
Derivation of Flip-Flop
Input Equations Using
4-Varable Maps

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