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Low Power VLSI PAPER- 1

1 a) Explain about the design limitations imposed on low power , low voltage circuits
pertaining to the following parameters.
(i) Power supply voltage. (ii) Threshold voltage. (iii) scaling.
(iv) interconnect wires.

b) What are the advantages and limitation of silicon on insulator technology.

2 a) Draw the cross sectional diagram of optimized Twin well BICMOS structure and
explain the process.

b) How threshold voltage is adjusted for CMOS structure in BICMOS devices.

3 Write down about LOCOS. Discuss about birds beak and crest problem, swami
process.

4 a) With the help of equation describe the level 1 and level2 modeling MOSFET

b) Describe the subthershold current model of MOSFET.

5 a) Explain limitations of MOS device characteristics.

b) Explain about Ebers moll model.

6 Draw the circuit diagram of two input CMOS NOR gate and explain its operation
with the help of truth table.

7 a) Explain about the optimizations theme and performance themes of latches.

b) What are the quality measures of latches and flip-flops? Explain.

8 a) Explain subHalfmicron d.c model formulation.

b) Draw a transmission gate band dynamic flip flop and explain its operation.
Low Power VLSI PAPER- 2

1 a) Explain how BICMOS technology is useful for low power VLSI.

b) What are the various limitations on low power and low voltage designs ? explain
them with suitable example.

2 a) Draw the diagram MOSFET structure with double diffused drawn and explain about
the same.

b) Explain punch through in short channel MOSFET.

3 a) Write about SOI wafer fabrication and advantage of SOI isolation.

b) Explain how the performance of high speed bipolar transistors is improved in


further?

4 a) With the help of equation describe the level 1 and level2 modeling MOSFET.

b) Describe the subthershold current model of MOSFET.

5 What are the experimental characteristics of sub half micron MOS devices? Explain
How to extract them

6 a) Draw the circuit of common emitter BICMOS,drive configuration & explain the
operation with ISD_VSD characteristics

b) Explain power dissipation in CMOS technology?

7 Compare the advance BIMOS NAND(two input) implementation with neat circuit
diagram?

8 Write notes on
a) Design perspectives of latches & flip-flops.

b) Lead-free pri CMOS

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