Wireless ECG Monitoring System Using PIC 16F877A and nRF905

The University of Victoria
Faculty of Engineering
CENG499A
Final Project Report
Wireless ECG/EKG Monitoring System
By Matthew Green
Dennis Leote
Kevin Harmon
Submitted to Dr. Pan Agathoklis
July 28, 2006

Table of Contents
Abstract ------------------------------------------------------------------------------ Page 1
Objective ----------------------------------------------------------------------------- Page 2
Project Design ----------------------------------------------------------------------- Page 3
Hardware ---------------------------------------------------------------------------- Page 3
The Power Supply --------------------------------------------------------- Page 4
Instrumentation Amplifier ----------------------------------------------- Page 5
Operational Amplifiers --------------------------------------------------- Page 5
Filters ------------------------------------------------------------------------ Page 6
Microcontroller ------------------------------------------------------------ Page 8
Transceivers ---------------------------------------------------------------- Page 8
MAX232 -------------------------------------------------------------------- Page 9
Software ------------------------------------------------------------------------------ Page 10
Transmitter Module ------------------------------------------------------- Page 10
Programming the PIC16F877A --------------------------------- Page 10
Analog to Digital Conversion (ADC) ---------------- Page 10
Sampling Rate -------------------------------------------- Page 11
Formatting ------------------------------------------------ Page 11
SPI --------------------------------------------------------- Page 11
RF Transmitter ---------------------------------------------------- Page 12
Receiver Module ---------------------------------------------------------- Page 12
RF Receiver ------------------------------------------------------- Page 12
PC Display ------------------------------------------------------------------ Page 13
i
Receiving the Data ------------------------------------------------ Page 14
X Plot --------------------------------------------------------------- Page 14
Y Plot --------------------------------------------------------------- Page 15
Reliability Considerations ------------------------------------------------ Page 15
Discussion and Recommendations ----------------------------------------------- Page 15
References ----------------------------------------------------------------------------Page 17
ii
List of Tables and Figures
Figure 1 – ECG/EKG Lead Placement ------------------------------------------- Page 1
Figure 2 – Ideal I-Waveform ------------------------------------------------------ Page 1
Figure 3 – Present Day ECG -------------------------------------------------------Page 2
Figure 4 – Excessive Amount of Wires in the Operating Room -------------- Page 2
Figure 5 – Block Diagram of Transmitter and Receiver ----------------------- Page 3
Figure 6 – Power Supply Circuit ------------------------------------------------- Page 4
Figure 7– An Instrumentation Amplifier ---------------------------------------- Page 5
Figure 8 – The AD620 ------------------------------------------------------------- Page 5
Figure 9 – ECG Waveform with 60 Hz not removed -------------------------- Page 6
Figure 10 – High Pass RC Filter -------------------------------------------------- Page 6
Figure 11 – Low Pass RC Filter --------------------------------------------------- Page 6
Figure 12 – 2nd Order Active Butterworth Filter -------------------------------- Page 7
Figure 13 – RS232 voltages --------------------------------------------------------Page 9
Figure 14 – Transmitter Module Block Diagram ------------------------------- Page 10
Figure 15 – Activity Diagram for Transmitter Module ------------------------ Page 12
Figure 16 – Receiver Module Block Diagram ---------------------------------- Page 12
Figure 17 – Single Lead Display (Lead I) --------------------------------------- Page 13
Figure 18 – Multiple Lead Display -----------------------------------------------Page 14
Table 1 – Voltage Requirements ------------------------------------------------- Page 4
Table 2 – Filter Values ------------------------------------------------------------- Page 7
Table 3 – Data Format -------------------------------------------------------------- Page 11
iii
iv
Abstract
In the human body, the heart is responsible for pumping oxygen carrying blood to the
entire body. To do this, it emits a small electrical charge that will cause the muscles
around the heart to contract in a sequential way such that the blood is pumped through
arteries to the intended tissues. If there are deficiencies or abnormalities, the individual
may be susceptible to serious health issues including cardiac arrest.
Care givers in hospitals world wide must be able to monitor these electrical charges and,
in doing so, be able to predict complications before they cause serious harm. To do this,
a device called an electrocardiogram (ECG/EKG) is used. An ECG involves placing
small pads in a triangular fashion on the patient’s chest, with the perimeter of the triangle
completely encompassing the heart (Figure 1). The lead placements are labelled
according to their location on the human body; Left Arm (LA), Right Arm (RA) and Left
Leg (LL). The corresponding waveforms are numbered using Roman numerals.
These pads are actually small leads connected back to a monitoring system that will
measure the potential voltage differences around the heart. Figure 2 depicts an ideal I-
Waveform taken from a healthy human body. When these results are displayed, the
doctors and nurses will be able to verify proper operation or predict possible
complications.
Figure 1 – ECG/EKG Lead Placement

Figure 2 – Ideal I-Waveform
1
Objective
As mentioned above, currently the ECG/EKG machines consist of a minimum of 3 pads

being placed on the body. These pads are wired back to a monitoring station where all of
the required data manipulation is performed before displaying the results on a monitor.
The main problem with the current method of monitoring a patient’s heart is very
awkward and restricting. The leads are constantly being dislodged from the patient by
the nurses, doctors, and even the patient themselves. This causes complications because
it appears to the monitoring station that the patient is going into cardiac arrest. (Figures 3
& 4 show a typical operating room with an excess of wires)
Figure 3 – Present Day ECG
Figure 4 – Excessive Amount of

Wires in the Operating Room
Another problem with the current system is that the mobility of the care givers is limited
due to the number of wires connecting the patient to various monitoring equipment. It is
not possible for a nurse or doctor to completely walk around the patient without having to
navigate the wires.
A solution to this would be to make the hospital utilize wireless data transmission as
much as possible to eliminate the need for wires. This process is currently being
experimented with. Currently there are various wireless applications in use in the
hospital industry. The most common are wireless pulse oxymetry, a method for
2
measuring the oxygen content in the blood. Another example is wireless temperature
sensors in which the patient swallows a small transponder that will constantly transmit
the body’s core temperature.
The objective of this project is to design a Wireless ECG Monitoring System. This
product will reliably measure the electrical activity around the heart and transmit this data
to a receiver connected to a PC. The data will then be displayed on the PC in the same
manner that the current method already does.
Project Design
This project was split into two main tasks, hardware and software. It is the responsibility
of the hardware to collect and compare the data, filter out the harmful 60 Hz signals and
transmit the data. It is the software’s responsibilities to digitize the signal, package the
data and synchronize the receiver and the transmitter.
Hardware
As mentioned above, the hardware is responsible for capturing and isolating the signal.
The hardware was divided up into stages; the power supply, instrumentation amplifiers,
operational amplifiers, filters, analog to digital converters, microcontroller, transceivers
and a MAX232. Figure 5 shows a block diagram of how the transmitter and receiver are
configured. The schematics and PCB layout are attached in Appendix A.
Figure 5 – Block Diagram of Transmitter and Receiver
3
The Power Supply
To supply power to the wireless transmitter of this project, a 12 Volt battery was chosen.
Table 1 shows a list of all various components and their minimum input voltages.
Device Vmin
Instrumentation Amplifiers ± 2.3 -18 Volts
Operational Amplifiers ± 18 Volts
Microcontroller 2.0 – 5.5 Volts
MAX232 0.3 – 6 Volts
Transceiver 3 Volts
Table 1 – Voltage Requirements
To guarantee the microcontroller received the required 5 volts, a voltage regulator was
used, which required a minimum of 7 volts.
Another issue that needed to be resolved was the DC offset. Since the typical ECG wave
will contain both positive and negative values, it was important to bias the signal such
that the ADC (analog to digital converter) would only see a level between zero and five
volts. To accomplish this, a small power supply was designed (Figure 6) using zener
diodes.
Point A is regulated by the 5.1V Zener

Diode. This level would be used as a virtual
ground reference for the instrumentation
and operational amplifier stages. The
benefit of this is that the amplifier stage
would have supply voltage of +6.9V and -
5.1V. This allowed the signal to be shifted
slightly closer to ground.
Point B, which is regulated to 3.3V,

supplies the ground reference for the
microcontroller stage. This leaves 8.7V for
the voltage regulator. It had to be slightly
below the reference voltage for the
amplifiers to compensate for the signal
when it dips below zero volts. The signal
from the amplifiers can now be tuned to
range from 0 to 5 volts at the ADC.
Figure 6 – Power Supply Circuit
4
Instrumentation Amplifier
To measure the difference in voltage between any two points on the human body, we
used an instrumentation amplifier made by Analog Devices, called an AD620 (Data
Sheets Attached in Appendix B).
An instrumentation amplifier is a
special type of differential
amplifier that will amplify the
difference between its two inputs
(Figure 7). The gain can be set by
adjusting only one resistor, Rgain.
The resulting output will be:
R
Vout = (V2 − V1 )(1 + )
R gain
Figure 7– An Instrumentation Amplifier
The AD620 is an instrumentation amplifier that

has been combined in an integrated circuit.
The benefit of this is that internal resistor
values (R) are all perfectly matched. The gain
can still be set by adjusting the one resistor
between pins 1 and 8.
Figure 8 – The AD620
Operational Amplifiers
The signal that is being analyzed on the individual’s chest has a typical maximum value
of 1mV. To make this useful, the signal would need to be amplified to approximately
5Vpp, which equates to a gain of roughly 5000. The AD620 does offer a certain amount
of gain; however it was observed that it functioned best when the gain was kept quite
low. We therefore divided up the amplification into 2 stages. The first was done using
the AD620 and the second done using a non-inverting op-amp.
We chose the gain to be 5 for the first stage and 1000 – 2000 for the next. We included a
potentiometer in the feedback loop of the op-amp to allow for some adjustment to the
gain as necessary.
5
Filters
The line interference (the 60Hz signal from the power lines) is abundant in the ECG
signal. The human body acts like a giant antenna to this frequency, and the amplitude of
the noise is roughly the same size of the ECG signal. It is therefore very difficult to
monitor the ECG wave through the noise. Figure 9 shows a typical display of an ECG
signal if the 60 Hz noise has not been removed.
Figure 9 – ECG Waveform with 60 Hz not removed
The actual signal that is measured on the human body is in the range of 1-2 mV. The
useful information is in the frequency range of 1-250 Hz, although the most important
data is below 40Hz. It is therefore desirable to filter out all of unwanted signals. To do
this some 4 stages of filtering was used. The intended result was to produce a Band Pass
Filter with the pass frequency between 1 - 40Hz.
The first stage of filtering was done prior to any amplification. It was a simple high pass
filter (HPF) that was designed using a simple RC circuit (Figure 10). This pre-filter was
designed to eliminate all of the low frequency noise. It was designed with a cut-off
frequency of 0.5 Hz.
1
f cutoff =
2πRC
Figure 11 – Low Pass RC Filter
Figure 10 – High Pass RC Filter
To eliminate the 60 Hz signal, a 4th order low pass filter (LPF) was used. This was
designed by using a 1st order RC filter in series with a 2nd order Butterworth Filter and
finally another the 1st order RC circuit. The RC circuit (Figure 11) is very similar to the
HPF defined above. In fact the cut-off frequency is calculated the same way. These were
designed to eliminate signals above 40Hz.
6
The Butterworth Filter (Figure 12) is an active filter that uses an op-amp to help get rid of
the noise. All filters will attenuate frequencies above and below the desired cut-off
frequency. The goal is to pick a filter that will be the least damaging to the desired signal
while offering maximum filtering to the unwanted signal. The benefit of the Butterworth
is that it will have a much more accurate cut-off frequency. It will therefore allow for
more of the desired signal to get through unscathed.
1
f cutoff =
2π R1 R2 C1C 2
Figure 12 – 2nd Order Active Butterworth Filter
The filter values were chosen according to the above formulas. In practice, however,
these values were only helpful in getting us close to the desired signal. The actual values
used were found by using a trial and error method. Various values were tested until the
best signal resulted. The final values of our filters were:
Filter # Filter Type Filter Order Cut-off Frequency

1 Passive RC 1 20 Hz
2 Active Butterworth 2 61.4 Hz
3 Passive RC 1 35 Hz
Table 2 – Filter Values
7
Microcontroller
The microcontroller performed all of the decision making processes. It was responsible
for the analog to digital conversion (ADC), data packaging and transceiver
synchronization. Refer to the following section on software for more information about
this.
The microcontroller used was a PIC16F877. The main reason this microcontroller was
used was because we were most familiar with it. The main features that it has that made
it quite useful are:
• Synchronous Serial Port with SPI

• In circuit programming via RS232
• 10 bit ADC
• Universal Synchronous Asynchronous Receiver Transmitter (USART)
• Low operating current < 0.6 mA
• 3 timers
• Simple (35 single word instructions to learn)
Transceivers
To transmit and receive all of the data, a single chip transceiver was chosen. The
nRF24L01 by Nordic Semiconductor was used. This was chosen because of its’ wide
range of features:
• Operates in the free to air ISM frequency band at 2.45 GHz

• Built in power amplifier
• Fully integrated frequency synthesizer
• Receiver chain with demodulator
• Crystal oscillator and modulator
• ShockBurstTM for low power operation
• Automatic CRC and preamble generation
• Automatic retransmission of data packet
• SPI interface
• Low current consumption
• Carrier detect for “listen before transmit” protocol
• Adjustable transmit power
8
MAX232
The final piece of hardware that was involved in the design of the wireless ECG machine
was the MAX232. This IC is used to convert TTL to RS232 and vice versa.
RS232 data will range from -5V to -15V for a logical high and +5V to +15V for a logical
low (Figure 13). The microcontroller will output data in the range of 0-5V (TTL). The
data must therefore be buffered before the two devices will be able to communicate with
one another.
Figure 13 – RS232 voltages
The MAX232 buffers the signal in both directions allowing the microcontroller to
communicate with the PC. The data can now be passed to the PC and displayed on the
graphic user interface (GUI)
9
Software
Once the electrical potential difference between leads has been acquired, the signal must
then be converted to the digital domain and communicated to the monitor display. The
software component of the ECG monitor includes processing the signal with the PIC
16f877A microprocessor, transmitting the signal to the display using the Nordic
nRF24L01 transceiver modules and displaying the information on a PC oscilloscope
application.
The software was written in C for the microprocessor and in Basic to write the display
application. The C compiler used was Hi-Tech C Trial version from Hi-Tech Software.
The display application was designed using Visual Basic 6.0 by Microsoft.
Transmitter Module
The transmitter module is responsible for obtaining and converting the analog ECG
signal into an 8-bit digital representation. It is also responsible for formatting and
transmitting the data. The transmitter module is within the immediate proximity of the
patient being monitored. As the system diagram presented in figure 1 shows, there are
four main steps required to transmit the ECG signal.
PIC 16f877A
ADC timing SPI

&
Form- nRF24L0
Analog atting 1
DAQ TX
Figure 14 – Transmitter Module Block Diagram
Programming the PIC 16f877A
Analog to Digital Conversion (ADC)
The amplified ECG signal is fed into the on-board ADC of the PIC. The PIC is capable of
10-bit resolution but an 8-bit digital representation provides enough accuracy and reduces
the bit-rate by half. The three analog leads each have their own ADC channel and are
sampled sequentially.
10
Sampling Rate
The sampling rate was determined by observing the highest frequency component of the
ECG signal, the QRS complex as depicted in figure 2, and using the Nyquist criteria. The
QRS complex has a possible range of frequencies between 12 Hz and 28 Hz. The Nyquist
frequency is thus taken to be 28 Hz and a sampling rate of 2 * Nyquist frequency = 56 Hz
must be observed. A sampling rate of 2 KHz was used for increased accuracy. The timing
was accomplished manually using delay routines that wait 500us between sampling.
Formatting
The data obtained from the ADC is bundled into an array of 30 bytes. This is done to
conform to the Enhanced ShockburstTM protocol employed by the nRF24L01 transceiver
module. Enhanced ShockburstTM allows for packets containing up to 30 bytes of data. To
maximize the ratio of data bits to total bits in a packet and thus increase efficiency, the
full 30 bytes allowed was utilized.
The format of used in constructing the 30-byte array is shown in Table 3 below.
A/D A/D A/D A/D A/D A/D

Chan1 Chan2 Chan2 ... Chan1 Chan2 Chan2
Sample 1 Sample 1 Sample 1 Sample 30 Sample 30 Sample 30
Table 3 – Data Format

SPI
To communicate with the nRF24L01 transceiver module, the Serial Port Interface (SPI)
module on the PIC was used. The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. The SPI was configured with the following
parameters:
• Master Mode – PIC is master with Clock as output

• Clock Polarity – Idle state for clock is a low level
• Clock rate – 1.25 MHz (fosc / 16).
• Data Sampling – Input data sampled at middle of data output time
The activity diagram shown in figure depicts the general process followed by the PIC
microprocessor.
11
A/D Wait
Conver 500 us
[array not full]

Three channel conversion
complete
Store Trans
Data [array full] mit
Figure 15 – Activity Diagram for Transmitter Module
RF Transmitter
The nRF24L01 transceivers are configured to transmit 2Mbps at a frequency of 2.45GHz,

within the ISM band. The data is encoded using Enhanced ShockburstTM (refer to
nRF24L01 datasheet for detailed description).
Receiver Module
The process of receiving the digital data from the patient is the responsibility of the
receiver module. The receiver is connected to a PC for display. As the system diagram
presented in figure 16 shows, there are four main components required to receive before
the data can be sent to the PC.
PIC 16f877A
SPI Pars U
Nf24L0 ing A PC
1 R Display
Rx T
Figure 16 – Receiver Module Block Diagram
RF Receiver
The nRF24L01 transceiver configured to perform as a receiver is much the same as the
transmitter with the same parameters. Only one data pipe is used to transfer the data. This
is in contrast to using a separate data pipe for each lead of the ECG. The reasoning
behind this is that there is less overhead involved by eliminating the need to continuously
change between data pipes.
12
The data is transferred from the transceiver to the PIC via an SPI interface. The data is
received in the format described in figure 16 and the 30 bytes of data is traversed
beginning with byte 0. As each byte is received, the data is sent to the PC through the
PIC’s on-board USART module at a baud rate of 115.2 kbps. The data is transmitted at
regular intervals of 500 us which corresponds to the sampling rate.
PC display
The ECG signal is displayed on a PC through a basic oscilloscope application. The

application was written in Visual Basic is included on the project CD as
“ECGMonitor.exe”. The application includes one control bar for rescaling the time
interval displayed.
Figure 17 – Single Lead Display (Lead I)
13
Figure 18 – Multiple Lead Display
Receiving the Data
The data is received through the serial port using COMM 2 at a baud rate of 115.2 kbps
in 500us intervals. The application receives the data for the three leads of the ECG signal
continuously in the following order: LeadI data byte, LeadII data byte, LeadIII, data byte.
As the data is received, the appropriate display area is updated.
X Plot
The display is meant to behave as an oscilloscope although limited in functionality. To

observe the ECG signal moving in time from the left to right, the x-coordinate is
incremented with each new data value received. A “scale factor” controls the rate that the
screen is refreshed.
Horizontal scaling provides a means of controlling the number of pulses displayed. The
person observing the signal has limited control over how long it takes the ECG signal to
pan the width of the display through a scroll bar located directly beneath the display. The
horizontal range was chosen to be able to display 2 beats. Heart rates can vary between
40 and 240 beats per minute or 1.5 and 0.25 seconds per beat respectively so the refresh
rate was chosen to vary between 0.125 sec and 3 sec. To achieve refresh rates
14
wihthin0.125 sec and 3 sec, the display width was set to be between 500 and 6000 pixels.
The scroll bar controls this “scale factor”
Y Plot
The y-coordinate is obtained directly from the incoming data. Since the incoming data is
within the range of 0 to 255, the vertical scaling for each lead translates to the same
range.
Reliability Considerations
The ECG monitor needs to be very reliable considering its’ application in the medical
field. The transmission frequency of 2.45 GHz is within the ISM band which is the band
reserved for non-commercial use of RF electromagnetic fields for industrial, scientific
and medical purposes. To avoid interference and loss of data, the nRF24L01 transceiver
modules are capable of addressing up to six data pipes per module. In addition, reliability
is ensured in the form of error detection and correction.
Each data packet includes one byte for a cyclic redundancy check (CRC) to detect the
presence of errors. Upon detection of any errors, a retransmission is requested to recover
the data that may have been lost. Up to 15 retransmissions will be requested before
finally discarding the data packet and carry on. The system can handle up to four packet
losses and still maintain the integrity of the displayed signal.
Testing was performed to determine the range with which the transceivers could reliable
operate within, i.e. 0 packet loss. The methodology used was to observe the number lost
packets in software at various distances. A radius of up to 5m found to be reliable. This
was the target radius since this is roughly the upper limit on the distance between
transmitter and receiver in an operating room.
Discussions & Recommendations
The Wireless ECG/EKG Monitoring System was designed and built, and was very
successful. A few modifications would be implemented if time permitted.
The first and most obvious change involves the circuit board. It was very big and
awkward. It served its purpose as a prototype board. However, if this product were to
got to production, the board would need to be re-designed into a smaller package using
surface mount components.
Next time, the filtering would be done digitally using a DSP chip. This would allow for
much more accurate filtering using an FIR or Wavelets.
The final change that would be considered would be to allow for some sort of automatic
adjustments of the gain. Every individual has a unique heartbeat. The amplitudes will
vary from person to person. The current configuration allows the gain to be adjusted
15
manually, but this is a slow and tedious task. Next time the gain would be adjusted in
firmware. This would be much faster and more accurate.
The overall performance of this project was excellent. There was positive feedback from
the judges, and we were awarded 3rd prize for our efforts. Below are a series of photos
from the demonstration.
16
References
Robert M. Berne and Matthew N. Levy, Cardiovascular Physiology 2nd Edition

The C.V. Mosby Company, St. Louis 1972
National Semiconductor - LM741 Operational Amplifier Datasheet
Analog Devices – AD620 Instrumentation Amplifier Datasheet
Nordic Semiconductor – Single chip 433/868/915 MHz Transceiver nRF905
Dallas Semiconductor - +5V-Powered, Multichannel RS-232 Drivers/Receivers datasheet
Microchip - PIC16F87X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers Datasheet
17
Appendix A
PCB Files
1 2 3 4 5 6 7 8
+6V
R3 R15
R2 1K Res1
1K 10K R18
200K C13
+6V
R1
7
Vref (micro) +6V
7
1K +6V 100nF U4 8
7
1 U1 U7 8 2
8 2 6
RA 2 C1 6 R21 R24 R27 3
D1 D2
5.1V Zener 6 3 3.9K 82K 82K 5
-6V -6V3.3 V Zener LA 3 5 1 R30
Cap Pol3 C4 C5 45K
1 C10 LM741
4
A 5 100uF LM741 10nF A
1uF 1uF
4
-6V AD620AN R6 R12 -6V Lead I
4
2.2K 1K -6V
C16
100nF
R16
R9 10K
1K
R4 R19
1K 200K C14
1K +6V
7
+6V
7
JP1 +6V 100nF U5 8
7
+6V 1 U2 U8 8 2
1
8 2 6
2 R22 R25 R28
-6V RA 2 C2 6 3
3
LL 6 3 3.9K 82K 82K 5
4 R31
LA LL 3 5 1
5 Cap Pol3 C6 C7 45K
RA 1 C11 LM741
4
6 100uF
5 LM741 1uF 1uF 10nF Lead II
4
Header 6H -6V AD620AN R13 -6V
4
1K -6V
R7 C17
2.2K 100nF
R10
1K
R5 R17 R20
1K 10K 200K C15
+6V
7
+6V
7
+6V 100nF U6 8
7
B 1 U3 U9 8 2 B
8 2 6
LA 2 C3 6 R23 R26 R29 3
6 3 3.9K 82K 82K 5
LL 3 5 1 R32
Cap Pol3 C8 C9 45K
1 C12 LM741
4
5 100uF R14 LM741 1uF 1uF 10nF Lead III
4
-6V AD620AN R8 1K -6V
4
2.2K
-6V
C18
100nF
R11
1K
C23
0.1uF
U11
C25 1 16 VDD C24
C1+ VCC
3 2 VDD
C1- V+
VDD 4
Cap C2+ 0.1uF
5
R36 0.1uF C2-
VDD VCC
47 TX 11 14
R33
4.7K 10 7
D5
OSC1 3.3 V Zener RX 12 13
9 8
1 2 OSC2 Vref (micro) C26
C Vref (micro) 15 6 Vref (micro) C
XTAL1 GND V-
C20 C19 MAX232 0.1uF
22pF 22pF
U10
Vref (micro) Vref (micro) OSC1 13 11 VDD
OSC1/CLKI VDD
MCLR! 1 32 VDD
MCLR/VPP VDD
14 OSC2
OSC2/CLKO
JP2
Lead I 2 15 Vref (micro)
RA0 RC0/T1OSI/T1CKI 1
Lead II 3 16 CSN IRQ
RA1 RC1/T1OSO/CCP2 2
VDD 4 17 CE MISO
RA2 RC2/CCP1 3
5 18 SCK MOSI
RA3 RC3/SCK/SCL 4
R34 6 23 MISO SCK
RA4/T0CKI RC4/SDI/SDA 5
4.7K Lead III 7 24 MOSI CSN Vref (micro)
RA5/SS RC5/SDO 6
5
9
4
8
3
7
2
6
1
25 TX CE
RC6/TX/CK 7
MCLR! 26 RX VCC
RC7/RX/DT 8 J3
D3 33 19 Header 8 D Connector 9
RB0/INT RD0/PSP0
C27 34 20
RB1 RD1/PSP1
SW1 0.1uF 35 21
RB2 RD2/PSP2
SW-PB 36 22
10
11
RB3 RD3/PSP3
37 27
RB4 RD4/PSP4
IRQ 38 28
RB5 RD5/PSP5
39 29
RB6 RD6/PSP6
40 30
RB7 RD7/PSP7
8
RE0/RD
Vref (micro) Vref (micro) Vref (micro) 12 9
VSS RE1/WR
Vref (micro) 31 10
VSS RE2/CS
PIC16C65-20I/P
VR1
D 5 Volt Reg D
+6V VDD
Vin Vout
D6 GND R35 C22
C21 470 0.1uF
22uF
Vref (micro) Vref (micro) 1 2 Vref (micro)

Title
D4
Vref (micro)
Size Number Revision
A2
Date: 30/07/2006 Sheet of
File: C:\Documents and Settings\..\ecg.SCHDOCDrawn By:
1 2 3 4 5 6 7 8
Designator Description Footprint Comment
C1 100u RAD-0.1 Cap Pol3
C10 10n RAD-0.1 Cap
C11 10n RAD-0.1 Cap
C12 10n RAD-0.1 Cap
C13 100n RAD-0.1 Cap
C19 22p RAD-0.1 Cap
C20 22p RAD-0.1 Cap
C21 0.1u RAD-0.1 Cap Pol1
C22 22u RAD-0.1 Cap
C23 0.1u RAD-0.1 Cap
D1 5.1V Zener AXIAL-0.3 5.1V Zener
D2 3.3 V Zener AXIAL-0.3 3.3 V Zener
D3 D Zener AXIAL-0.3 D Zener
D4 LED1 AXIAL-0.3 LED1
D5 3.3 V Zener AXIAL-0.3 3.3 V Zener
D6 Diode AXIAL-0.3 Diode
J3 D Connector 9 DSUB1.385-2H9 D Connector 9
JP1 Header 6H HDR1X6 Header 6H
JP2 Header 8 HDR1X8 Header 8
R1 1K AXIAL-0.3 Res1
R6 2K2 AXIAL-0.3 Res1
R9 1K VR4 RPot1
R10 1K VR4 RPot1
R11 1K VR4 RPot1
R18 200K VR4 RPot1
R19 200K VR4 RPot1
R20 200K VR4 RPot1
R35 470R AXIAL-0.3 Res1
R36 47R AXIAL-0.3 Res1
SW1 Push Button Switch SPST-2 SW-PB
U1 AD620AN DIP-8 AD620AN
U4 LM741 DIP-8 LM741
U10 PIC16C65-20I/P DIP-P40/X.85 PIC16C65-20I/P
U11 MAX232 DIP-16/X1.5 MAX232
VR1 5 Volt Reg SPDT-3 5 Volt Reg
XTAL1 XTAL RAD-0.1 XTAL
Appendix B
Datasheets
a Low Cost, Low Power
Instrumentation Amplifier
AD620
FEATURES CONNECTION DIAGRAM
EASY TO USE 8-Lead Plastic Mini-DIP (N), Cerdip (Q)
Gain Set with One External Resistor and SOIC (R) Packages
(Gain Range 1 to 1000)
Wide Power Supply Range (62.3 V to 618 V)
RG 1 8 RG
Higher Performance than Three Op Amp IA Designs
Available in 8-Lead DIP and SOIC Packaging –IN 2 7 +VS
Low Power, 1.3 mA max Supply Current +IN 3 6 OUTPUT
EXCELLENT DC PERFORMANCE (“B GRADE”) –VS 4 AD620 5 REF

50 mV max, Input Offset Voltage
0.6 mV/8C max, Input Offset Drift TOP VIEW
1.0 nA max, Input Bias Current

100 dB min Common-Mode Rejection Ratio (G = 10) 1000. Furthermore, the AD620 features 8-lead SOIC and DIP
LOW NOISE packaging that is smaller than discrete designs, and offers lower
9 nV/√Hz, @ 1 kHz, Input Voltage Noise power (only 1.3 mA max supply current), making it a good fit
0.28 mV p-p Noise (0.1 Hz to 10 Hz) for battery powered, portable (or remote) applications.
The AD620, with its high accuracy of 40 ppm maximum
EXCELLENT AC SPECIFICATIONS
nonlinearity, low offset voltage of 50 µV max and offset drift of
120 kHz Bandwidth (G = 100)
0.6 µV/°C max, is ideal for use in precision data acquisition
15 ms Settling Time to 0.01%
systems, such as weigh scales and transducer interfaces. Fur-
APPLICATIONS thermore, the low noise, low input bias current, and low power
Weigh Scales of the AD620 make it well suited for medical applications such
ECG and Medical Instrumentation as ECG and noninvasive blood pressure monitors.
Transducer Interface The low input bias current of 1.0 nA max is made possible with
Data Acquisition Systems the use of Superβeta processing in the input stage. The AD620
Industrial Process Controls works well as a preamplifier due to its low input voltage noise of
Battery Powered and Portable Equipment 9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,
0.1 pA/√Hz input current noise. Also, the AD620 is well suited
PRODUCT DESCRIPTION for multiplexed applications with its settling time of 15 µs to
The AD620 is a low cost, high accuracy instrumentation ampli- 0.01% and its cost is low enough to enable designs with one in-
fier that requires only one external resistor to set gains of 1 to amp per channel.
30,000 10,000
TOTAL ERROR, PPM OF FULL SCALE
25,000 3 OP-AMP
IN-AMP 1,000
(3 OP-07s) TYPICAL STANDARD
RTI VOLTAGE NOISE
(0.1 – 10Hz) – mV p-p
20,000 BIPOLAR INPUT

IN-AMP
100
15,000 G = 100
AD620A
10
10,000
RG
AD620 SUPERbETA
BIPOLAR INPUT
1 IN-AMP
5,000
0 0.1
0 5 10 15 20 1k 10k 100k 1M 10M 100M
SUPPLY CURRENT – mA SOURCE RESISTANCE – V
Figure 1. Three Op Amp IA Designs vs. AD620 Figure 2. Total Voltage Noise vs. Source Resistance
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD620–SPECIFICATIONS (Typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)
AD620A AD620B AD620S1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
GAIN G = 1 + (49.4 k/R G)

Gain Range 1 10,000 1 10,000 1 10,000
Gain Error2 VOUT = ± 10 V
G=1 0.03 0.10 0.01 0.02 0.03 0.10 %
G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %
G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %
Nonlinearity, VOUT = –10 V to +10 V,
G = 1–1000 RL = 10 kΩ 10 40 10 40 10 40 ppm
G = 1–100 RL = 2 kΩ 10 95 10 95 10 95 ppm
Gain vs. Temperature
G =1 10 10 10 ppm/°C
Gain >1 2 –50 –50 –50 ppm/°C
VOLTAGE OFFSET (Total RTI Error = V OSI + VOSO/G)

Input Offset, VOSI VS = ± 5 V to ± 15 V 30 125 15 50 30 125 µV
Over Temperature VS = ± 5 V to ± 15 V 185 85 225 µV
Average TC VS = ± 5 V to ± 15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C
Output Offset, V OSO VS = ± 15 V 400 1000 200 500 400 1000 µV
VS = ± 5 V 1500 750 1500 µV
Over Temperature VS = ± 5 V to ± 15 V 2000 1000 2000 µV
Average TC VS = ± 5 V to ± 15 V 5.0 15 2.5 7.0 5.0 15 µV/°C
Offset Referred to the
Input vs.
Supply (PSR) VS = ± 2.3 V to ± 18 V
G=1 80 100 80 100 80 100 dB
G = 10 95 120 100 120 95 120 dB
G = 100 110 140 120 140 110 140 dB
G = 1000 110 140 120 140 110 140 dB
INPUT CURRENT
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10i2 10i2 10i2 GΩipF
Common-Mode 10i2 10i2 10i2 GΩipF
Input Voltage Range 3 VS = ± 2.3 V to ± 5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
Over Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
I kΩ Source Imbalance VCM = 0 V to ± 10 V
G=1 73 90 80 90 73 90 dB
G = 10 93 110 100 110 93 110 dB
G = 100 110 130 120 130 110 130 dB
G = 1000 110 130 120 130 110 130 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ± 2.3 V to ± 5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
VS = ± 5 V to ± 18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
Short Current Circuit ± 18 ± 18 ± 18 mA
–2– REV. E
AD620
AD620A AD620B AD620S1
Model Conditions Min Typ Max Min Typ Max Min Typ Max Units
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G=1 1000 1000 1000 kHz
G = 10 800 800 800 kHz
G = 100 120 120 120 kHz
G = 1000 12 12 12 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step
G = 1–100 15 15 15 µs
G = 1000 150 150 150 µs
NOISE
Voltage Noise, 1 kHz Total RTI Noise = (e2 ni ) + (eno / G)2
Input, Voltage Noise, e ni 9 13 9 13 9 13 nV/√Hz
Output, Voltage Noise, e no 72 100 72 100 72 100 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G=1 3.0 3.0 6.0 3.0 6.0 µV p-p
G = 10 0.55 0.55 0.8 0.55 0.8 µV p-p
G = 100–1000 0.28 0.28 0.4 0.28 0.4 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz to 10 Hz 10 10 10 pA p-p
REFERENCE INPUT
RIN 20 20 20 kΩ
IIN VIN+ , VREF = 0 +50 +60 +50 +60 +50 +60 µA
Voltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
POWER SUPPLY
Operating Range 4 ± 2.3 ± 18 ± 2.3 ± 18 ± 2.3 ± 18 V
Quiescent Current VS = ± 2.3 V to ± 18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
Does not include effects of external resistor R G.
3
One input grounded. G = 1.
4
This is defined as the same supply range which is used to specify PSR.
Specifications subject to change without notice.
REV. E –3–
AD620
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW Model Temperature Ranges Package Options*
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS AD620AN –40°C to +85°C N-8
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .± 25 V AD620BN –40°C to +85°C N-8
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite AD620AR –40°C to +85°C SO-8
Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C AD620AR-REEL –40°C to +85°C 13" REEL
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C AD620AR-REEL7 –40°C to +85°C 7" REEL
Operating Temperature Range AD620BR –40°C to +85°C SO-8
AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD620BR-REEL –40°C to +85°C 13" REEL
AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C AD620BR-REEL7 –40°C to +85°C 7" REEL
Lead Temperature Range AD620ACHIPS –40°C to +85°C Die Form
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C AD620SQ/883B –55°C to +125°C Q-8
NOTES
1 *N = Plastic DIP; Q = Cerdip; SO = Small Outline.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package: θJA = 95°C/W
8-Lead Cerdip Package: θJA = 110°C/W
8-Lead SOIC Package: θJA = 155°C/W
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
RG* +VS OUTPUT
8 7 6
5 REFERENCE
8
0.0708
(1.799)
1 2 3 4
0.125 –VS
RG* (3.180)
–IN +IN
*FOR CHIP APPLICATIONS: THE PADS 1RG AND 8RG MUST BE CONNECTED IN PARALLEL
TO THE EXTERNAL GAIN REGISTER RG. DO NOT CONNECT THEM IN SERIES TO RG. FOR
UNITY GAIN APPLICATIONS WHERE RG IS NOT REQUIRED, THE PADS 1RG MAY SIMPLY
BE BONDED TOGETHER, AS WELL AS THE PADS 8RG.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
–4– REV. E
AD620
Typical Characteristics (@ +258C, V = 615 V, R = 2 kV, unless otherwise noted) S L
50 2.0
SAMPLE SIZE = 360
1.5
40
INPUT BIAS CURRENT – nA

PERCENTAGE OF UNITS
1.0
+IB
–I B
30 0.5
20
–0.5
–1.0
10
–1.5
0
–2.0
–80 –40 0 +40 +80 –75 –25 25 75 125 175
INPUT OFFSET VOLTAGE – mV TEMPERATURE – 8C
Figure 3. Typical Distribution of Input Offset Voltage Figure 6. Input Bias Current vs. Temperature
50 2
SAMPLE SIZE = 850
CHANGE IN OFFSET VOLTAGE – mV

40
1.5
PERCENTAGE OF UNITS
30
20
0.5
10
0
0
–1200 –600 0 +600 +1200 0 1 2 3 4 5
INPUT BIAS CURRENT – pA WARM-UP TIME – Minutes
Figure 4. Typical Distribution of Input Bias Current Figure 7. Change in Input Offset Voltage vs.
Warm-Up Time
50 1000
SAMPLE SIZE = 850
40 GAIN = 1
PERCENTAGE OF UNITS
VOLTAGE NOISE – nV/!Hz
100
30
GAIN = 10
20
10
10
GAIN = 100, 1,000
GAIN = 1000
BW LIMIT
0 1
–400 –200 0 +200 +400
1 10 100 1k 10k 100k
INPUT OFFSET CURRENT – pA FREQUENCY – Hz
Figure 5. Typical Distribution of Input Offset Current Figure 8. Voltage Noise Spectral Density vs. Frequency,
(G = 1–1000)
REV. E –5–
AD620–Typical Characteristics
1000
CURRENT NOISE – fA/!Hz
100
10
1 10 100 1000
FREQUENCY – Hz
Figure 9. Current Noise Spectral Density vs. Frequency Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
100,000
TOTAL DRIFT FROM 258C TO 858C, RTI – mV

10,000
RTI NOISE – 2.0 mV/DIV
FET INPUT
IN-AMP
1000
AD620A
100
10
TIME – 1 SEC/DIV 1k 10k 100k 1M 10M
SOURCE RESISTANCE – V
Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Figure 12. Total Drift vs. Source Resistance
+160
+140 G = 1000
G = 100
+120
RTI NOISE – 0.1mV/DIV
G = 10
+100
CMR – dB
G=1
+80
+60
+40
+20
0
TIME – 1 SEC/DIV 0.1 1 10 100 1k 10k 100k 1M
FREQUENCY – Hz
Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 13. CMR vs. Frequency, RTI, Zero to 1 kΩ Source
Imbalance
–6– REV. E
AD620
180 35
G = 10, 100, 1000
160
30
OUTPUT VOLTAGE – Volts p-p

140
G = 1000 25
120 G=1
PSR – dB
20
100 G = 100
BW LIMIT
15
80
G = 10
10
60
G=1 5
40
G = 1000
G = 100
20 0
0.1 1 10 100 1k 10k 100k 1M 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz
Figure 14. Positive PSR vs. Frequency, RTI (G = 1–1000) Figure 17. Large Signal Frequency Response
180 +VS –0.0
160 –0.5
(REFERRED TO SUPPLY VOLTAGES)

INPUT VOLTAGE LIMIT – Volts
140 –1.0
120 –1.5
PSR – dB
100
G = 1000
80 +1.5
G = 100
60 +1.0
G = 10
40 +0.5
G=1
20 –VS +0.0
0.1 1 10 100 1k 10k 100k 1M 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE 6 Volts
Figure 15. Negative PSR vs. Frequency, RTI (G = 1–1000) Figure 18. Input Voltage Range vs. Supply Voltage, G = 1
1000 +VS –0.0
–0.5
(REFERRED TO SUPPLY VOLTAGES)
OUTPUT VOLTAGE SWING – Volts
RL = 10kV
100 –1.0
RL = 2kV
–1.5
GAIN – V/V
10
+1.5
RL = 2kV
1 +1.0
+0.5 RL = 10kV
0.1 –VS +0.0

100 1k 10k 100k 1M 10M 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE 6 Volts
Figure 16. Gain vs. Frequency Figure 19. Output Voltage Swing vs. Supply Voltage,
G = 10
REV. E –7–
AD620
30
OUTPUT VOLTAGE SWING – Volts p-p
VS = 615V .... .... .... ........ ........ .... ........

G = 10
20
10
.... .... .... ........ ........ .... ........
0
0 100 1k 10k
LOAD RESISTANCE – V
Figure 20. Output Voltage Swing vs. Load Resistance Figure 23. Large Signal Response and Settling Time,
G = 10 (0.5 mV = 001%)
.... .... .... ........ ........ .... ........ .... .... ........ .... ........ .... ........
.... .... .... ........ ........ .... ........ .... .... ........ .... ........ .... ........
Figure 21. Large Signal Pulse Response and Settling Time Figure 24. Small Signal Response, G = 10, RL = 2 kΩ,
G = 1 (0.5 mV = 0.01%) CL = 100 pF
.... .... .... ........ ........ .... ........ .... .... .... ........ ........ .... ........
.... .... .... ........ ........ .... ........ .... .... .... ........ ........ .... ........
Figure 22. Small Signal Response, G = 1, RL = 2 kΩ, Figure 25. Large Signal Response and Settling Time,
CL = 100 pF G = 100 (0.5 mV = 0.01%)
–8– REV. E
AD620
20
.... .... .... ........ ........ .... ........

15
TO 0.01%
SETTLING TIME – ms
TO 0.1%
10
5
.... .... .... ........ ........ .... ........
0
0 5 10 15 20
OUTPUT STEP SIZE – Volts
Figure 26. Small Signal Pulse Response, G = 100, Figure 29. Settling Time vs. Step Size (G = 1)
RL = 2 kΩ, CL = 100 pF
1000
.... .... ........ ........ .... .... ........
SETTLING TIME – ms 100
10
.... .... ........ ........ .... .... ........
1
1 10 100 1000
GAIN
Figure 27. Large Signal Response and Settling Time, Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step
G = 1000 (0.5 mV = 0.01%)
.... .... .... ........ ........ .... ........ .... .... ........ ........ .... .... ........
.... .... .... ........ ........ .... ........ .... .... ........ ........ .... .... ........
Figure 28. Small Signal Pulse Response, G = 1000, Figure 31a. Gain Nonlinearity, G = 1, RL = 10 kΩ
RL = 2 kΩ, CL = 100 pF (10 µ V = 1 ppm)
REV. E –9–
AD620
I1 20mA VB 20mA I2
.... .... .... ........ .... .... .... ........

A1 A2
10kV
C1 C2
10kV
A3 OUTPUT
R3 10kV 10kV
R1 R2 REF
400V
– IN Q1 Q2 +IN
R4
.... .... .... ........ .... .... .... ........ RG 400V
GAIN GAIN
SENSE SENSE
–VS
Figure 33. Simplified Schematic of AD620

Figure 31b. Gain Nonlinearity, G = 100, RL = 10 kΩ
(100 µ V = 10 ppm) THEORY OF OPERATION
The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to
0.15% at G = 100) with only one resistor. Monolithic construc-
tion and laser wafer trimming allow the tight matching and
.... .... ........ ........ .... .... ........
tracking of circuit components, thus ensuring the high level of
performance inherent in this circuit.
The input transistors Q1 and Q2 provide a single differential-
pair bipolar input for high precision (Figure 33), yet offer 10×
lower Input Bias Current thanks to Superβeta processing. Feed-
back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main-
tains constant collector current of the input devices Q1, Q2
.... .... ........ ........ .... .... ........ thereby impressing the input voltage across the external gain
setting resistor RG. This creates a differential gain from the
inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1.
The unity-gain subtracter A3 removes any common-mode sig-
nal, yielding a single-ended output referred to the REF pin
potential.
Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 kΩ The value of RG also determines the transconductance of the
(1 mV = 100 ppm) preamp stage. As RG is reduced for larger gains, the transcon-
ductance increases asymptotically to that of the input transistors.
1kV
10kV* 10T 10kV This has three important advantages: (a) Open-loop gain is
INPUT
10V p-p
boosted for increasing programmed gain, thus reducing gain-
100kV
VOUT
related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The
+VS
2
input voltage noise is reduced to a value of 9 nV/√Hz, deter-
11kV 1kV 100V
7
mined mainly by the collector current and base resistance of the
1
G=1000 G=1
input devices.
AD620 6 The internal gain resistors, R1 and R2, are trimmed to an abso-
G=100 G=10
lute value of 24.7 kΩ, allowing the gain to be programmed
49.9V 499V 5.49kV
8
5 accurately with a single external resistor.
4
3 The gain equation is then
–VS 49.4 kΩ
*ALL RESISTORS 1% TOLERANCE G= +1
RG
Figure 32. Settling Time Test Circuit
so that
49.4 kΩ
RG =
G −1
–10– REV. E
AD620
Make vs. Buy: A Typical Bridge Application Error Budget systems, absolute accuracy and drift errors are by far the most
The AD620 offers improved performance over “homebrew” significant contributors to error. In more complex systems with
three op amp IA designs, along with smaller size, fewer compo- an intelligent processor, an autogain/autozero cycle will remove all
nents and 10× lower supply current. In the typical application, absolute accuracy and drift errors leaving only the resolution
shown in Figure 34, a gain of 100 is required to amplify a bridge errors of gain nonlinearity and noise, thus allowing full 14-bit
output of 20 mV full scale over the industrial temperature range accuracy.
of –40°C to +85°C. The error budget table below shows how to Note that for the homebrew circuit, the OP07 specifications for
calculate the effect various error sources have on circuit accuracy. input voltage offset and noise have been multiplied by √2. This
Regardless of the system in which it is being used, the AD620 is because a three op amp type in-amp has two op amps at its
provides greater accuracy, and at low power and price. In simple inputs, both contributing to the overall input error.
+10V
10kV* 10kV*
OP07D
R = 350V R = 350V
10kV**
RG
499V AD620A 100V** 10kV** OP07D
R = 350V R = 350V
REFERENCE
OP07D
10kV* 10kV*
AD620A MONOLITHIC
PRECISION BRIDGE TRANSDUCER INSTRUMENTATION “HOMEBREW” IN-AMP, G = 100
AMPLIFIER, G = 100 *0.02% RESISTOR MATCH, 3PPM/8C TRACKING
**DISCRETE 1% RESISTOR, 100PPM/8C TRACKING
SUPPLY CURRENT = 15mA MAX
SUPPLY CURRENT = 1.3mA MAX
Figure 34. Make vs. Buy
Table I. Make vs. Buy Error Budget
AD620 Circuit “Homebrew” Circuit Error, ppm of Full Scale

Error Source Calculation Calculation AD620 Homebrew
ABSOLUTE ACCURACY at TA = +25°C
Input Offset Voltage, µV 125 µV/20 mV (150 µV × √2)/20 mV 16,250 10,607
Output Offset Voltage, µV 1000 µV/100/20 mV ((150 µV × 2)/100)/20 mV 14,500 10,150
Input Offset Current, nA 2 nA × 350 Ω/20 mV (6 nA × 350 Ω)/20 mV 14,118 14,153
CMR, dB 110 dB→3.16 ppm, × 5 V/20 mV (0.02% Match × 5 V)/20 mV/100 14,791 10,500
Total Absolute Error 17,558 11,310
DRIFT TO +85°C
Gain Drift, ppm/°C (50 ppm + 10 ppm) × 60°C 100 ppm/°C Track × 60°C 13,600 16,000
Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV (2.5 µV/°C × √2 × 60°C)/20 mV 13,000 10,607
Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100/20 mV (2.5 µV/°C × 2 × 60°C)/100/20 mV 14,450 10,150
Total Drift Error 17,050 16,757
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 14,140 10,140
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 141,14 13,127
Total Resolution Error 14,154 101,67
Grand Total Error 14,662 28,134
G = 100, VS = ± 15 V.
(All errors are min/max and referred to input.)
REV. E –11–
AD620
+5V
20kV
7
3
3kV 3kV REF
8
G=100 AD620B 6 IN
499V DIGITAL
3kV 3kV 5
1 10kV ADC DATA
OUTPUT
2 4
AD705 AGND
20kV
0.6mA
1.7mA 1.3mA 0.10mA
MAX
MAX
Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply
Pressure Measurement Medical ECG

Although useful in many bridge applications such as weigh The low current noise of the AD620 allows its use in ECG
scales, the AD620 is especially suitable for higher resistance monitors (Figure 36) where high source resistances of 1 MΩ or
pressure sensors powered at lower voltages where small size and higher are not uncommon. The AD620’s low power, low supply
low power become more significant. voltage requirements, and space-saving 8-lead mini-DIP and
Figure 35 shows a 3 kΩ pressure transducer bridge powered SOIC package offerings make it an excellent choice for battery
from +5 V. In such a circuit, the bridge consumes only 1.7 mA. powered data recorders.
Adding the AD620 and a buffered voltage divider allows the Furthermore, the low bias currents and low current noise
signal to be conditioned for only 3.8 mA of total supply current. coupled with the low voltage noise of the AD620 improve the
Small size and low cost make the AD620 especially attractive for dynamic range for better performance.
voltage output pressure transducers. Since it delivers low noise The value of capacitor C1 is chosen to maintain stability of the
and drift, it will also serve applications such as diagnostic non- right leg drive loop. Proper safeguards, such as isolation, must
invasive blood pressure measurement. be added to this circuit to protect the patient from possible
harm.
+3V
PATIENT/CIRCUIT
PROTECTION/ISOLATION
R1 R3
C1 24.9kV 0.03Hz
10kV RG HIGH OUTPUT
8.25kV AD620A PASS G = 143 1V/mV
R4 R2 G=7 FILTER
1MV 24.9kV
OUTPUT
AMPLIFIER
AD705J
–3V
Figure 36. A Medical ECG Monitor Circuit
–12– REV. E
AD620
Precision V-I Converter INPUT AND OUTPUT OFFSET VOLTAGE
The AD620, along with another op amp and two resistors, makes The low errors of the AD620 are attributed to two sources,
a precision current source (Figure 37). The op amp buffers the input and output errors. The output error is divided by G when
reference terminal to maintain good CMR. The output voltage referred to the input. In practice, the input errors dominate at
VX of the AD620 appears across R1, which converts it to a high gains and the output errors dominate at low gains. The
current. This current less only, the input bias current of the op total VOS for a given gain is calculated as:
amp, then flows out to the load.
Total Error RTI = input error + (output error/G)
+VS Total Error RTO = (input error × G) + output error
VIN+ 3 7 REFERENCE TERMINAL

8 The reference terminal potential defines the zero output voltage,
+ VX –
RG AD620 6 and is especially useful when the load does not share a precise
1
R1 ground with the rest of the system. It provides a direct means of
5
VIN– 2
injecting a precise offset to the output, with an allowable range
4 I
L of 2 V within the supply voltages. Parasitic resistance should be
–VS kept to a minimum for optimum CMR.
AD705
Vx [(V IN+) – (V IN– )] G INPUT PROTECTION
I L= =
R1 R1
LOAD The AD620 features 400 Ω of series thin film resistance at its
inputs, and will safely withstand input overloads of up to ± 15 V
or ±60 mA for several hours. This is true for all gains, and power
Figure 37. Precision Voltage-to-Current Converter on and off, which is particularly important since the signal
(Operates on 1.8 mA, ± 3 V) source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA (IIN ≤
GAIN SELECTION VIN/400 Ω). For input overloads beyond the supplies, clamping
The AD620’s gain is resistor programmed by RG, or more pre- the inputs to the supplies (using a low leakage diode such as an
cisely, by whatever impedance appears between Pins 1 and 8. FD333) will reduce the required resistance, yielding lower
The AD620 is designed to offer accurate gains using 0.1%–1% noise.
resistors. Table II shows required values of RG for various gains.
Note that for G = 1, the RG pins are unconnected (RG = ∞). For RF INTERFERENCE
any arbitrary gain RG can be calculated by using the formula: All instrumentation amplifiers can rectify out of band signals,
and when amplifying small signals, these rectified voltages act as
49.4 kΩ
RG = small dc offset errors. The AD620 allows direct access to the
G −1 input transistor bases and emitters enabling the user to apply
some first order filtering to unwanted RF signals (Figure 38),
To minimize gain error, avoid high parasitic resistance in series
where RC < 1/(2 πf) and where f ≥ the bandwidth of the
with RG; to minimize gain drift, RG should have a low TC—less
AD620; C ≤ 150 pF. Matching the extraneous capacitance at
than 10 ppm/°C—for the best performance.
Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.
Table II. Required Values of Gain Resistors RG
1% Std Table Calculated 0.1% Std Table Calculated

Value of RG, V Gain Value of RG, V Gain
1 8
49.9 k 1.990 49.3 k 2.002
C
12.4 k 4.984 12.4 k 4.984 R
–IN 2 7
5.49 k 9.998 5.49 k 9.998
R
2.61 k 19.93 2.61 k 19.93 +IN 3 6
1.00 k 50.40 1.01 k 49.91
499 100.0 499 100.0
4 5
249 199.4 249 199.4
100 495.0 98.8 501.0 C
49.9 991.0 49.3 1,003
Figure 38. Circuit to Attenuate RF Interference
REV. E –13–
AD620
COMMON-MODE REJECTION GROUNDING
Instrumentation amplifiers like the AD620 offer high CMR, Since the AD620 output voltage is developed with respect to the
which is a measure of the change in output voltage when both potential on the reference terminal, it can solve many grounding
inputs are changed by equal amounts. These specifications are problems by simply tying the REF pin to the appropriate “local
usually given for a full-range input voltage change and a speci- ground.”
fied source imbalance. In order to isolate low level analog signals from a noisy digital
For optimal CMR the reference terminal should be tied to a low environment, many data-acquisition components have separate
impedance point, and differences in capacitance and resistance analog and digital ground pins (Figure 41). It would be conve-
should be kept to a minimum between the two inputs. In many nient to use a single ground line; however, current through
applications shielded cables are used to minimize noise, and for ground wires and PC runs of the circuit card can cause hun-
best CMR over frequency the shield should be properly driven. dreds of millivolts of error. Therefore, separate ground returns
Figures 39 and 40 show active data guards that are configured should be provided to minimize the current flow from the sensi-
to improve ac common-mode rejections by “bootstrapping” the tive points to the system ground. These ground returns must be
capacitances of input cable shields, thus minimizing the capaci- tied together at some point, usually best at the ADC package as
tance mismatch between the inputs. shown.
+VS
ANALOG P.S. DIGITAL P.S.
– INPUT +15V C –15V C +5V
AD648
100V
0.1mF 0.1mF
1mF 1mF 1mF
RG
AD620 VOUT
100V +
–VS
AD620 DIGITAL
REFERENCE AD585 AD574A DATA
S/H ADC OUTPUT
+ INPUT
–VS
Figure 41. Basic Grounding Practice
Figure 39. Differential Shield Driver
+VS
– INPUT
RG
100V 2
AD548 AD620 VOUT
RG
2
REFERENCE
+ INPUT
–VS
Figure 40. Common-Mode Shield Driver
–14– REV. E
AD620
GROUND RETURNS FOR INPUT BIAS CURRENTS sources such as transformers, or ac-coupled sources, there must
Input bias currents are those currents necessary to bias the input be a dc path from each input to ground as shown in Figure 42.
transistors of an amplifier. There must be a direct return path Refer to the Instrumentation Amplifier Application Guide (free
for these currents; therefore, when amplifying “floating” input from Analog Devices) for more information regarding in amp
applications.
+VS +VS
– INPUT – INPUT
RG AD620 VOUT RG AD620 VOUT
LOAD LOAD
+ INPUT REFERENCE + INPUT REFERENCE
–VS –VS
TO POWER TO POWER
SUPPLY SUPPLY
GROUND GROUND
Figure 42a. Ground Returns for Bias Currents with Figure 42b. Ground Returns for Bias Currents with
Transformer Coupled Inputs Thermocouple Inputs
+VS
– INPUT
RG AD620 VOUT
LOAD
+ INPUT REFERENCE
100kV 100kV –VS
TO POWER
SUPPLY
GROUND
Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs
REV. E –15–
AD620
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
0.430 (10.92)
0.348 (8.84)
C1599c–0–7/99
8 5
0.280 (7.11)
0.240 (6.10)
1 4
0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
0.015 (0.38) 0.195 (4.95)
0.210 (5.33)
MAX 0.115 (2.93)
0.130
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204)
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
Cerdip (Q-8) Package
0.005 (0.13) 0.055 (1.4)

MIN MAX
8 5
0.310 (7.87)
0.220 (5.59)
1 4
PIN 1
0.320 (8.13)
0.405 (10.29) 0.290 (7.37)
MAX 0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX 0.150
0.200 (5.08) (3.81)
0.125 (3.18) MIN
0.015 (0.38)
0.023 (0.58) 0.100 0.070 (1.78) SEATING 15° 0.008 (0.20)
PLANE
0.014 (0.36) (2.54) 0.030 (0.76) 0°
BSC
SOIC (SO-8) Package
0.1968 (5.00)
0.1890 (4.80)
8 5
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 1 4 0.2284 (5.80)
PIN 1 0.0688 (1.75) 0.0196 (0.50)

x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.0040 (0.10)
8°
0.0500 0.0192 (0.49) 0° 0.0500 (1.27)
SEATING (1.27) 0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
PRINTED IN U.S.A.
0.0160 (0.41)
–16– REV. E
LM741 Operational Amplifier
August 2000
LM741
Operational Amplifier
General Description output, no latch-up when the common mode range is ex-
ceeded, as well as freedom from oscillations.
The LM741 series are general purpose operational amplifi-
The LM741C is identical to the LM741/LM741A except that
ers which feature improved performance over industry stan-
the LM741C has their performance guaranteed over a 0˚C to
dards like the LM709. They are direct, plug-in replacements
+70˚C temperature range, instead of −55˚C to +125˚C.
for the 709C, LM201, MC1439 and 748 in most applications.
The amplifiers offer many features which make their appli-
cation nearly foolproof: overload protection on the input and
Features
Connection Diagrams
Metal Can Package Dual-In-Line or S.O. Package
00934102 00934103
Note 1: LM741H is available per JM38510/10101 Order Number LM741J, LM741J/883, LM741CN
Order Number LM741H, LM741H/883 (Note 1), See NS Package Number J08A, M08A or N08E
LM741AH/883 or LM741CH
See NS Package Number H08C
Ceramic Flatpak
00934106
Order Number LM741W/883
See NS Package Number W10A
Typical Application
Offset Nulling Circuit
00934107
© 2004 National Semiconductor Corporation DS009341 www.national.com

LM741
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 7)
LM741A LM741 LM741C

Supply Voltage ± 22V ± 22V ± 18V
Power Dissipation (Note 3) 500 mW 500 mW 500 mW
Differential Input Voltage ± 30V ± 30V ± 30V
Input Voltage (Note 4) ± 15V ± 15V ± 15V
Output Short Circuit Duration Continuous Continuous Continuous
Operating Temperature Range −55˚C to +125˚C −55˚C to +125˚C 0˚C to +70˚C
Storage Temperature Range −65˚C to +150˚C −65˚C to +150˚C −65˚C to +150˚C
Junction Temperature 150˚C 150˚C 100˚C
Soldering Information
N-Package (10 seconds) 260˚C 260˚C 260˚C
J- or H-Package (10 seconds) 300˚C 300˚C 300˚C
M-Package
Vapor Phase (60 seconds) 215˚C 215˚C 215˚C
Infrared (15 seconds) 215˚C 215˚C 215˚C
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of
soldering
surface mount devices.
ESD Tolerance (Note 8) 400V 400V 400V
Electrical Characteristics (Note 5)

Parameter Conditions LM741A LM741 LM741C Units
Min Typ Max Min Typ Max Min Typ Max
Input Offset Voltage TA = 25˚C
RS ≤ 10 kΩ 1.0 5.0 2.0 6.0 mV
RS ≤ 50Ω 0.8 3.0 mV
TAMIN ≤ TA ≤ TAMAX
RS ≤ 50Ω 4.0 mV
RS ≤ 10 kΩ 6.0 7.5 mV
Average Input Offset 15 µV/˚C
Voltage Drift
Input Offset Voltage TA = 25˚C, VS = ± 20V ± 10 ± 15 ± 15 mV
Adjustment Range
Input Offset Current TA = 25˚C 3.0 30 20 200 20 200 nA
TAMIN ≤ TA ≤ TAMAX 70 85 500 300 nA
Average Input Offset 0.5 nA/˚C
Current Drift
Input Bias Current TA = 25˚C 30 80 80 500 80 500 nA
TAMIN ≤ TA ≤ TAMAX 0.210 1.5 0.8 µA
Input Resistance TA = 25˚C, VS = ± 20V 1.0 6.0 0.3 2.0 0.3 2.0 MΩ
TAMIN ≤ TA ≤ TAMAX, 0.5 MΩ
VS = ± 20V
Input Voltage Range TA = 25˚C ± 12 ± 13 V
TAMIN ≤ TA ≤ TAMAX ± 12 ± 13 V
www.national.com 2
LM741
Electrical Characteristics (Note 5) (Continued)
Parameter Conditions LM741A LM741 LM741C Units
Min Typ Max Min Typ Max Min Typ Max
Large Signal Voltage Gain TA = 25˚C, RL ≥ 2 kΩ
VS = ± 20V, VO = ± 15V 50 V/mV
VS = ± 15V, VO = ± 10V 50 200 20 200 V/mV
TAMIN ≤ TA ≤ TAMAX,
RL ≥ 2 kΩ,
VS = ± 20V, VO = ± 15V 32 V/mV
VS = ± 15V, VO = ± 10V 25 15 V/mV
VS = ± 5V, VO = ± 2V 10 V/mV
Output Voltage Swing VS = ± 20V
RL ≥ 10 kΩ ± 16 V
RL ≥ 2 kΩ ± 15 V
VS = ± 15V
RL ≥ 10 kΩ ± 12 ± 14 ± 12 ± 14 V
RL ≥ 2 kΩ ± 10 ± 13 ± 10 ± 13 V
Output Short Circuit TA = 25˚C 10 25 35 25 25 mA
Current TAMIN ≤ TA ≤ TAMAX 10 40 mA
Common-Mode TAMIN ≤ TA ≤ TAMAX
Rejection Ratio RS ≤ 10 kΩ, VCM = ± 12V 70 90 70 90 dB
RS ≤ 50Ω, VCM = ± 12V 80 95 dB
Supply Voltage Rejection TAMIN ≤ TA ≤ TAMAX,
Ratio VS = ± 20V to VS = ± 5V
RS ≤ 50Ω 86 96 dB
RS ≤ 10 kΩ 77 96 77 96 dB
Transient Response TA = 25˚C, Unity Gain
Rise Time 0.25 0.8 0.3 0.3 µs
Overshoot 6.0 20 5 5 %
Bandwidth (Note 6) TA = 25˚C 0.437 1.5 MHz
Slew Rate TA = 25˚C, Unity Gain 0.3 0.7 0.5 0.5 V/µs
Supply Current TA = 25˚C 1.7 2.8 1.7 2.8 mA
Power Consumption TA = 25˚C
VS = ± 20V 80 150 mW
VS = ± 15V 50 85 50 85 mW
LM741A VS = ± 20V
TA = TAMIN 165 mW
TA = TAMAX 135 mW
LM741 VS = ± 15V
TA = TAMIN 60 100 mW
TA = TAMAX 45 75 mW
Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
3 www.national.com
LM741
Electrical Characteristics (Note 5) (Continued)
Note 3: For operation at elevated temperatures, these devices must be derated based on thermal resistance, and Tj max. (listed under “Absolute Maximum
Ratings”). Tj = TA + (θjA PD).
Thermal Resistance Cerdip (J) DIP (N) HO8 (H) SO-8 (M)
θjA (Junction to Ambient) 100˚C/W 100˚C/W 170˚C/W 195˚C/W
θjC (Junction to Case) N/A N/A 25˚C/W N/A
Note 4: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 5: Unless otherwise specified, these specifications apply for VS = ± 15V, −55˚C ≤ TA ≤ +125˚C (LM741/LM741A). For the LM741C/LM741E, these
specifications are limited to 0˚C ≤ TA ≤ +70˚C.
Note 6: Calculated value from: BW (MHz) = 0.35/Rise Time(µs).
Note 7: For military specifications see RETS741X for LM741 and RETS741AX for LM741A.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Schematic Diagram
00934101
www.national.com 4
LM741
Physical Dimensions inches (millimeters)
unless otherwise noted
Metal Can Package (H)

Order Number LM741H, LM741H/883, LM741AH/883, LM741AH-MIL or LM741CH
NS Package Number H08C
5 www.national.com
LM741
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Ceramic Dual-In-Line Package (J)

Order Number LM741J/883
NS Package Number J08A
Dual-In-Line Package (N)

Order Number LM741CN
NS Package Number N08E
www.national.com 6
LM741 Operational Amplifier
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
10-Lead Ceramic Flatpak (W)

Order Number LM741W/883, LM741WG-MPR or LM741WG/883
NS Package Number W10A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, or device or system whose failure to perform can be reasonably
(b) support or sustain life, and whose failure to perform when expected to cause the failure of the life support device or
properly used in accordance with instructions for use system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship
Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned
Substances’’ as defined in CSP-9-111S2.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Americas Customer Europe Customer Support Center Asia Pacific Customer Japan Customer Support Center
Support Center Fax: +49 (0) 180-530 85 86 Support Center Fax: 81-3-5639-7507
Email: new.feedback@nsc.com Email: europe.support@nsc.com Email: ap.support@nsc.com Email: jpn.feedback@nsc.com
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English Tel: +44 (0) 870 24 0 2171
www.national.com Français Tel: +33 (0) 1 41 91 8790
19-4323; Rev 15; 1/06
+5V-Powered, Multichannel RS-232

Drivers/Receivers
General Description Next-Generation
MAX220–MAX249
The MAX220–MAX249 family of line drivers/receivers is Device Features
intended for all EIA/TIA-232E and V.28/V.24 communica- ♦ For Low-Voltage, Integrated ESD Applications
tions interfaces, particularly applications where ±12V is MAX3222E/MAX3232E/MAX3237E/MAX3241E/
not available. MAX3246E: +3.0V to +5.5V, Low-Power, Up to
These parts are especially useful in battery-powered sys- 1Mbps, True RS-232 Transceivers Using Four
tems, since their low-power shutdown mode reduces 0.1µF External Capacitors (MAX3246E Available
power dissipation to less than 5µW. The MAX225, in a UCSP™ Package)
MAX233, MAX235, and MAX245/MAX246/MAX247 use ♦ For Low-Cost Applications
no external components and are recommended for appli- MAX221E: ±15kV ESD-Protected, +5V, 1µA,
cations where printed circuit board space is critical. Single RS-232 Transceiver with AutoShutdown™
________________________Applications Ordering Information

Portable Computers PART TEMP RANGE PIN-PACKAGE
Low-Power Modems MAX220CPE 0°C to +70°C 16 Plastic DIP
MAX220CSE 0°C to +70°C 16 Narrow SO
Interface Translation
MAX220CWE 0°C to +70°C 16 Wide SO
Battery-Powered RS-232 Systems MAX220C/D 0°C to +70°C Dice*
Multidrop RS-232 Networks MAX220EPE -40°C to +85°C 16 Plastic DIP
MAX220ESE -40°C to +85°C 16 Narrow SO
MAX220EWE -40°C to +85°C 16 Wide SO
MAX220EJE -40°C to +85°C 16 CERDIP
MAX220MJE -55°C to +125°C 16 CERDIP
AutoShutdown and UCSP are trademarks of Maxim Integrated Ordering Information continued at end of data sheet.
Products, Inc. *Contact factory for dice specifications.
Selection Table
Power No. of Nominal SHDN Rx
Part Supply RS-232 No. of Cap. Value & Three- Active in Data Rate
Number (V) Drivers/Rx Ext. Caps (µF) State SHDN (kbps) Features
MAX220 +5 2/2 4 0.047/0.33 No — 120 Ultra-low-power, industry-standard pinout
MAX222 +5 2/2 4 0.1 Yes — 200 Low-power shutdown
MAX223 (MAX213) +5 4/5 4 1.0 (0.1) Yes ✔ 120 MAX241 and receivers active in shutdown
MAX225 +5 5/5 0 — Yes ✔ 120 Available in SO
MAX230 (MAX200) +5 5/0 4 1.0 (0.1) Yes — 120 5 drivers with shutdown
MAX231 (MAX201) +5 and 2/2 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;
+7.5 to +13.2 same functions as MAX232
MAX232 (MAX202) +5 2/2 4 1.0 (0.1) No — 120 (64) Industry standard
MAX232A +5 2/2 4 0.1 No — 200 Higher slew rate, small caps
MAX233 (MAX203) +5 2/2 0 — No — 120 No external caps
MAX233A +5 2/2 0 — No — 200 No external caps, high slew rate
MAX234 (MAX204) +5 4/0 4 1.0 (0.1) No — 120 Replaces 1488
MAX235 (MAX205) +5 5/5 0 — Yes — 120 No external caps
MAX236 (MAX206) +5 4/3 4 1.0 (0.1) Yes — 120 Shutdown, three state
MAX237 (MAX207) +5 5/3 4 1.0 (0.1) No — 120 Complements IBM PC serial port
MAX238 (MAX208) +5 4/4 4 1.0 (0.1) No — 120 Replaces 1488 and 1489
MAX239 (MAX209) +5 and 3/5 2 1.0 (0.1) No — 120 Standard +5/+12V or battery supplies;
+7.5 to +13.2 single-package solution for IBM PC serial port
MAX240 +5 5/5 4 1.0 Yes — 120 DIP or flatpack package
MAX241 (MAX211) +5 4/5 4 1.0 (0.1) Yes — 120 Complete IBM PC serial port
MAX242 +5 2/2 4 0.1 Yes ✔ 200 Separate shutdown and enable
MAX243 +5 2/2 4 0.1 No — 200 Open-line detection simplifies cabling
MAX244 +5 8/10 4 1.0 No — 120 High slew rate
MAX245 +5 8/10 0 — Yes ✔ 120 High slew rate, int. caps, two shutdown modes
MAX246 +5 8/10 0 — Yes ✔ 120 High slew rate, int. caps, three shutdown modes
MAX247 +5 8/9 0 — Yes ✔ 120 High slew rate, int. caps, nine operating modes
MAX248 +5 8/8 4 1.0 Yes ✔ 120 High slew rate, selective half-chip enables
MAX249 +5 6/10 4 1.0 Yes ✔ 120 Available in quad flatpack package
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS—MAX220/222/232A/233A/242/243
MAX220–MAX249
Supply Voltage (VCC) ...............................................-0.3V to +6V 18-Pin Plastic DIP (derate 11.11mW/°C above +70°C)..889mW
V+ (Note 1) ..................................................(VCC - 0.3V) to +14V 20-Pin Plastic DIP (derate 8.00mW/°C above +70°C) ..440mW
V- (Note 1) .............................................................+0.3V to +14V 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
Input Voltages 16-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
TIN..............................................................-0.3V to (VCC - 0.3V) 18-Pin Wide SO (derate 9.52mW/°C above +70°C)......762mW
RIN (Except MAX220) ........................................................±30V 20-Pin Wide SO (derate 10.00mW/°C above +70°C)....800mW
RIN (MAX220).....................................................................±25V 20-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW
TOUT (Except MAX220) (Note 2) .......................................±15V 16-Pin CERDIP (derate 10.00mW/°C above +70°C).....800mW
TOUT (MAX220)...............................................................±13.2V 18-Pin CERDIP (derate 10.53mW/°C above +70°C).....842mW
Output Voltages Operating Temperature Ranges
TOUT ...................................................................................±15V MAX2_ _AC_ _, MAX2_ _C_ _ .............................0°C to +70°C
ROUT .........................................................-0.3V to (VCC + 0.3V) MAX2_ _AE_ _, MAX2_ _E_ _ ..........................-40°C to +85°C
Driver/Receiver Output Short Circuited to GND.........Continuous MAX2_ _AM_ _, MAX2_ _M_ _ .......................-55°C to +125°C
Continuous Power Dissipation (TA = +70°C) Storage Temperature Range .............................-65°C to +160°C
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW Lead Temperature (soldering, 10s) (Note 3) ...................+300°C
Note 1: For the MAX220, V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V.
Note 2: Input voltage measured with TOUT in high-impedance state, SHDN or VCC = 0V.
Note 3: Maximum reflow temperature for the MAX223A is +225°C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243
(VCC = +5V ±10%, C1–C4 = 0.1µF‚ MAX220, C1 = 0.047µF, C2–C4 = 0.33µF, TA = TMIN to TMAX‚ unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
RS-232 TRANSMITTERS
Output Voltage Swing All transmitter outputs loaded with 3kΩ to GND ±5 ±8 V
Input Logic Threshold Low 1.4 0.8 V
All devices except MAX220 2 1.4
Input Logic Threshold High V
MAX220: VCC = 5.0V 2.4
All except MAX220, normal operation 5 40
Logic Pullup/lnput Current SHDN = 0V, MAX222/MAX242, shutdown, µA
±0.01 ±1
MAX220
VCC = 5.5V, SHDN = 0V, VOUT = ±15V,
±0.01 ±10
MAX222/MAX242
Output Leakage Current µA
VOUT = ±15V ±0.01 ±10
VCC = SHDN = 0V
MAX220, VOUT = ±12V ±25
Data Rate 200 116 kbps
Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M Ω
VOUT = 0V ±7 ±22
Output Short-Circuit Current VOUT = 0V mA
MAX220 ±60
RS-232 RECEIVERS
±30
RS-232 Input Voltage Operating Range V
MAX220 ±25
All except MAX243 R2IN 0.8 1.3
RS-232 Input Threshold Low VCC = 5V V
MAX243 R2 IN (Note 4) -3
All except MAX243 R2IN 1.8 2.4
RS-232 Input Threshold High VCC = 5V V
MAX243 R2 IN (Note 4) -0.5 -0.1
2 _______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)

All except MAX220/MAX243, VCC = 5V, no
0.2 0.5 1.0
hysteresis in SHDN
RS-232 Input Hysteresis V
MAX220 0.3
MAX243 1
3 5 7
RS-232 Input Resistance TA = +25°C (MAX220) KΩ
3 5 7
IOUT = 3.2mA 0.2 0.4
TTL/CMOS Output Voltage Low V
IOUT = 1.6mA (MAX220) 0.4
TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V
Sourcing VOUT = GND -2 -10
TTL/CMOS Output Short-Circuit Current mA
Shrinking VOUT = VCC 10 30
SHDN = VCC or EN = VCC (SHDN = 0V for
TTL/CMOS Output Leakage Current ±0.05 ±10 µA
MAX222), 0V ≤ VOUT ≤ VCC
EN Input Threshold Low MAX242 1.4 0.8 V
EN Input Threshold High MAX242 2.0 1.4 V
Operating Supply Voltage 4.5 5.5 V
MAX220 0.5 2
No load MAX222/MAX232A/MAX233A/
4 10
VCC Supply Current (SHDN = VCC), MAX242/MAX243
µA
figures 5, 6, 11, 19 MAX220 12
3kΩ load both
inputs MAX222/MAX232A/MAX233A/
15
MAX242/MAX243
TA = +25°C 0.1 10
MAX222/ TA = 0°C to +70°C 2 50
Shutdown Supply Current µA
MAX242 TA = -40°C to +85°C 2 50
TA = -55°C to +125°C 35 100
SHDN Input Leakage Current MAX222/MAX242 ±1 µA
SHDN Threshold Low MAX222/MAX242 1.4 0.8 V
SHDN Threshold High MAX222/MAX242 2.0 1.4 V
CL = 50pF to MAX222/MAX232A/MAX233/
2500pF, RL = 3kΩ MAX242/MAX243 6 12 30
to 7kΩ, VCC = 5V,
Transition Slew Rate V/µs
TA = +25°C,
measured from MAX220 1.5 3 30.0
+3V to -3V or -3V
MAX222/MAX232A/MAX233/
1.3 3.5
tPHLT MAX242/MAX243
Transmitter Propagation Delay TLL to MAX220 4 10
µs
RS-232 (Normal Operation), Figure 1 MAX222/MAX232A/MAX233/
1.5 3.5
tPLHT MAX242/MAX243
MAX220 5 10
Note 4: MAX243 R2OUT is guaranteed to be low when R2IN is ≥ 0V or is floating.
_______________________________________________________________________________________ 3
Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX220/222/232A/233A/242/243 (continued)
MAX220–MAX249

0.5 1
tPHLR MAX242/MAX243
Receiver Propagation Delay RS-232 to MAX220 0.6 3
µs
TLL (Normal Operation), Figure 2 MAX222/MAX232A/MAX233/
0.6 1
tPLHR MAX242/MAX243
MAX220 0.8 3
tPHLS MAX242 0.5 10

Receiver Propagation Delay RS-232 to
µs
TLL (Shutdown), Figure 2
tPHLS MAX242 2.5 10
Receiver-Output Enable Time, Figure 3 tER MAX242 125 500 ns

Receiver-Output Disable Time, Figure 3 tDR MAX242 160 500 ns
MAX222/MAX242, 0.1µF
Transmitter-Output Enable Time (SHDN
tET caps (includes charge-pump 250 µs
Goes High), Figure 4
start-up)
Transmitter-Output Disable Time (SHDN MAX222/MAX242,

tDT 600 ns
Goes Low), Figure 4 0.1µF caps
300
Transmitter + to - Propagation Delay MAX242/MAX243
tPHLT - tPLHT ns
Difference (Normal Operation)
MAX220 2000
Receiver + to - Propagation Delay 100
tPHLR - tPLHR MAX242/MAX243 ns
Difference (Normal Operation)
MAX220 225
__________________________________________Typical Operating Characteristics

MAX220/MAX222/MAX232A/MAX233A/MAX242/MAX243
AVAILABLE OUTPUT CURRENT MAX222/MAX242

OUTPUT VOLTAGE vs. LOAD CURRENT vs. DATA RATE ON-TIME EXITING SHUTDOWN
10 11 +10V
MAX220-01
MAX220-02
MAX220-03
1µF V+
8 OUTPUT LOAD CURRENT 1µF CAPS
10 FLOWS FROM V+ TO V-
6 EITHER V+ OR V- LOADED V+
0.1µF CAPS
ALL CAPS +5V
OUTPUT CURRENT (mA)
VCC = ±5V 0.1µF

OUTPUT VOLTAGE (V)
4 9 1µF +5V
V+, V- VOLTAGE (V)
NO LOAD ON SHDN
2 TRANSMITTER OUTPUTS VCC = +5.25V 0V
8
(EXCEPT MAX220, MAX233A)
0 0V
ALL CAPS
-2 V- LOADED, NO LOAD ON V+ 7 0.1µF
VCC = +4.75V 1µF CAPS
-4 0.1µF 1µF
6
-6
5 0.1µF CAPS
-8 V- V-
V+ LOADED, NO LOAD ON V-
-10 4 -10V
0 5 10 15 20 25 0 10 20 30 40 50 60 500µs/div
LOAD CURRENT (mA) DATA RATE (kbits/sec)
4 _______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
ABSOLUTE MAXIMUM RATINGS—MAX223/MAX230–MAX241
VCC ...........................................................................-0.3V to +6V 20-Pin Wide SO (derate 10 00mW/°C above +70°C).......800mW
V+ ................................................................(VCC - 0.3V) to +14V 24-Pin Wide SO (derate 11.76mW/°C above +70°C).......941mW
V- ............................................................................+0.3V to -14V 28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W
Input Voltages 44-Pin Plastic FP (derate 11.11mW/°C above +70°C) .....889mW
TIN ............................................................-0.3V to (VCC + 0.3V) 14-Pin CERDIP (derate 9.09mW/°C above +70°C) ..........727mW
RIN......................................................................................±30V 16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW
Output Voltages 20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW
TOUT ...................................................(V+ + 0.3V) to (V- - 0.3V) 24-Pin Narrow CERDIP
ROUT .........................................................-0.3V to (VCC + 0.3V) (derate 12.50mW/°C above +70°C) ..............1W
Short-Circuit Duration, TOUT ......................................Continuous 24-Pin Sidebraze (derate 20.0mW/°C above +70°C)..........1.6W
Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.52mW/°C above +70°C).............762mW
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)....800mW Operating Temperature Ranges
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW MAX2 _ _ C _ _......................................................0°C to +70°C
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW MAX2 _ _ E _ _ ...................................................-40°C to +85°C
24-Pin Narrow Plastic DIP MAX2 _ _ M _ _ ...............................................-55°C to +125°C
(derate 13.33mW/°C above +70°C) ..........1.07W Storage Temperature Range .............................-65°C to +160°C
24-Pin Plastic DIP (derate 9.09mW/°C above +70°C)......500mW Lead Temperature (soldering, 10s) (Note 4) ...................+300°C
16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW
Note 4: Maximum reflow temperature for the MAX233/MAX235 is +225°C.
ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,
VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)
Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±7.3 V
MAX232/233 5 10
No load,
VCC Power-Supply Current MAX223/230/234–238/240/241 7 15 mA
TA = +25°C
MAX231/239 0.4 1
MAX231 1.8 5
V+ Power-Supply Current mA
MAX239 5 15
MAX223 15 50
Shutdown Supply Current TA = +25°C µA
MAX230/235/236/240/241 1 10
Input Logic Threshold Low TIN; EN, SHDN (MAX233); EN, SHDN (MAX230/235–241) 0.8 V
TIN 2.0
Input Logic Threshold High EN, SHDN (MAX223); V
2.4
EN, SHDN (MAX230/235/236/240/241)
Logic Pull-Up Current TIN = 0V 1.5 200 µA
Receiver Input Voltage
-30 +30 V
Operating Range
_______________________________________________________________________________________ 5
Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX223/MAX230–MAX241 (continued)
MAX220–MAX249
(MAX223/230/232/234/236/237/238/240/241, VCC = +5V ±10; MAX233/MAX235, VCC = 5V ±5%‚ C1–C4 = 1.0µF; MAX231/MAX239,
VCC = 5V ±10%; V+ = 7.5V to 13.2V; TA = TMIN to TMAX; unless otherwise noted.)
Normal operation
SHDN = 5V (MAX223) 0.8 1.2
TA = +25°C, SHDN = 0V (MAX235/236/240/241)
RS-232 Input Threshold Low V
VCC = 5V Shutdown (MAX223)
SHDN = 0V, 0.6 1.5
EN = 5V (R4IN, R5IN)
Normal operation
SHDN = 5V (MAX223) 1.7 2.4
TA = +25°C, SHDN = 0V (MAX235/236/240/241)
RS-232 Input Threshold High V
VCC = 5V Shutdown (MAX223)
SHDN = 0V, 1.5 2.4
EN = 5V (R4IN‚ R5IN)
RS-232 Input Hysteresis VCC = 5V, no hysteresis in shutdown 0.2 0.5 1.0 V
RS-232 Input Resistance TA = +25°C, VCC = 5V 3 5 7 kΩ
TTL/CMOS Output Voltage Low IOUT = 1.6mA (MAX231/232/233, IOUT = 3.2mA) 0.4 V
TTL/CMOS Output Voltage High IOUT = -1mA 3.5 VCC - 0.4 V
0V ≤ ROUT ≤ VCC; EN = 0V (MAX223);
TTL/CMOS Output Leakage Current 0.05 ±10 µA
EN = VCC (MAX235–241 )
Normal MAX223 600

Receiver Output Enable Time ns
operation MAX235/236/239/240/241 400
Normal MAX223 900

Receiver Output Disable Time ns
operation MAX235/236/239/240/241 250
Normal operation 0.5 10
RS-232 IN to
Propagation Delay TTL/CMOS OUT, SHDN = 0V tPHLS 4 40 µs
CL = 150pF (MAX223) tPLHS 6 40
MAX223/MAX230/MAX234–241, TA = +25°C, VCC = 5V,
RL = 3kΩ to 7kΩ‚ CL = 50pF to 2500pF, measured from 3 5.1 30
+3V to -3V or -3V to +3V
Transition Region Slew Rate V/µs
MAX231/MAX232/MAX233, TA = +25°C, VCC = 5V,
RL = 3kΩ to 7kΩ, CL = 50pF to 2500pF, measured from 4 30
+3V to -3V or -3V to +3V
Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 Ω
Transmitter Output Short-Circuit

±10 mA
Current mA
6 _______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
MAX223/MAX230–MAX241
TRANSMITTER OUTPUT VOLTAGE (VOH)
TRANSMITTER OUTPUT vs. LOAD CAPACITANCE AT TRANSMITTER SLEW RATE
VOLTAGE (VOH) vs. VCC DIFFERENT DATA RATES vs. LOAD CAPACITANCE
8.5 7.4 12.0
MAX220-04
MAX220-06
MAX220-05
1 TRANSMITTER LOADED TA = +25°C
2 TRANSMITTERS
LOADED 7.2 11.0 VCC = +5V
LOADED, RL = 3kΩ
8.0 10.0 C1–C4 = 1µF
7.0
SLEW RATE (V/µs)

1 TRANSMITTER 9.0 2 TRANSMITTERS
VOH (V)
6.8
VOH (V)
LOADED 160kbits/sec LOADED

7.5 3 TRANS- 8.0
80kbits/sec
MITTERS 6.6 20kbits/sec
LOADED 7.0
TA = +25°C 6.4 TA = +25°C 3 TRANSMITTERS
7.0 C1–C4 = 1µF VCC = +5V 6.0
LOADED
TRANSMITTER 3 TRANSMITTERS LOADED
6.2 5.0 4 TRANSMITTERS
4 TRANSMITTERS LOADS = RL = 3kΩ
LOADED
LOADED 3kΩ || 2500pF C1–C4 = 1µF
6.5 6.0 4.0
4.5 5.0 5.5 0 500 1000 1500 2000 2500 0 500 1000 1500 2000 2500
VCC (V) LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (VOL)

TRANSMITTER OUTPUT vs. LOAD CAPACITANCE AT TRANSMITTER OUTPUT VOLTAGE (V+, V-)
VOLTAGE (VOL) vs. VCC DIFFERENT DATA RATES vs. LOAD CURRENT
-6.0 -6.0 10
MAX220-09
MAX220-08
MAX220-07
4 TRANS- TA = +25°C TA = +25°C

MITTERS C1–C4 = 1µF -6.2 8
-6.5 VCC = +5V
LOADED TRANSMITTER 3 TRANSMITTERS LOADED 6 TA = +25°C
LOADS = -6.4 RL = 3kΩ VCC = +5V
3kΩ || 2500pF 4
-7.0 C1–C4 = 1µF C1–C4 = 1µF
-6.6 2
V+, V- (V)
V- LOADED,
VOL (V)
VOL (V)
V+ AND V- V+ LOADED,
160kbits/sec NO LOAD
-7.5 -6.8 0 EQUALLY
80kbits/sec ON V+ NO LOAD
1 TRANS- -2 LOADED ON V-
-7.0 20Kkbits/sec
-8.0 MITTER
LOADED -4
-7.2
2 TRANS- 3 TRANS- -6
-8.5
MITTERS MITTERS -7.4
-8
LOADED LOADED ALL TRANSMITTERS UNLOADED
-9.0 -7.6 -10
4.5 5.0 5.5 0 500 1000 1500 2000 2500 0 5 10 15 20 25 30 35 40 45 50
VCC (V) LOAD CAPACITANCE (pF) CURRENT (mA)
V+, V- WHEN EXITING SHUTDOWN

(1µF CAPACITORS)
MAX220-13
V+
V-
SHDN*
500ms/div
*SHUTDOWN POLARITY IS REVERSED
FOR NON MAX241 PARTS
_______________________________________________________________________________________ 7
Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS—MAX225/MAX244–MAX249
MAX220–MAX249
Supply Voltage (VCC) ...............................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)
Input Voltages 28-Pin Wide SO (derate 12.50mW/°C above +70°C) .............1W
TIN‚ ENA, ENB, ENR, ENT, ENRA, 40-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ...611mW
ENRB, ENTA, ENTB..................................-0.3V to (VCC + 0.3V) 44-Pin PLCC (derate 13.33mW/°C above +70°C) ...........1.07W
RIN .....................................................................................±25V Operating Temperature Ranges
TOUT (Note 5).....................................................................±15V MAX225C_ _, MAX24_C_ _ ..................................0°C to +70°C
ROUT ........................................................-0.3V to (VCC + 0.3V) MAX225E_ _, MAX24_E_ _ ...............................-40°C to +85°C
Short Circuit (one output at a time) Storage Temperature Range .............................-65°C to +160°C
TOUT to GND ............................................................Continuous Lead Temperature (soldering,10s) (Note 6) ....................+300°C
ROUT to GND............................................................Continuous
Note 5: Input voltage measured with transmitter output in a high-impedance state, shutdown, or VCC = 0V.
Note 6: Maximum reflow temperature for the MAX225/MAX245/MAX246/MAX247 is +225°C.
ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249
(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-
erwise noted.)
RS-232 TRANSMITTERS
Input Logic Threshold Low 1.4 0.8 V
Input Logic Threshold High 2 1.4 V
Normal operation 10 50
Logic Pull-Up/lnput Current Tables 1a–1d µA
Shutdown ±0.01 ±1
Data Rate Tables 1a–1d, normal operation 120 64 kbps
Output Voltage Swing All transmitter outputs loaded with 3kΩ to GND ±5 ±7.5 V
ENA, ENB, ENT, ENTA, ENTB =
±0.01 ±25
VCC, VOUT = ±15V
Output Leakage Current (Shutdown) Tables 1a–1d µA
VCC = 0V,
±0.01 ±25
VOUT = ±15V
Transmitter Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V (Note 7) 300 10M Ω
Output Short-Circuit Current VOUT = 0V ±7 ±30 mA
RS-232 RECEIVERS
RS-232 Input Voltage Operating Range ±25 V
RS-232 Input Threshold Low VCC = 5V 0.8 1.3 V
RS-232 Input Threshold High VCC = 5V 1.8 2.4 V
RS-232 Input Hysteresis VCC = 5V 0.2 0.5 1.0 V
RS-232 Input Resistance 3 5 7 kΩ
TTL/CMOS Output Voltage Low IOUT = 3.2mA 0.2 0.4 V
TTL/CMOS Output Voltage High IOUT = -1.0mA 3.5 VCC - 0.2 V
Sourcing VOUT = GND -2 -10
TTL/CMOS Output Short-Circuit Current mA
Shrinking VOUT = VCC 10 30
Normal operation, outputs disabled,
TTL/CMOS Output Leakage Current ±0.05 ±0.10 µA
Tables 1a–1d, 0V ≤ VOUT ≤ VCC, ENR_ = VCC
8 _______________________________________________________________________________________
Drivers/Receivers
ELECTRICAL CHARACTERISTICS—MAX225/MAX244–MAX249 (continued)
MAX220–MAX249
(MAX225, VCC = 5.0V ±5%; MAX244–MAX249, VCC = +5.0V ±10%, external capacitors C1–C4 = 1µF; TA = TMIN to TMAX; unless oth-
erwise noted.)
POWER SUPPLY AND CONTROL LOGIC
MAX225 4.75 5.25
Operating Supply Voltage V
MAX244–MAX249 4.5 5.5
MAX225 10 20
No load
VCC Supply Current MAX244–MAX249 11 30
mA
(Normal Operation) 3kΩ loads on MAX225 40
all outputs MAX244–MAX249 57
TA = +25°C 8 25
Shutdown Supply Current µA
TA = TMIN to TMAX 50
Leakage current ±1 µA
Control Input Threshold low 1.4 0.8
V
Threshold high 2.4 1.4
AC CHARACTERISTICS
CL = 50pF to 2500pF, RL = 3kΩ to 7kΩ, VCC = 5V,
Transition Slew Rate 5 10 30 V/µs
TA = +25°C, measured from +3V to -3V or -3V to +3V
Transmitter Propagation Delay tPHLT 1.3 3.5

TLL to RS-232 (Normal Operation), µs
Figure 1 tPLHT 1.5 3.5
Receiver Propagation Delay tPHLR 0.6 1.5

TLL to RS-232 (Normal Operation), µs
Figure 2 tPLHR 0.6 1.5
Receiver Propagation Delay tPHLS 0.6 10

TLL to RS-232 (Low-Power Mode), µs
Figure 2 tPLHS 3.0 10
Transmitter + to - Propagation
tPHLT - tPLHT 350 ns
Delay Difference (Normal Operation)
Receiver + to - Propagation
tPHLR - tPLHR 350 ns
Delay Difference (Normal Operation)
Receiver-Output Enable Time, Figure 3 tER 100 500 ns
Receiver-Output Disable Time, Figure 3 tDR 100 500 ns
MAX246–MAX249
5 µs
(excludes charge-pump startup)
Transmitter Enable Time tET
10 ms
(includes charge-pump startup)
Transmitter Disable Time, Figure 4 tDT 100 ns
Note 7: The 300Ω minimum specification complies with EIA/TIA-232E, but the actual resistance when in shutdown mode or VCC =
0V is 10MΩ as is implied by the leakage specification.
_______________________________________________________________________________________ 9
Drivers/Receivers
MAX220–MAX249

TRANSMITTER OUTPUT VOLTAGE (V+, V-)

TRANSMITTER SLEW RATE OUTPUT VOLTAGE vs. LOAD CAPACITANCE AT
vs. LOAD CAPACITANCE vs. LOAD CURRENT FOR V+ AND V- DIFFERENT DATA RATES
18 10 9.0
MAX220-10
MAX220-11
MAX220-12
VCC = 5V VCC = 5V WITH ALL TRANSMITTERS DRIVEN
8 LOADED WITH 5kΩ
16 V+ AND V- LOADED 8.5
TRANSMITTER SLEW RATE (V/µs)
6 EITHER V+ OR 10kb/sec
14 8.0 20kb/sec
V- LOADED
OUTPUT VOLTAGE (V)
EXTERNAL POWER SUPPLY 4 VCC = 5V

12 1µF CAPACITORS 2 EXTERNAL CHARGE PUMP 7.5 40kb/sec
V+, V (V)
1µF CAPACITORS
10 0 8 TRANSMITTERS 7.0 60kb/sec
40kb/s DATA RATE DRIVING 5kΩ AND
8 8 TRANSMITTERS -2
2000pF AT 20kbits/sec 6.5
LOADED WITH 3kΩ -4 V- LOADED
6 6.0 100kb/sec
-6 V+ AND V- LOADED
200kb/sec
4 5.5
-8
V+ LOADED ALL CAPACITIORS 1µF
2 -10 5.0
0 1 2 3 4 5 0 5 10 15 20 25 30 35 0 1 2 3 4 5
LOAD CAPACITANCE (nF) LOAD CURRENT (mA) LOAD CAPACITANCE (nF)
10 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+3V
0V* 50% 50%
+3V INPUT
INPUT
0V
VCC
OUTPUT 50% 50%
V+ GND
OUTPUT 0V
V-
tPHLR tPLHR
tPHLS tPLHS
tPLHT tPHLT
*EXCEPT FOR R2 ON THE MAX243

WHERE -3V IS USED.
Figure 1. Transmitter Propagation-Delay Timing Figure 2. Receiver Propagation-Delay Timing
EN
RX OUT 1kΩ
RX IN RX VCC - 2V
+3V
SHDN
a) TEST CIRCUIT 0V
150pF
+3V OUTPUT DISABLE TIME (tDT)
EN INPUT V+
0V +5V
EN
OUTPUT ENABLE TIME (tER) 0V
+3.5V -5V
RECEIVER V-
OUTPUTS
+0.8V
a) TIMING DIAGRAM
b) ENABLE TIMING
+3V
EN
0V 1 OR 0 TX
EN INPUT
OUTPUT DISABLE TIME (tDR) 3kΩ 50pF
VOH
VOH - 0.5V
RECEIVER VCC - 2V
OUTPUTS
VOL + 0.5V b) TEST CIRCUIT
VOL
c) DISABLE TIMING
Figure 3. Receiver-Output Enable and Disable Timing Figure 4. Transmitter-Output Disable Timing
______________________________________________________________________________________ 11
Drivers/Receivers
Table 1a. MAX245 Control Pin Configurations
MAX220–MAX249
ENT ENR OPERATION STATUS TRANSMITTERS RECEIVERS

0 0 Normal Operation All Active All Active
0 1 Normal Operation All Active All 3-State
1 0 Shutdown All 3-State All Low-Power Receive Mode
1 1 Shutdown All 3-State All 3-State
Table 1b. MAX245 Control Pin Configurations

OPERATION TRANSMITTERS RECEIVERS
ENT ENR
STATUS TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5
0 0 Normal Operation All Active All Active All Active All Active
RA1–RA4 3-State, RB1–RB4 3-State,
0 1 Normal Operation All Active All Active
RA5 Active RB5 Active
All Low-Power All Low-Power

1 0 Shutdown All 3-State All 3-State
Receive Mode Receive Mode

1 1 Shutdown All 3-State All 3-State RA5 Low-Power RB5 Low-Power
Table 1c. MAX246 Control Pin Configurations

OPERATION TRANSMITTERS RECEIVERS
ENA ENB
STATUS TA1–TA4 TB1–TB4 RA1–RA5 RB1–RB5
0 0 Normal Operation All Active All Active All Active All Active
RB1–RB4 3-State,
0 1 Normal Operation All Active All 3-State All Active
RB5 Active
RA1–RA4 3-State,
1 0 Shutdown All 3-State All Active All Active
RA5 Active

1 1 Shutdown All 3-State All 3-State RA5 Low-Power RA5 Low-Power
12 ______________________________________________________________________________________
Drivers/Receivers
Table 1d. MAX247/MAX248/MAX249 Control Pin Configurations
MAX220–MAX249
TRANSMITTERS RECEIVERS
OPERATION MAX247 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB5
ENTA ENTB ENRA ENRB
STATUS MAX248 TA1–TA4 TB1–TB4 RA1–RA4 RB1–RB4
MAX249 TA1–TA3 TB1–TB3 RA1–RA5 RB1–RB5
0 0 0 0 Normal Operation All Active All Active All Active All Active
All 3-State, except
0 0 0 1 Normal Operation All Active All Active All Active RB5 stays active on
MAX247
0 0 1 0 Normal Operation All Active All Active All 3-State All Active
All 3-State, except
0 0 1 1 Normal Operation All Active All Active All 3-State RB5 stays active on
MAX247
0 1 0 0 Normal Operation All Active All 3-State All Active All Active
All 3-State, except
0 1 0 1 Normal Operation All Active All 3-State All Active RB5 stays active on
MAX247
0 1 1 0 Normal Operation All Active All 3-State All 3-State All Active
All 3-State, except
0 1 1 1 Normal Operation All Active All 3-State All 3-State RB5 stays active on
MAX247
1 0 0 0 Normal Operation All 3-State All Active All Active All Active
All 3-State, except
1 0 0 1 Normal Operation All 3-State All Active All Active RB5 stays active on
MAX247
1 0 1 0 Normal Operation All 3-State All Active All 3-State All Active
All 3-State, except
1 0 1 1 Normal Operation All 3-State All Active All 3-State RB5 stays active on
MAX247
Low-Power Low-Power
1 1 0 0 Shutdown All 3-State All 3-State
All 3-State, except

Low-Power
1 1 0 1 Shutdown All 3-State All 3-State RB5 stays active on
Receive Mode
MAX247
Low-Power
1 1 1 0 Shutdown All 3-State All 3-State All 3-State
Receive Mode
All 3-State, except

1 1 1 1 Shutdown All 3-State All 3-State All 3-State RB5 stays active on
MAX247
______________________________________________________________________________________ 13
Drivers/Receivers
_______________Detailed Description mode, in three-state mode, or when device power is
MAX220–MAX249
removed. Outputs can be driven to ±15V. The power-

The MAX220–MAX249 contain four sections: dual
supply current typically drops to 8µA in shutdown mode.
charge-pump DC-DC voltage converters, RS-232 dri-
The MAX220 does not have pull-up resistors to force the
vers, RS-232 receivers, and receiver and transmitter
outputs of the unused drivers low. Connect unused
enable control inputs.
inputs to GND or VCC.
Dual Charge-Pump Voltage Converter The MAX239 has a receiver three-state control line, and
The MAX220–MAX249 have two internal charge-pumps the MAX223, MAX225, MAX235, MAX236, MAX240,
that convert +5V to ±10V (unloaded) for RS-232 driver and MAX241 have both a receiver three-state control
operation. The first converter uses capacitor C1 to dou- line and a low-power shutdown control. Table 2 shows
ble the +5V input to +10V on C3 at the V+ output. The the effects of the shutdown control and receiver three-
second converter uses capacitor C2 to invert +10V to state control on the receiver outputs.
-10V on C4 at the V- output. The receiver TTL/CMOS outputs are in a high-imped-
A small amount of power may be drawn from the +10V ance, three-state mode whenever the three-state enable
(V+) and -10V (V-) outputs to power external circuitry line is high (for the MAX225/MAX235/MAX236/MAX239–
(see the Typical Operating Characteristics section), MAX241), and are also high-impedance whenever the
except on the MAX225 and MAX245–MAX247, where shutdown control line is high.
these pins are not available. V+ and V- are not regulated, When in low-power shutdown mode, the driver outputs
so the output voltage drops with increasing load current. are turned off and their leakage current is less than 1µA
Do not load V+ and V- to a point that violates the mini- with the driver output pulled to ground. The driver output
mum ±5V EIA/TIA-232E driver output voltage when leakage remains less than 1µA, even if the transmitter
sourcing current from V+ and V- to external circuitry. output is backdriven between 0V and (VCC + 6V). Below
When using the shutdown feature in the MAX222, -0.5V, the transmitter is diode clamped to ground with
MAX225, MAX230, MAX235, MAX236, MAX240, 1kΩ series impedance. The transmitter is also zener
MAX241, and MAX245–MAX249, avoid using V+ and V- clamped to approximately V CC + 6V, with a series
to power external circuitry. When these parts are shut impedance of 1kΩ.
down, V- falls to 0V, and V+ falls to +5V. For applica- The driver output slew rate is limited to less than 30V/µs
tions where a +10V external supply is applied to the V+ as required by the EIA/TIA-232E and V.28 specifica-
pin (instead of using the internal charge pump to gen- tions. Typical slew rates are 24V/µs unloaded and
erate +10V), the C1 capacitor must not be installed and 10V/µs loaded with 3Ω and 2500pF.
the SHDN pin must be tied to VCC. This is because V+
is internally connected to VCC in shutdown mode. RS-232 Receivers
EIA/TIA-232E and V.28 specifications define a voltage
RS-232 Drivers level greater than 3V as a logic 0, so all receivers invert.
The typical driver output voltage swing is ±8V when Input thresholds are set at 0.8V and 2.4V, so receivers
loaded with a nominal 5kΩ RS-232 receiver and VCC = respond to TTL level inputs as well as EIA/TIA-232E and
+5V. Output swing is guaranteed to meet the EIA/TIA- V.28 levels.
232E and V.28 specification, which calls for ±5V mini-
mum driver output levels under worst-case conditions. The receiver inputs withstand an input overvoltage up
These include a minimum 3kΩ load, VCC = +4.5V, and to ±25V and provide input terminating resistors with
maximum operating temperature. Unloaded driver out-
put voltage ranges from (V+ -1.3V) to (V- +0.5V). Table 2. Three-State Control of Receivers
Input thresholds are both TTL and CMOS compatible. PART SHDN SHDN EN EN(R) RECEIVERS
The inputs of unused drivers can be left unconnected
since 400kΩ input pull-up resistors to VCC are built in Low X High Impedance
(except for the MAX220). The pull-up resistors force the MAX223 __ High Low __ Active
High High High Impedance
outputs of unused drivers low because all drivers invert.
The internal input pull-up resistors typically source 12µA, Low High Impedance
MAX225 __ __ __
except in shutdown mode where the pull-ups are dis- High Active
abled. Driver outputs turn off and enter a high-imped- MAX235 Low Low High Impedance
ance state—where leakage current is typically MAX236 Low __ __ High Active
microamperes (maximum 25µA)—when in shutdown MAX240 High X High Impedance
14 ______________________________________________________________________________________
Drivers/Receivers
nominal 5kΩ values. The receivers implement Type 1 Shutdown—MAX222–MAX242
MAX220–MAX249
interpretation of the fault conditions of V.28 and On the MAX222‚ MAX235‚ MAX236‚ MAX240‚ and
EIA/TIA-232E. MAX241‚ all receivers are disabled during shutdown.
The receiver input hysteresis is typically 0.5V with a On the MAX223 and MAX242‚ two receivers continue to
guaranteed minimum of 0.2V. This produces clear out- operate in a reduced power mode when the chip is in
put transitions with slow-moving input signals, even shutdown. Under these conditions‚ the propagation
with moderate amounts of noise and ringing. The delay increases to about 2.5µs for a high-to-low input
receiver propagation delay is typically 600ns and is transition. When in shutdown, the receiver acts as a
independent of input swing direction. CMOS inverter with no hysteresis. The MAX223 and
MAX242 also have a receiver output enable input (EN
Low-Power Receive Mode for the MAX242 and EN for the MAX223) that allows
The low-power receive-mode feature of the MAX223, receiver output control independent of SHDN (SHDN
MAX242, and MAX245–MAX249 puts the IC into shut- for MAX241). With all other devices‚ SHDN (SHDN for
down mode but still allows it to receive information. This MAX241) also disables the receiver outputs.
is important for applications where systems are periodi- The MAX225 provides five transmitters and five
cally awakened to look for activity. Using low-power receivers‚ while the MAX245 provides ten receivers and
receive mode, the system can still receive a signal that eight transmitters. Both devices have separate receiver
will activate it on command and prepare it for communi- and transmitter-enable controls. The charge pumps
cation at faster data rates. This operation conserves turn off and the devices shut down when a logic high is
system power. applied to the ENT input. In this state, the supply cur-
Negative Threshold—MAX243 rent drops to less than 25µA and the receivers continue
The MAX243 is pin compatible with the MAX232A, differ- to operate in a low-power receive mode. Driver outputs
ing only in that RS-232 cable fault protection is removed enter a high-impedance state (three-state mode). On
on one of the two receiver inputs. This means that control the MAX225‚ all five receivers are controlled by the
lines such as CTS and RTS can either be driven or left ENR input. On the MAX245‚ eight of the receiver out-
floating without interrupting communication. Different puts are controlled by the ENR input‚ while the remain-
cables are not needed to interface with different pieces of ing two receivers (RA5 and RB5) are always active.
equipment. RA1–RA4 and RB1–RB4 are put in a three-state mode
when ENR is a logic high.
The input threshold of the receiver without cable fault
protection is -0.8V rather than +1.4V. Its output goes Receiver and Transmitter Enable
positive only if the input is connected to a control line Control Inputs
that is actively driven negative. If not driven, it defaults The MAX225 and MAX245–MAX249 feature transmitter
to the 0 or “OK to send” state. Normally‚ the MAX243’s and receiver enable controls.
other receiver (+1.4V threshold) is used for the data line The receivers have three modes of operation: full-speed
(TD or RD)‚ while the negative threshold receiver is con- receive (normal active)‚ three-state (disabled)‚ and low-
nected to the control line (DTR‚ DTS‚ CTS‚ RTS, etc.). power receive (enabled receivers continue to function
Other members of the RS-232 family implement the at lower data rates). The receiver enable inputs control
optional cable fault protection as specified by EIA/TIA- the full-speed receive and three-state modes. The
232E specifications. This means a receiver output goes transmitters have two modes of operation: full-speed
high whenever its input is driven negative‚ left floating‚ transmit (normal active) and three-state (disabled). The
or shorted to ground. The high output tells the serial transmitter enable inputs also control the shutdown
communications IC to stop sending data. To avoid this‚ mode. The device enters shutdown mode when all
the control lines must either be driven or connected transmitters are disabled. Enabled receivers function in
with jumpers to an appropriate positive voltage level. the low-power receive mode when in shutdown.
______________________________________________________________________________________ 15
Drivers/Receivers
Tables 1a–1d define the control states. The MAX244 The MAX249 provides ten receivers and six drivers with
MAX220–MAX249
has no control pins and is not included in these tables. four control pins. The ENRA and ENRB receiver enable
The MAX246 has ten receivers and eight drivers with inputs each control five receiver outputs. The ENTA
two control pins, each controlling one side of the and ENTB transmitter enable inputs control three dri-
device. A logic high at the A-side control input (ENA) vers each. There is no always-active receiver. The
causes the four A-side receivers and drivers to go into device enters shutdown mode and transmitters go into
a three-state mode. Similarly, the B-side control input a three-state mode with a logic high on both ENTA and
(ENB) causes the four B-side drivers and receivers to ENTB. In shutdown mode, active receivers operate in a
go into a three-state mode. As in the MAX245, one A- low-power receive mode at data rates up to 20kb/s.
side and one B-side receiver (RA5 and RB5) remain __________Applications Information
active at all times. The entire device is put into shut-
down mode when both the A and B sides are disabled Figures 5 through 25 show pin configurations and typi-
(ENA = ENB = +5V). cal operating circuits. In applications that are sensitive
to power-supply noise, VCC should be decoupled to
The MAX247 provides nine receivers and eight drivers ground with a capacitor of the same value as C1 and
with four control pins. The ENRA and ENRB receiver C2 connected as close as possible to the device.
enable inputs each control four receiver outputs. The
ENTA and ENTB transmitter enable inputs each control
four drivers. The ninth receiver (RB5) is always active.
The device enters shutdown mode with a logic high on
both ENTA and ENTB.
The MAX248 provides eight receivers and eight drivers
with four control pins. The ENRA and ENRB receiver
enable inputs each control four receiver outputs. The
ENTA and ENTB transmitter enable inputs control four
drivers each. This part does not have an always-active
receiver. The device enters shutdown mode and trans-
mitters go into a three-state mode with a logic high on
both ENTA and ENTB.
16 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+5V INPUT C3
TOP VIEW
C5
16
1 VCC
C1+ 1 16 VCC C1+ V+ 2 +10V
C1 +5V TO +10V
V+ 2 3 C1-
15 GND VOLTAGE DOUBLER
4
C1- 3 C2+ +10V TO -10V 6 -10V
14 T1OUT C2 5 C2- VOLTAGE INVERTER
V-
C4
C2+ 4 MAX220 13 R1IN
+5V
MAX232
C2- 5 MAX232A 12 R1OUT 400kΩ
V- 6 11 T1IN T1OUT 14
11 T1IN
+5V
T2OUT 7 10 T2IN TTL/CMOS RS-232
INPUTS 400kΩ OUTPUTS
R2IN 8 9 R2OUT 10 T2IN T2OUT 7
DIP/SO 12 R1OUT R1IN 13
CAPACITANCE (µF) TTL/CMOS 5kΩ RS-232

OUTPUTS INPUTS
DEVICE C1 C2 C3 C4 C5
9 R2OUT R2IN 8
MAX220 0.047 0.33 0.33 0.33 0.33
MAX232 1.0 1.0 1.0 1.0 1.0
MAX232A 0.1 0.1 0.1 0.1 0.1 5kΩ
GND
15
Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit
+5V INPUT C3
TOP VIEW ALL CAPACITORS = 0.1µF
C5
17
2 VCC 3 +10V
C1+ +5V TO +10V
C1 V+
(N.C.) EN 1 4 C1- VOLTAGE DOUBLER
20 SHDN
5
(N.C.) EN 1 C1+ 2 C2+ 7 -10V
18 SHDN 19 VCC
C2 +10V TO -10V V-
6 C2- C4
VOLTAGE INVERTER
C1+ 2 17 VCC V+ 3 18 GND
V+ 3 C1- 4 +5V
16 GND 17 T1OUT (EXCEPT MAX220)
400kΩ
C1- 4 15 T1OUT C2+ 5 MAX222 16 N.C.
MAX242 12 T1IN T1OUT 15
C2+ 5 MAX222 14 R1IN C2- 6 15 R1IN +5V
MAX242 TTL/CMOS RS-232
V- 7 400kΩ (EXCEPT MAX220)
C2- 6 13 R1OUT 14 R1OUT INPUTS OUTPUTS
11 T2IN T2OUT 8
V- 7 12 T1IN T2OUT 8 13 N.C.
T2OUT 8 11 T2IN R2IN 9 12 T1IN 13 R1OUT R1IN 14
R2IN 9 10 R2OUT R2OUT 10 11 T2IN
TTL/CMOS 5kΩ RS-232
OUTPUTS INPUTS
SSOP
1 (N.C.) EN 5kΩ
( ) ARE FOR MAX222 ONLY. 18
GND SHDN
PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY.
16
Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit
______________________________________________________________________________________ 17
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
0.1
28 27
+5V VCC VCC
400kΩ
T1IN
3 11
ENR 1 +5V T1OUT
28 VCC
ENR 2 400kΩ
27 VCC
T2IN
T1IN 3 4 12
26 ENT T2OUT
+5V
T2IN 4 25 T3IN 400kΩ
R1OUT 5 MAX225 24 T4IN T3IN
25 18
+5V T3OUT
R2OUT 6 23 T5IN
400kΩ
R3OUT 7 22 R4OUT
T4IN
24 17
R3IN 8 21 R5OUT +5V T4OUT
R2IN 9 20 R5IN 400kΩ
T5IN T5OUT
R1IN 10 19 R4IN 23 16
T1OUT 11 18 T3OUT ENT
26 15
T2OUT 12 17 T4OUT T5OUT
GND 13 16 T5OUT R1OUT R1IN

5 10
GND 14 15 T5OUT
5kΩ
SO R2OUT R2IN
6 9
5kΩ
R3OUT R3IN
7 8
MAX225 FUNCTIONAL DESCRIPTION
5kΩ
5 RECEIVERS
5 TRANSMITTERS R4OUT R4IN
22 19
2 CONTROL PINS
1 RECEIVER ENABLE (ENR) 5kΩ
1 TRANSMITTER ENABLE (ENT)
R5OUT R5IN
21 20
5kΩ
1 ENR
2 ENR
PINS (ENR, GND, VCC, T5OUT) ARE INTERNALLY CONNECTED. GND GND
CONNECT EITHER OR BOTH EXTERNALLY. T5OUT IS A SINGLE DRIVER. 13 14
Figure 7. MAX225 Pin Configuration and Typical Operating Circuit
18 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW 1.0µF
11
12 1.0µF
C1+ VCC 13
1.0µF 14 +5V TO +10V V+
C1- VOLTAGE DOUBLER
15
C2+ +10V TO -10V 17
1.0µF VOLTAGE INVERTER V-
16 C2-
1.0µF
+5V
400kΩ
7 T1IN T1OUT 2
T1
T3OUT 1 28 T4OUT +5V
T1OUT 2 27 R3IN 400kΩ

6 T2IN T2OUT 3
T2OUT 3 26 R3OUT T2
R2IN 4 25 SHDN (SHDN) +5V

TTL/CMOS RS-232
R2OUT 5 24 EN (EN) INPUTS 400kΩ OUTPUTS
MAX223 20 T3IN T3OUT 1
T2IN 6 MAX241 23 R4IN* T3
T1IN 7 22 R4OUT* +5V
R1OUT 8 21 T4IN 400kΩ

21 T4IN T4OUT 28
R1IN 9 20 T3IN T4
GND 10 19 R5OUT*
8 R1OUT R1IN 9
VCC 11 18 R5IN* R1
5kΩ
C1+ 12 17 V-
V+ 13 16 C2- R2IN 4
5 R2OUT
R2
C1- 14 15 C2+
5kΩ
Wide SO/
SSOP LOGIC 26 R3OUT R3IN 27 RS-232
R3
OUTPUTS INPUTS
5kΩ
22 R4OUT R4IN 23
R4
5kΩ
19 R5OUT R5IN 18
R5
*R4 AND R5 IN MAX223 REMAIN ACTIVE IN SHUTDOWN 5kΩ
NOTE: PIN LABELS IN ( ) ARE FOR MAX241 24 EN (EN) SHDN 25
(SHDN)
GND
10
Figure 8. MAX223/MAX241 Pin Configuration and Typical Operating Circuit
______________________________________________________________________________________ 19
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW 1.0µF
7 1.0µF
8 C1+ VCC
V+ 9
1.0µF 10 C1- +5V TO +10V
VOLTAGE DOUBLER
T3OUT 1 20 T4OUT 11
C2+ +10V TO -10V 13
1.0µF 12 V-
T1OUT 2 19 T5IN C2- VOLTAGE INVERTER
1.0µF
T2OUT 3 18 N.C. +5V
400kΩ
T2IN 4 17 SHDN 5 T1IN T1OUT 2
T1
T1IN 5 MAX230 16 T5OUT +5V
400kΩ
GND 6 15 T4IN 4 T2IN T2OUT 3
T2
VCC 7 14 T3IN +5V
400kΩ
C1+ 8 13 V-
TTL/CMOS 14 T3IN T3OUT 1 RS-232
T3
V+ 9 12 C2- INPUTS +5V OUTPUTS
400kΩ
C1- 10 11 C2+ 15 T4IN T4OUT 20
T4
+5V
400kΩ
DIP/SO 19 T5IN T5OUT 16
T5
N.C. x 18 GND
17 SHDN
6
+5V INPUT
TOP VIEW 1.0µF +7.5V TO +12V
13 (15)
1 VCC 14 (16)
C1+ V+
1.0µF 2 +12V TO -12V 3
C1- VOLTAGE CONVERTER V-
C2
+5V 1.0µF
C+ 1 14 V+ C+ 1 16 V+
400kΩ
C- 2 13 VCC C- 2 15 VCC (10) (13)
8 T1IN T1OUT 11
T1
V- 3 12 GND V- 3 14 GND +5V
TTL/CMOS RS-232
T2OUT 4 MAX231 11 T1OUT T2OUT 4 MAX231 13 T1OUT INPUTS 400kΩ OUTPUTS
R2IN 5 10 R1IN R2IN 5 12 R1IN 7 T2IN T2OUT 4
T2
R2OUT 6 9 R1OUT R2OUT 6 11 R1OUT
(11) (12)
9 R1OUT R1IN 10
T2IN 7 8 T1IN T2IN 7 10 T1IN R1
N.C. 8 9 N.C. TTL/CMOS 5kΩ RS-232

OUTPUTS INPUTS
DIP
SO 6 R2OUT R2IN 5
R2
5kΩ
GND
PIN NUMBERS IN ( ) ARE FOR SO PACKAGE 12 (14)
Figure 10. MAX231 Pin Configurations and Typical Operating Circuit
20 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+5V INPUT
1.0µF
TOP VIEW 7
+5V VCC
400kΩ
2 T1IN T1OUT 5
T2IN 1 20 R2OUT
+5V
T1IN 2 19 R2IN TTL/CMOS RS-232
INPUTS 400kΩ
R1OUT 3 OUTPUTS
18 T2OUT 1 T2IN T2OUT 18
R1IN 4 17 V-
3 R1OUT R1IN 4
T1OUT 5 MAX233 16 C2-
MAX233A
GND 6 15 C2+ TTL/CMOS 5kΩ RS-232
OUTPUTS INPUTS
VCC 7 14 V+ (C1-)
(V+) C1+ 8 13 C1- (C1+) 20 R2OUT R2IN 19
GND 9 12 V- (C2+) 8 (13) 5kΩ C2+ 11 (12)

DO NOT MAKE C1+
CONNECTIONS TO 13 (14) 15
(V-) CS- 10 11 C2+ (C2-) C1-
THESE PINS C2+
12 (10) 16
INTERNAL -10 V- C2-
DIP/SO POWER SUPPLY 17 V-
10 (11)
C2-
INTERNAL +10V 14 (8) V+
GND GND
POWER SUPPLY
6 9
( ) ARE FOR SO PACKAGE ONLY.
Figure 11. MAX233/MAX233A Pin Configuration and Typical Operating Circuit
+5V INPUT
1.0µF
TOP VIEW
6 1.0µF
7
C1+ VCC 8
+5V TO +10V V+
1.0µF 9
C1- VOLTAGE DOUBLER
10
C2+ +10V TO -10V 12
11 C2- 1.0µF
T1OUT 1 16 T3OUT
+5V
T2OUT 2 15 T4OUT
400kΩ
T2IN 3 14 T4IN 4 T1IN T1OUT 1
T1
T1IN 4 MAX234 13 T3IN +5V
GND 5 12 V- 400kΩ
VCC 6 11 C2- 3 T2IN T2OUT 3
T2
C1+ 7 10 C2+ TTL/CMOS +5V RS-232
V+ 8 9 C1-
13 T3IN T3OUT 16
T3
DIP/SO +5V
400kΩ
14 T4IN T4OUT 15
T4
GND
5
______________________________________________________________________________________ 21
Drivers/Receivers
MAX220–MAX249
+5V INPUT
TOP VIEW 1.0µF
12
VCC
+5V
400kΩ
8 T1IN T1OUT 3
T1
+5V
400kΩ
7 T2IN T2OUT 4
T2
+5V
400kΩ
T3
INPUTS OUTPUTS
T4OUT 1 24 R3IN +5V
400kΩ
T3OUT 2 23 R3OUT T4OUT 1
16 T4IN
T4
T1OUT 3 22 T5IN
+5V
T2OUT 4 21 SHDN 400kΩ
R2IN 5 MAX235 20 EN 22 T5IN T5OUT 19
T5
R2OUT 6 19 T5OUT
T2IN 7 18 R4IN
9 R1OUT R1IN 10
T1
T1IN 8 17 R4OUT
5kΩ
R1OUT 9 16 T4IN
R1IN 10 15 T3IN R2IN 5

6 R2OUT
R2
GND 11 14 R5OUT
5kΩ
VCC 12 13 R5IN
TTL/CMOS 23 R3OUT R3IN 24 RS-232

DIP R3
OUTPUTS INPUTS
5kΩ
17 R4OUT R4IN 18
R4
5kΩ
14 R5OUT R5IN 13
R5
5kΩ
20 EN 21
SHDN
GND
11
22 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
TOP VIEW +5V INPUT
1.0µF
9 1.0µF
10 11
C1+ VCC V+
1.0µF +5V TO +10V
12
C1- VOLTAGE DOUBLER
13 15
C2+ V-
1.0µF +10V TO -10V
14 C2- 1.0µF
VOLTAGE INVERTER
+5V
400kΩ
7 T1IN T1OUT 2
T1
T3OUT 1 24 T4OUT +5V

400kΩ
T1OUT 2 23 R2IN
6 T2IN T2OUT 3
T2OUT 3 22 R2OUT T2
R1IN 4 21 SHDN TTL/CMOS +5V RS-232

R1OUT 5 MAX236 20 EN
18 T3IN T3OUT 1
T2IN 6 19 T4IN T3
T1IN 7 18 T3IN +5V

400kΩ
GND 8 17 R3OUT
19 T4IN T4OUT 24
VCC 9 16 R3IN T4
C1+ 10 15 V-
V+ 11 14 C2- R1IN 4
5 R1OUT
R1
C1- 12 13 C2+
5kΩ
DIP/SO
22 R2OUT R2IN 23 RS-232
TTL/CMOS R2
OUTPUTS INPUTS
5kΩ
17 R3OUT R3IN 16
R3
5kΩ
20 EN 21
SHDN
GND
______________________________________________________________________________________ 23
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V INPUT
1.0µF
9 1.0µF
10 VCC 11
C1+ V+
+5V TO +10V
1.0µF 12 VOLTAGE DOUBLER
C1-
13 15
C2+ V-
1.0µF +10V TO -10V
14 VOLTAGE INVERTER 1.0µF
C2-
+5V
400kΩ
T3OUT 1 24 T4OUT 7 T1IN T1OUT 2

T1
T1OUT 2 23 R2IN +5V
400kΩ
T2OUT 3 22 R2OUT
6 T2IN T2OUT 3
R1IN 4 21 T5IN T2
+5V
R1OUT 5 MAX237 20 T5OUT 400kΩ
T2IN 6 19 T4IN TTL/CMOS 18 T3IN T3OUT 1
T3 RS-232
T1IN 7 18 T3IN INPUTS +5V OUTPUTS
400kΩ
GND 8 17 R3OUT
19 T4IN T4OUT 24
VCC 9 16 R3IN T4
+5V
C1+ 10 15 V-
400kΩ
V+ 11 14 C2-
21 T5IN T5OUT 20
T5
C1- 12 13 C2+

R1
5kΩ
22 R2OUT R2IN 23 RS-232

TTL/CMOS R2
OUTPUTS INPUTS
5kΩ
17 R3OUT R3IN 16
R3
5kΩ
GND
8
24 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
TOP VIEW
+5V INPUT
1.0µF
9 1.0µF
10 VCC 11
C1+ V+
+5V TO +10V
1.0µF 12
C1- VOLTAGE DOUBLER
13
C2+ 15
1.0µF +10V TO -10V V-
14 VOLTAGE INVERTER
C2- 1.0µF
+5V
400kΩ
T2OUT 1 24 T3OUT 5 T1IN T1OUT 2

T1
T1OUT 2 23 R3IN +5V
400kΩ
R2IN 3 22 R3OUT
18 T2IN T2OUT 1
R2OUT 4 21 T4IN T2
+5V
T1IN 5 MAX238 20 T4OUT TTL/CMOS RS-232
INPUTS 400kΩ
OUTPUTS
R1OUT 6 19 T3IN T3OUT 24
19 T3IN
T3
R1IN 7 18 T2IN +5V
GND 8 17 R4OUT 400kΩ
VCC 9 16 R4IN 21 T4IN T4OUT 20

T4
C1+ 10 15 V-
V+ 11 14 C2-
C1- 12 13 C2+ 6 R1OUT R1IN 7

R1
DIP/SO 5kΩ
4 R2OUT R2IN 3
R2

OUTPUTS INPUTS
22 R3OUT R3IN 23
R3
5kΩ
17 R4OUT R4IN 16
R4
5kΩ
GND
8
______________________________________________________________________________________ 25
Drivers/Receivers
MAX220–MAX249
TOP VIEW
7.5V TO 13.2V
+5V INPUT INPUT
1.0µF
4 5
6 VCC V+
C1+ 8
V-
+10V TO -10V
1.0µF 7 1.0µF
C1- VOLTAGE INVERTER
+5V
400kΩ
24 T1IN T1OUT 19
T1
R1OUT 1 24 T1IN +5V
400kΩ
R1IN 2 23 T2IN
TTL/CMOS 23 T2IN T2OUT 20
GND 3 22 R2OUT T2 RS-232
INPUTS OUTPUTS
+5V
VCC 4 21 R2IN
400kΩ
V+ 5 MAX239 20 T2OUT
16 T3IN T3OUT 13
C+ 6 19 T1OUT T3
C- 7 18 R3IN
V- 8 17 R3OUT 1 R1OUT R1IN 2
R1
R5IN 9 16 T3IN
5kΩ
R5OUT 10 15 N.C.
R4OUT 11 14 EN 22 R2OUT R2IN 21

R2
R4IN 12 13 T3OUT
5kΩ
DIP/SO
R3
OUTPUTS INPUTS
5kΩ
11 R4OUT R4IN 12
R4
5kΩ
10 R5OUT R5IN 9
R5
5kΩ
14 EN 15
N.C.
GND
3
26 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+5V INPUT
1.0µF
TOP VIEW
19
25 1.0µF
C1+ VCC 26
1.0µF 27 +5V TO +10V V+
C1- VOLTAGE DOUBLER
28
C2+ +5V TO -10V 30
29 C2- 1.0µF
+5V
400kΩ
15 T1IN T1OUT 7
T1
+5V
400kΩ
14 T2IN T2OUT 8
T2
R3OUT
T2OUT
T1OUT
T3OUT
T4OUT
R2IN
R3IN
N.C.
N.C.
N.C.
T5IN
+5V
400kΩ

T3
INPUTS OUTPUTS
11
10
9
8
7
6
5
4
3
2
1
+5V
400kΩ
N.C. 12 44 N.C. 38 T4IN T4OUT 5
T4
R2OUT 13 43 SHDN
T2IN 14 42 EN +5V
400kΩ
T1IN 15 41 T5OUT
R1OUT 16 40 R4IN 2 T5IN T5OUT 41
T5
R1IN 17 39 R4OUT
GND 18 MAX240 38 T4IN R1IN 17
16 R1OUT
VCC 19 37 T3IN R1
N.C. 20 36 R5OUT 5kΩ
N.C. 21 35 R5IN
N.C. 22 34 N.C. 13 R2OUT R2IN 10
R2
23
24
25
26
27
28
29
30
31
32
33
5kΩ

R3
N.C.
N.C.
C1+
V+
C1-
C2+
C2
V-
N.C.
N.C.
N.C.
OUTPUTS INPUTS
5kΩ
Plastic FP
39 R4OUT R4IN 40
R4
5kΩ
36 R5OUT R5IN 35
R5
5kΩ
42 EN 43
SHDN
GND
18
______________________________________________________________________________________ 27
Drivers/Receivers
MAX220–MAX249
TOP VIEW +5V INPUT ALL CAPACITORS = 0.1µF

0.1µF 0.1µF
16
1
C1+ VCC
2 +10V
0.1µF +5V TO +10V V+
3 C1- VOLTAGE DOUBLER
4
C2+
C1+ 1 16 VCC +10V TO -10V 6 -10V
0.1µF 5 C2- V-
VOLTAGE INVERTER
V+ 2 15 GND 0.1µF
C1- 3 14 T1OUT +5V
C2+ 4 MAX243 13 R1IN 400kΩ
C2- 5 12 R1OUT 11 T1IN T1OUT 14
V- 6 11 T1IN +5V
TTL/CMOS RS-232
T2OUT 7 10 T2IN
R2IN 8 9 R2OUT 10 T2IN T2OUT 7
DIP/SO
12 R1OUT R1IN 13

OUTPUTS INPUTS
9 R2OUT R2IN 8
RECEIVER INPUT R1 OUTPUT R2 OUTPUT

≤ -3 V HIGH HIGH 5kΩ
OPEN HIGH LOW
≥ +3V LOW LOW GND
15
28 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW 1µF
1µF
20
21
C1+ VCC 22
1µF
TB4OUT
TA4OUT
TA3OUT
TA2OUT
TA1OUT
TB1OUT
TB2OUT
TB3OUT
23 C1- +5V TO +10V VOLTAGE DOUBLER V+
RA4IN
RA5IN
RB5IN
24 26
C2+ V- 1µF
1µF 25 C2-
6 5 4 3 2 1 44 43 42 41 40 +10V TO -10V VOLTAGE INVERTER
2 TA1OUT +5V +5V TB1OUT 44
400kΩ
15 TA1IN TB1IN 30
RA3IN 7 39 RB4IN
RA2IN 8 38 RB3IN +5V +5V
2 TA2OUT TB2OUT 43
RA1IN 9 37 RB2IN
400kΩ
RA1OUT 10 36 RB1IN 16 TA2IN TB2IN 29
RA2OUT 11 35 RB1OUT
RA3OUT 12
MAX244 34 RB2OUT 3 TA3OUT +5V +5V TB3OUT 42
RA4OUT 13 33 RB3OUT 400kΩ
RA5OUT 14 32 RB4OUT 17 TA3IN TB3IN 28
TA1IN 15 31 RB5OUT
TA2IN 16 30 TB1IN
400kΩ
TA3IN 17 29 TB2IN 18 TA4IN TB4IN 27
9 RA1IN RB1IN 36
18 19 20 21 22 23 24 25 26 27 28
TA4IN
GND
C1+
V+
C1-
C2+
C2-
V-
TB4IN
TB3IN
VCC
5kΩ 5kΩ
PLCC 10 RA1OUT RB1OUT 35

8 RA2IN RB2IN 37
5kΩ 5kΩ
10 RECEIVERS 11 RA2OUT RB2OUT 34
5 A-SIDE RECEIVER 7 RA3IN RB3IN 38
5 B-SIDE RECEIVER
8 TRANSMITTERS 5kΩ 5kΩ
4 A-SIDE TRANSMITTERS
4 B-SIDE TRANSMITTERS 12 RA3OUT RB3OUT 33
NO CONTROL PINS 6 RA4IN RB4IN 39
5kΩ 5kΩ
13 RA4OUT RB4OUT 32
5 RA5IN RB5IN 40
5kΩ 5kΩ
14 RA5OUT RB5OUT 31
GND
19
______________________________________________________________________________________ 29
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
40
VCC
ENR 1 40 VCC 16 TA1OUT +5V +5V TB1OUT 24
400kΩ
TA1IN 2 39 ENT
2 TA1IN TB1IN 38
TA2IN 3 38 TB1IN
TA3IN 4 37 TB2IN
400kΩ
TA4IN 5 36 TB3IN
3 TA2IN TB2IN 37
RA5OUT 6 35 TB4IN
RA4OUT 7
MAX245 34 RB5OUT 18 TA3OUT +5V +5V TB3OUT 22
400kΩ
RA3OUT 8 33 RB4OUT
4 TA3IN TB3IN 36
RA2OUT 9 32 RB3OUT
RA1OUT 10 31 RB2OUT
400kΩ
RA1IN 11 30 RB1OUT 5 TA4IN TB4IN 35
RA2IN 12 29 RB1IN
1 ENR ENT 39
RA3IN 13 28 RB2IN
11 RA1IN RB1IN 29
RA4IN 14 27 RB3IN
RA5IN 15 26 RB4IN
5kΩ 5kΩ
TA1OUT 16 25 RB5IN
TA2OUT 17 24 TB1OUT 10 RA1OUT RB1OUT 30

12 RA2IN RB2IN 28
TA3OUT 18 23 TB2OUT
TA4OUT 19 22 TB3OUT
5kΩ 5kΩ
GND 20 21 TB4OUT
9 RA2OUT RB2OUT 31
DIP 13 RA3IN RB3IN 27
5kΩ 5kΩ
8 RA3OUT RB3OUT 32
14 RA4IN RB4IN 26
10 RECEIVERS
5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE)
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE) 5kΩ 5kΩ
8 TRANSMITTTERS
7 RA4OUT RB4OUT 33
15 RA5IN RB5IN 25
2 CONTROL PINS
1 RECEIVER ENABLE (ENR)
5kΩ 5kΩ
1 TRANSMITTER ENABLE (ENT)
6 RA5OUT RB5OUT 34
GND
20
30 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
40
VCC
ENA 1 40 VCC +5V +5V
16 TA1OUT TB1OUT 24
TA1IN 2 39 ENB
400kΩ
TA2IN 3 38 TB1IN
2 TA1IN TB1IN 38
TA3IN 4 37 TB2IN +5V +5V
TA4IN 5 36 TB3IN 17 TA2OUT TB2OUT 23
400kΩ
RA5OUT 6 35 TB4IN
3 TA2IN TB2IN 37
RA4OUT 7 MAX246 34 RB5OUT +5V +5V
RA3OUT 8 33 RB4OUT 18 TA3OUT TB3OUT 22

4 TA3IN TB3IN 36
RA1OUT 10 31 RB2OUT
+5V +5V
RA1IN 11 30 RB1OUT 19 TA4OUT TB4OUT 21
RA2IN 12 29 RB1IN 400kΩ

5 TA4IN TB4IN 35
RA3IN 13 28 RB2IN
1 ENA ENB 39
RA4IN 14 27 RB3IN
11 RA1IN RB1IN 29
RA5IN 15 26 RB4IN
TA1OUT 16 25 RB5IN 5kΩ 5kΩ

TA2OUT 17 24 TB1OUT
10 RA1OUT RB1OUT 30
TA3OUT 18 23 TB2OUT
12 RA2IN RB2IN 28
TA4OUT 19 22 TB3OUT
GND 20 21 TB4OUT 5kΩ 5kΩ
DIP 9 RA2OUT RB2OUT 31

13 RA3IN RB3IN 27
5kΩ 5kΩ
5 A-SIDE RECEIVERS (RA5 ALWAYS ACTIVE)
14 RA4IN RB4IN 26
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)
8 TRANSMITTERS
5kΩ 5kΩ
2 CONTROL PINS 15 RA5IN RB5IN 25
ENABLE A-SIDE (ENA)
ENABLE B-SIDE (ENB) 5kΩ 5kΩ
6 RA5OUT RB5OUT 34
GND
20
______________________________________________________________________________________ 31
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW
1µF
40
1 ENTA VCC ENTB 39
ENTA 1 40 VCC +5V +5V
16 TA1OUT TB1OUT 24
TA1IN 2 39 ENTB
400kΩ
TA2IN 3 38 TB1IN 2 TA1IN TB1IN 38
TA3IN 4 37 TB2IN +5V +5V
17 TA2OUT TB2OUT 23
TA4IN 5 36 TB3IN
400kΩ
RB5OUT 6 35 TB4IN 3 TA2IN TB2IN 37
RA4OUT 7 MAX247 34 RB4OUT +5V +5V
18 TA3OUT TB3OUT 22
RA3OUT 8 33 RB3OUT
400kΩ
RA2OUT 9 32 RB2OUT
4 TA3IN TB3IN 36
RA1OUT 10 31 RB1OUT +5V +5V
19 TA4OUT TB4OUT 21
ENRA 11 30 ENRB
400kΩ
RA1IN 12 29 RB1IN
5 TA4IN TB4IN 35
RA2IN 13 28 RB2IN
6 RB5OUT RB5IN 25
RA3IN 14 27 RB3IN
TA1OUT 16 25 RB5IN
TA2OUT 17 24 TB1OUT 12 RA1IN RB1IN 29
TA3OUT 18 23 TB2OUT
5kΩ 5kΩ
TA4OUT 19 22 TB3OUT
GND 20 21 TB4OUT 10 RA1OUT RB1OUT 31

13 RA2IN RB2IN 28
DIP
5kΩ 5kΩ
4 A-SIDE RECEIVERS 14 RA3IN RB3IN 27
5 B-SIDE RECEIVERS (RB5 ALWAYS ACTIVE)
8 TRANSMITTERS 5kΩ 5kΩ
4 CONTROL PINS 15 RA4IN RB4IN 26
ENABLE RECEIVER A-SIDE (ENRA)

ENABLE RECEIVER B-SIDE (ENRB) 5kΩ 5kΩ
ENABLE RECEIVER A-SIDE (ENTA)

7 RA4OUT RB4OUT 34
ENABLE RECEIVERr B-SIDE (ENTB)
11 ENRA ENRB 30
GND
20
32 ______________________________________________________________________________________
Drivers/Receivers
MAX220–MAX249
TOP VIEW +5V
1µF
1µF
20
21
C1+ VCC 22
TA4OUT
TA3OUT
TA2OUT
TA1OUT
TB1OUT
TB2OUT
TB3OUT
TA4OUT
1µF V+
23 C1-
RA3IN
RA4IN
RB4IN
+5V TO +10V VOLTAGE DOUBLER 26
24 V-
C2+ 1µF
6 5 4 3 2 1 44 43 42 41 40 1µF 25 C2- +10V TO -10V VOLTAGE INVERTER
18 ENTA ENTB 27
+5V +5V
1 TA1OUT TB1OUT 44
RA1IN 8 38 RB2IN 14 TA1IN TB1IN 31
ENRA 9 37 RB1IN +5V +5V
RA1OUT 10 36 ENRB 2 TA2OUT TB2OUT 43
RA3OUT 12
MAX248 34 RB2OUT 15 TA2IN TB2IN 30
3 TA3OUT TB3OUT 42
TA1IN 14 32 RB4OUT
TA2IN 15 31 TB1IN 400kΩ
16 TA3IN TB3IN 29
TA3IN 16 30 TB2IN
TA4IN 17 29 TB3IN
+5V +5V
4 TA4OUT TB4OUT 41
400kΩ
18 19 20 21 22 23 24 25 26 27 28
17 TA4IN TB4IN 28
ENTA
GND
C1+
V+
C1-
C2+
C2-
V-
ENTB
TB4IN
VCC
8 RA1IN RB1IN 37
PLCC
5kΩ 5kΩ
MAX248 FUNCTIONAL DESCRIPTION 10 RA1OUT RB1OUT 35

8 RECEIVERS 7 RA2IN RB2IN 38
4 A-SIDE RECEIVERS
4 B-SIDE RECEIVERS 5kΩ 5kΩ
8 TRANSMITTERS
11 RA2OUT RB2OUT 34
6 RA3IN RB3IN 39
4 B-SIDE TRANSMITTERS
4 CONTROL PINS
5kΩ 5kΩ
ENABLE RECEIVER B-SIDE (ENRB)
12 RA3OUT RB3OUT 33
ENABLE RECEIVER A-SIDE (ENTA)
5 RA4IN RB4IN 40
ENABLE RECEIVER B-SIDE (ENTB)
5kΩ 5kΩ
13 RA4OUT RB4OUT 32
9 ENRA ENRB 36
GND
19
______________________________________________________________________________________ 33
Drivers/Receivers
MAX220–MAX249
+5V
TOP VIEW 1µF
1µF
20
21
C1+ VCC 22
TA3OUT
TA2OUT
TA1OUT
TB1OUT
TB2OUT
TB3OUT
1µF V+
23 C1-
RA3IN
RA4IN
RA5IN
RB5IN
RB4IN
+5V TO +10V VOLTAGE DOUBLER 26
24 V-
C2+ 1µF
6 5 4 3 2 1 44 43 42 41 40 1µF 25 C2- +10V TO -10V VOLTAGE INVERTER
18 ENTA ENTB 27
+5V +5V
1 TA1OUT TB1OUT 44
RA1IN 8 38 RB2IN 15 TA1IN TB1IN 30
ENRA 9 37 RB1IN +5V +5V
RA1OUT 10 36 ENRB 2 TA2OUT TB2OUT 43
RA3OUT 12
MAX249 34 RB2OUT 16 TA2IN TB2IN 29
3 TA3OUT TB3OUT 42
RA5OUT 14 32 RB4OUT
TA1IN 15 31 RB5OUT 400kΩ
17 TA3IN TB3IN 28
TA2IN 16 30 TB1IN
8 RA1IN RB1IN 37
TA3IN 17 29 TB2IN
18 19 20 21 22 23 24 25 26 27 28 5kΩ 5kΩ
ENTA
GND
C1+
V+
C1-
C2+
C2-
V-
ENTB
TB3IN
VCC
10 RA1OUT RB1OUT 35
7 RA2IN RB2IN 38
PLCC
5kΩ 5kΩ
11 RA2OUT RB2OUT 34
6 RA3IN RB3IN 39
10 RECEIVERS
5 A-SIDE RECEIVERS
5kΩ 5kΩ
5 B-SIDE RECEIVERS
6 TRANSMITTERS 12 RA3OUT RB3OUT 33
3 A-SIDE TRANSMITTERS 5 RA4IN RB4IN 40
3 B-SIDE TRANSMITTERS
4 CONTROL PINS
5kΩ 5kΩ
ENABLE RECEIVER B-SIDE (ENRB) 13 RA4OUT RB4OUT 32
ENABLE RECEIVER A-SIDE (ENTA) 4 RA5IN RB5IN 41
ENABLE RECEIVER B-SIDE (ENTB)
5kΩ 5kΩ
14 RA5OUT RB5OUT 31
9 ENRA ENRB 36
GND
19
34 ______________________________________________________________________________________
Drivers/Receivers
___________________________________________Ordering Information (continued)
MAX220–MAX249
PART TEMP RANGE PIN-PACKAGE PART TEMP RANGE PIN-PACKAGE
MAX222CPN 0°C to +70°C 18 Plastic DIP MAX232AC/D 0°C to +70°C Dice*
MAX222CWN 0°C to +70°C 18 Wide SO MAX232AEPE -40°C to +85°C 16 Plastic DIP
MAX222C/D 0°C to +70°C Dice* MAX232AESE -40°C to +85°C 16 Narrow SO
MAX222EPN -40°C to +85°C 18 Plastic DIP MAX232AEWE -40°C to +85°C 16 Wide SO
MAX222EWN -40°C to +85°C 18 Wide SO MAX232AEJE -40°C to +85°C 16 CERDIP
MAX222EJN -40°C to +85°C 18 CERDIP MAX232AMJE -55°C to +125°C 16 CERDIP
MAX222MJN -55°C to +125°C 18 CERDIP MAX232AMLP -55°C to +125°C 20 LCC
MAX223CAI 0°C to +70°C 28 SSOP MAX233CPP 0°C to +70°C 20 Plastic DIP
MAX223CWI 0°C to +70°C 28 Wide SO MAX233EPP -40°C to +85°C 20 Plastic DIP
MAX223C/D 0°C to +70°C Dice* MAX233ACPP 0°C to +70°C 20 Plastic DIP
MAX223EAI -40°C to +85°C 28 SSOP MAX233ACWP 0°C to +70°C 20 Wide SO
MAX223EWI -40°C to +85°C 28 Wide SO MAX233AEPP -40°C to +85°C 20 Plastic DIP
MAX225CWI 0°C to +70°C 28 Wide SO MAX233AEWP -40°C to +85°C 20 Wide SO
MAX225EWI -40°C to +85°C 28 Wide SO MAX234CPE 0°C to +70°C 16 Plastic DIP
MAX230CPP 0°C to +70°C 20 Plastic DIP MAX234CWE 0°C to +70°C 16 Wide SO
MAX230CWP 0°C to +70°C 20 Wide SO MAX234C/D 0°C to +70°C Dice*
MAX230C/D 0°C to +70°C Dice* MAX234EPE -40°C to +85°C 16 Plastic DIP
MAX230EPP -40°C to +85°C 20 Plastic DIP MAX234EWE -40°C to +85°C 16 Wide SO
MAX230EWP -40°C to +85°C 20 Wide SO MAX234EJE -40°C to +85°C 16 CERDIP
MAX230EJP -40°C to +85°C 20 CERDIP MAX234MJE -55°C to +125°C 16 CERDIP
MAX230MJP -55°C to +125°C 20 CERDIP MAX235CPG 0°C to +70°C 24 Wide Plastic DIP
MAX231CPD 0°C to +70°C 14 Plastic DIP MAX235EPG -40°C to +85°C 24 Wide Plastic DIP
MAX231CWE 0°C to +70°C 16 Wide SO MAX235EDG -40°C to +85°C 24 Ceramic SB
MAX231CJD 0°C to +70°C 14 CERDIP MAX235MDG -55°C to +125°C 24 Ceramic SB
MAX231C/D 0°C to +70°C Dice* MAX236CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX231EPD -40°C to +85°C 14 Plastic DIP MAX236CWG 0°C to +70°C 24 Wide SO
MAX231EWE -40°C to +85°C 16 Wide SO MAX236C/D 0°C to +70°C Dice*
MAX231EJD -40°C to +85°C 14 CERDIP MAX236ENG -40°C to +85°C 24 Narrow Plastic DIP
MAX231MJD -55°C to +125°C 14 CERDIP MAX236EWG -40°C to +85°C 24 Wide SO
MAX232CPE 0°C to +70°C 16 Plastic DIP MAX236ERG -40°C to +85°C 24 Narrow CERDIP
MAX232CSE 0°C to +70°C 16 Narrow SO MAX236MRG -55°C to +125°C 24 Narrow CERDIP
MAX232CWE 0°C to +70°C 16 Wide SO MAX237CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX232C/D 0°C to +70°C Dice* MAX237CWG 0°C to +70°C 24 Wide SO
MAX232EPE -40°C to +85°C 16 Plastic DIP MAX237C/D 0°C to +70°C Dice*
MAX232ESE -40°C to +85°C 16 Narrow SO MAX237ENG -40°C to +85°C 24 Narrow Plastic DIP
MAX232EWE -40°C to +85°C 16 Wide SO MAX237EWG -40°C to +85°C 24 Wide SO
MAX232EJE -40°C to +85°C 16 CERDIP MAX237ERG -40°C to +85°C 24 Narrow CERDIP
MAX232MJE -55°C to +125°C 16 CERDIP MAX237MRG -55°C to +125°C 24 Narrow CERDIP
MAX232MLP -55°C to +125°C 20 LCC MAX238CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX232ACPE 0°C to +70°C 16 Plastic DIP MAX238CWG 0°C to +70°C 24 Wide SO
MAX232ACSE 0°C to +70°C 16 Narrow SO MAX238C/D 0°C to +70°C Dice*
MAX232ACWE 0°C to +70°C 16 Wide SO MAX238ENG -40°C to +85°C 24 Narrow Plastic DIP
* Contact factory for dice specifications.
______________________________________________________________________________________ 35
Drivers/Receivers
___________________________________________Ordering Information (continued)
MAX220–MAX249
PART TEMP RANGE PIN-PACKAGE PART TEMP RANGE PIN-PACKAGE

MAX238EWG -40°C to +85°C 24 Wide SO MAX243CPE 0°C to +70°C 16 Plastic DIP
MAX238ERG -40°C to +85°C 24 Narrow CERDIP MAX243CSE 0°C to +70°C 16 Narrow SO
MAX238MRG -55°C to +125°C 24 Narrow CERDIP MAX243CWE 0°C to +70°C 16 Wide SO
MAX239CNG 0°C to +70°C 24 Narrow Plastic DIP MAX243C/D 0°C to +70°C Dice*
MAX239CWG 0°C to +70°C 24 Wide SO MAX243EPE -40°C to +85°C 16 Plastic DIP
MAX239C/D 0°C to +70°C Dice* MAX243ESE -40°C to +85°C 16 Narrow SO
MAX239ENG -40°C to +85°C 24 Narrow Plastic DIP MAX243EWE -40°C to +85°C 16 Wide SO
MAX239EWG -40°C to +85°C 24 Wide SO MAX243EJE -40°C to +85°C 16 CERDIP
MAX239ERG -40°C to +85°C 24 Narrow CERDIP MAX243MJE -55°C to +125°C 16 CERDIP
MAX239MRG -55°C to +125°C 24 Narrow CERDIP MAX244CQH 0°C to +70°C 44 PLCC
MAX240CMH 0°C to +70°C 44 Plastic FP MAX244C/D 0°C to +70°C Dice*
MAX240C/D 0°C to +70°C Dice* MAX244EQH -40°C to +85°C 44 PLCC
MAX241CAI 0°C to +70°C 28 SSOP MAX245CPL 0°C to +70°C 40 Plastic DIP
MAX241CWI 0°C to +70°C 28 Wide SO MAX245C/D 0°C to +70°C Dice*
MAX241C/D 0°C to +70°C Dice* MAX245EPL -40°C to +85°C 40 Plastic DIP
MAX241EAI -40°C to +85°C 28 SSOP MAX246CPL 0°C to +70°C 40 Plastic DIP
MAX241EWI -40°C to +85°C 28 Wide SO MAX246C/D 0°C to +70°C Dice*
MAX242CAP 0°C to +70°C 20 SSOP MAX246EPL -40°C to +85°C 40 Plastic DIP
MAX242CPN 0°C to +70°C 18 Plastic DIP MAX247CPL 0°C to +70°C 40 Plastic DIP
MAX242CWN 0°C to +70°C 18 Wide SO MAX247C/D 0°C to +70°C Dice*
MAX242C/D 0°C to +70°C Dice* MAX247EPL -40°C to +85°C 40 Plastic DIP
MAX242EPN -40°C to +85°C 18 Plastic DIP MAX248CQH 0°C to +70°C 44 PLCC
MAX242EWN -40°C to +85°C 18 Wide SO MAX248C/D 0°C to +70°C Dice*
MAX242EJN -40°C to +85°C 18 CERDIP MAX248EQH -40°C to +85°C 44 PLCC
MAX242MJN -55°C to +125°C 18 CERDIP MAX249CQH 0°C to +70°C 44 PLCC
MAX249EQH -40°C to +85°C 44 PLCC
* Contact factory for dice specifications.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Revision History
Pages changed at Rev 15: 2–5, 8, 9, 36
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
PRODUCT SPECIFICATION
Single chip 433/868/915 MHz Transceiver nRF905

FEATURES APPLICATIONS
• True single chip GFSK transceiver in a small • Wireless data communication

32-pin package (32L QFN 5x5mm) • Alarm and security systems
• ShockBurst™ mode for low power operation • Home Automation
• Power supply range 1.9 to 3.6 V • Remote control
• Multi channel operation – ETSI/FCC • Surveillance
Compatible • Automotive
• Channel switching time <650µs • Telemetry
• Extremely low cost Bill of Material (BOM) • Industrial sensors
• No external SAW filter • Keyless entry
• Adjustable output power up to 10dBm • Toys
• Carrier detect for "listen before transmit"
protocols
• Data Ready signal when a valid data packet
is received or transmitted
• Address Match for detection of incoming
packet
• Automatic retransmission of data packet
• Automatic CRC and preamble generation
• Low supply current (TX), typical 9mA
@ -10dBm output power
• Low supply current (RX), typical 12.5mA
GENERAL DESCRIPTION
nRF905 is a single-chip radio transceiver for the 433/868/915 MHz ISM band. The
transceiver consists of a fully integrated frequency synthesiser, receiver chain with
demodulator, a power amplifier, a crystal oscillator and a modulator. The
ShockBurstTM feature automatically handles preamble and CRC. Configuration is
easily programmable by use of the SPI interface. Current consumption is very low, in
transmit only 9mA at an output power of -10dBm, and in receive mode 12.5mA. Built
in power down modes makes power saving easily realizable.
QUICK REFERENCE DATA

Parameter Value Unit
Minimum supply voltage 1.9 V
Maximum transmit output power 10 dBm
Data rate 50 kbps
Supply current in transmit @ -10dBm output power 9 mA
Supply current in receive mode 12.5 mA
Temperature range -40 to +85 °C
Typical Sensitivity -100 dBm
Supply current in power down mode 2.5 µΑ
Table 1 nRF905 quick reference data.
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 -Fax +4772898989
Revision: 1.3 Page 1 of 41 December 2005
nRF905 Single Chip 433/868/915 MHz Radio Transceiver
ORDERING INFORMATION
Type Number Description Version
nRF905 IC 32L QFN 5x5mm -
nRF905-EVKIT 433 Evaluation kit 433MHz 1.0
nRF905-EVKIT 868/915 Evaluation kit 868/915MHz 1.0
Table 2 nRF905 ordering information.
BLOCK DIAGRAM
DVDD_1V2 (31)
VDD (17)
VDD (25)
VSS (16)
VSS (18)
VSS (22)
VSS (24)
VSS (26)
VSS (27)
VSS (28)
VSS (29)
VSS (30)
VDD (4)
VSS (5)
VSS (9)
XC1 (14)
MISO (10)
MOSI (11) SPI Voltage Crystal
SCK (12)
interface regulators oscillator XC2 (15)
TX - addr.
CSN (13)
TX - reg.
IF BBF
RX - reg.
Config-reg. LNA
TRX_CE (1)
PWR_UP (2) ShockBurst
TX_EN (32)
Demod
VDD_PA (19)
Dataslicer Frequency
Synthesiser
CD (6) CRC code/
decode
AM (7)
Address
DR (8) ANT1 (20)
decode
PA
GFSK ANT2 (21)
uPCLK (3)
filter
Manchester
encoder/ IREF (23)
decoder
Figure 1 nRF905 with external components.
TABLE OF CONTENTS
1 Pin Functions..................................................................................................................... 4
2 Pin Assignment ................................................................................................................. 5
3 Electrical Specifications.................................................................................................... 6
4 Current Consumption........................................................................................................ 8
5 Modes of Operation .......................................................................................................... 9
5.1 Active Modes ........................................................................................................... 9
5.2 Power Saving Modes................................................................................................ 9
5.3 nRF ShockBurst™ Mode ......................................................................................... 9
5.4 Typical ShockBurstTM TX ...................................................................................... 10
5.5 Typical ShockBurstTM RX...................................................................................... 12
5.6 Power Down Mode................................................................................................. 14
5.7 Standby Mode......................................................................................................... 14
6 Device Configuration...................................................................................................... 15
6.1 SPI Register Configuration .................................................................................... 15
6.2 SPI Instruction Set.................................................................................................. 16
6.3 SPI Timing ............................................................................................................. 17
6.4 RF – Configuration Register Description............................................................... 19
6.5 Register Contents ................................................................................................... 20
7 Important Timing Data.................................................................................................... 21
7.1 Device Switching Times ........................................................................................ 21
7.2 ShockBurstTM TX timing........................................................................................ 21
7.3 ShockBurstTM RX timing........................................................................................ 22
7.4 Preamble................................................................................................................. 22
7.5 Time On Air ........................................................................................................... 23
8 Peripheral RF Information .............................................................................................. 24
8.1 Crystal Specification .............................................................................................. 24
8.2 External Clock Reference....................................................................................... 24
8.3 Microprocessor Output Clock ................................................................................ 24
8.4 Antenna Output ...................................................................................................... 25
8.5 Output Power Adjustment ...................................................................................... 25
8.6 Modulation ............................................................................................................. 25
8.7 Output Frequency................................................................................................... 26
8.8 PCB Layout and Decoupling Guidelines ............................................................... 27
9 nRF905 features .............................................................................................................. 28
9.1 Carrier Detect. ........................................................................................................ 28
9.2 Address Match........................................................................................................ 28
9.3 Data Ready ............................................................................................................. 28
9.4 Auto Retransmit ..................................................................................................... 29
9.5 RX Reduced Power Mode...................................................................................... 29
10 Package Outline .......................................................................................................... 30
10.1 Package marking .................................................................................................... 31
11 Application Examples................................................................................................. 32
11.1 Differential Connection to a Loop Antenna ........................................................... 32
11.2 PCB Layout Example; Differential Connection to a Loop Antenna ...................... 33
11.3 Single ended connection to 50Ω antenna ............................................................... 34
11.4 PCB Layout Example; Single Ended Connection to 50Ω Antenna ....................... 36
12 Absolute Maximum Ratings ....................................................................................... 37
13 Glossary of Terms....................................................................................................... 38
14 Definitions .................................................................................................................. 39
1 PIN FUNCTIONS
Pin Name Pin function Description
1 TRX_CE Digital input Enables chip for receive and transmit
2 PWR_UP Digital input Power up chip
3 uPCLK Clock output Output clock, divided crystal oscillator full-swing clock
4 VDD Power Power supply (+3V DC)
5 VSS Power Ground (0V)
6 CD Digital output Carrier Detect
7 AM Digital output Address Match
8 DR Digital output Receive and transmit Data Ready
10 MISO SPI - interface SPI output
11 MOSI SPI - interface SPI input
12 SCK SPI - Clock SPI clock
13 CSN SPI - enable SPI enable, active low
14 XC1 Analog Input Crystal pin 1/ External clock reference pin
15 XC2 Analog Output Crystal pin 2
18 VSS Power Ground
19 VDD_PA Power output Positive supply (1.8V) to nRF905 power amplifier
20 ANT1 RF Antenna interface 1
21 ANT2 RF Antenna interface 2
23 IREF Analog Input Reference current
31 DVDD_1V2 Power Low voltage positive digital supply output for de-coupling
32 TX_EN Digital input TX_EN=”1”TX mode, TX_EN=”0”RX mode
Table 3 nRF905 pin function.
2 PIN ASSIGNMENT
TX_EN DVDD_1V2 VSS VSS VSS VSS VSS VDD
32 31 30 29 28 27 26 25
TRX_CE 1 24 VSS
PWR_UP 2 23 IREF
nRF905
uPCLK 3 32L QFN 5x5
22 VSS
VDD 4 21 ANT2
VSS 5 20 ANT1
CD 6 19 VDD_PA
AM 7 18 VSS
DR 8 17 VDD
9 10 11 12 13 14 15 16
VSS MISO MOSI SCK CSN XC1 XC2 VSS
Figure 2 nRF905 pin assignment (top view) for a 32L QFN 5x5 package.
3 ELECTRICAL SPECIFICATIONS
Conditions: VDD = +3V VSS = 0V, TEMP = -40ºC to +85ºC (typical +27ºC)
Symbol Parameter (condition) Notes Min. Typ. Max. Units
Operating conditions
VDD Supply voltage 1.9 3.6 V
TEMP Operating temperature -40 85 ºC
Digital input/output
VIH HIGH level input voltage 0.7·VDD VDD V
VIL LOW level input voltage VSS 0.3·VDD V
Ci Pin capacitance 5 pF
IiL Pin leakage current 1) ±10 nA
VOH HIGH level output voltage (IOH=-0.5mA) VDD-0.3 VDD V
VOL LOW level output voltage (IOL=0.5mA) VSS 0.3 V
General electrical specification

Istby_eclk Supply current in standby, uCLK enabled 2) 100 µA
Istby_dclk Supply current in standby, uCLK disabled 3) 12.5 µA
IPD Supply current in power down mode 4) 2.5 µA
ISPI Supply current in SPI programming 5) 20 µA
General RF conditions
fOP Operating frequency 6) 430 928 MHz
fXTAL Crystal frequency 7) 4 20 MHz
∆f Frequency deviation ±42 ±50 ±58 kHz
BR Data rate 8) 50 kbps
fCH433 Channel spacing for 433MHz band 100 kHz
fCH868/915 Channel spacing for 868/915MHz band 200 kHz
Transmitter operation
PRF10 Output power 10dBm setting 9) 7 10 11 dBm
PRF6 Output power 6dBm setting 9) 3 6 9 dBm
PRF-2 Output power –2dBm setting 9) -6 -2 2 dBm
PRF-10 Output power -10dBm setting 9) -14 -10 -6 dBm
PBW_-16 -16dBc bandwidth for modulated carrier 8) 173 kHz
PRF1 1st adjacent channel transmit power 10) -27 dBc
PRF2 2nd adjacent channel transmit power 10) -54 dBc
ITX10dBm Supply current @ 10dBm output power 30 mA
ITX-10dBm Supply current @ -10dBm output power 9 mA
Receiver operation
IRX Supply current in receive mode 12.5 mA
RXSENS Sensitivity at 0.1%BER -100 dBm
RXMAX Maximum received signal 0 dBm
C/ICO C/I Co-channel 11) 13 dB
C/I1ST 1st adjacent channel selectivity C/I 200kHz 11) -7 dB
C/I2ND 2nd adjacent channel selectivity C/I 400kHz 11) -16 dB
C/I+1M Blocking at +1MHz 11) -40 dB
C/I-1M Blocking at -1MHz 11) -50 dB
C/IIM Image rejection 11) -36 dB
Table 4 nRF905 electrical specifications.
1) Max value determined by design and characterization testing.

2) Output frequency is 4MHz load of external clock pin is 5pF, Crystal is 4MHz.
3) Crystal is 4MHz.
4) Pin voltages are VSS or VDD.
5) Chip in power down, SPI_SCK frequency is 1MHz.
6) Operates in the 433, 868 and 915 MHz ISM band.
7) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz)
8) Data is Manchester-encoded before GFSK modulation.
9) Optimum load impedance, please see peripheral RF information.
10) Channel width and channel spacing is 200kHz.
11) Channel Level +3dB over sensitivity, interfering signal a standard CW, image lies 2MHz above wanted.
4 CURRENT CONSUMPTION
MODE CRYSTAL OUTPUT TYPICAL

FREQ. [MHZ] CLOCK CURRENT
FREQ. [MHZ]
Power Down 16 OFF 2.5 uA
Standby 4 OFF 12 uA
Standby 8 OFF 25 uA
Standby 12 OFF 27 uA
Standby 4 0.5 110 uA
Standby 4 1 130 uA
Standby 8 1 145 uA
Standby 12 1 150 uA
Standby 16 1 155 uA
Standby 20 1 170 uA
Standby 4 2 170 uA
Standby 8 2 185 uA
Standby 12 2 190 uA
Standby 16 2 195 uA
Standby 20 2 210 uA
Standby 4 4 260 uA
Standby 8 4 275 uA
Standby 12 4 280 uA
Standby 16 4 285 uA
Standby 20 4 300 uA
Rx @ 433 16 OFF 12.2 mA
Rx @ 868/915 16 OFF 12.8 mA
Reduced Rx 16 OFF 10.5 mA
Tx @ 10dBm 16 OFF 30 mA
Tx @ 6dBm 16 OFF 20 mA
Tx @ -2dBm 16 OFF 14 mA
Tx @ -10dBm 16 OFF 9 mA
Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC,
Load capacitance of external clock = 13pF, Crystal load capacitance = 12pF
Table 5 nRF905 current consumption.
5 MODES OF OPERATION
The nRF905 has two active (RX/TX) modes and two power-saving modes
5.1 Active Modes

• ShockBurst™ RX
• ShockBurst™ TX
5.2 Power Saving Modes

• Power down and SPI - programming
• Standby and SPI - programming
The nRF905 mode is decided by the settings of TRX_CE, TX_EN and PWR_UP.
PWR_UP TRX_CE TX_EN Operating Mode

0 X X Power down and SPI – programming
1 0 X Standby and SPI – programming
1 X 0 Read data from RX register
1 1 0 Radio Enabled - ShockBurstTM RX
1 1 1 Radio Enabled - ShockBurstTM TX
Table 6 nRF905 operational modes.
5.3 nRF ShockBurst™ Mode
The nRF905 uses the Nordic Semiconductor ASA ShockBurst™ feature.

ShockBurstTM makes it possible to use the high data rate offered by the nRF905
without the need of a costly, high-speed micro controller (MCU) for data
processing/clock recovery. By placing all high speed signal processing related to RF
protocol on-chip, the nRF905 offers the application micro controller a simple SPI
interface, the data rate is decided by the interface-speed the micro controller itself sets
up. By allowing the digital part of the application to run at low speed, while
maximizing the data rate on the RF link, the nRF905 ShockBurst™ mode reduces the
average current consumption in applications. In ShockBurstTM RX, Address Match
(AM) and Data Ready (DR) notifies the MCU when a valid address and payload is
received respectively. In ShockBurstTM TX, the nRF905 automatically generates
preamble and CRC. Data Ready (DR) notifies the MCU that the transmission is
completed. All together, this means reduced memory demand in the MCU resulting in
a low cost MCU, as well as reduced software development time.
5.4 Typical ShockBurstTM TX
1. When the application MCU has data for a remote node, the address of the
receiving node (TX-address) and payload data (TX-payload) are clocked
into nRF905 via the SPI interface. The application protocol or MCU sets
the speed of the interface.
2. MCU sets TRX_CE and TX_EN high, this activates a nRF905
ShockBurst™ transmission.
3. nRF905 ShockBurst™:
• Radio is automatically powered up.
• Data packet is completed (preamble added, CRC calculated).
• Data packet is transmitted (100kbps, GFSK, Manchester-encoded).
• Data Ready is set high when transmission is completed.
4. If AUTO_RETRAN is set high, the nRF905 continuously retransmits the
packet until TRX_CE is set low.
5. When TRX_CE is set low, the nRF905 finishes transmitting the outgoing
packet and then sets itself into standby mode.
If TX_EN is set low while TRX_CE is kept high, the nRF905 finishes transmitting
the outgoing packet and then enter RX-mode in the channel already programmed in
the RF-CONFIG register.
The ShockBurstTM mode ensures that a transmitted packet that has started always
finishes regardless of what TRX_EN and TX_EN is set to during transmission. The
new mode is activated when the transmission is completed. Please see subsequent
chapters for detailed timing
For test purposes such as antenna tuning and measuring output power it is possible to
set the transmitter so that a constant carrier is produced. To do this TRX_CE must be
maintained high instead of being pulsed. In addition Auto Retransmit should be
switched off. After the burst of data has been sent then the device will continue to
send the unmodulated carrier.
Radio in Standby
TX_EN = HI
PWR_UP = HI
TRX_CE = LO
Data Package
SPI - programming
uController loading ADDR ADDR PAYLOAD

and PAYLOAD data
(Configuration register if
changes since last TX/RX)
TRX_CE NO
= HI ?
YES
Transmitter is
powered up
nRF ShockBurst TX
DR is
Generate CRC and preamble set low
Pre-
Sending package after pre- ADDR PAYLOAD CRC
amble
DR is set high when completed amble
NO
AUTO_ YES
TRX_CE
RETRAN
NO = HI ?
= HI ?
Bit in configuration
register
YES
Figure 3 Flowchart ShockBurstTM transmit of nRF905.
NB: DR is set low under the following conditions after it has been set high:
• If TX_EN is set low
• If PWR_UP is set low
5.5 Typical ShockBurstTM RX
1. ShockBurstTM RX is selected by setting TRX_CE high and TX_EN low.

2. After 650µs nRF905 is monitoring the air for incoming communication.
3. When the nRF905 senses a carrier at the receiving frequency, Carrier
Detect (CD) pin is set high.
4. When a valid address is received, Address Match (AM) pin is set high.
5. When a valid packet has been received (correct CRC found), nRF905
removes the preamble, address and CRC bits, and the Data Ready (DR)
pin is set high.
6. MCU sets the TRX_CE low to enter standby mode (low current mode).
7. MCU can clock out the payload data at a suitable rate via the SPI interface.
8. When all payload data is retrieved, nRF905 sets Data Ready (DR) and
Address Match (AM) low again.
9. The chip is now ready for entering ShockBurstTM RX, ShockBurstTM TX or
power down mode.
If TX_EN is set high while TRX_CE is kept high, the nRF905 would enter
ShockBurstTMTX and start a transmission according to the present contents in the SPI-
registers.
If TRX_CE or TX_EN is changed during an incoming packet, the nRF905 changes

mode immediately and the packet is lost. However, if the MCU is sensing the Address
Match (AM) pin, it knows when the chip is receiving an incoming packet and can
therefore decide whether to wait for the Data Ready (DR) signal or enter a different
mode.
To avoid spurious address matches it is recommended that the address length be 24

bits or higher in length. Small addresses such as 8 or 16 bits can often lead to
statistical failures due to the address being repeated as part of the data packet. This
can be avoided by using a longer address.
Each byte within the address should be unique. Repeating bytes within the address
reduces the effectiveness of the address and increases its susceptibility to noise hence
increasing the packet error rate. The address should also have several level shifts (i.e.
10101100) to reduce the statistical effect of noise and hence reduce the packet error
rate.
Radio in Standby
TX_EN = LO
PWR_UP = HI
TRX_CE NO
= HI ?
YES
Receiver is
powered up
Receiver
Sensing for incomming data
CD is set high if carrier
Data Package
NO Correct Pre-
ADDR PAYLOAD CRC
ADDR? amble
YES
AM is set
high
Receiving
data
NO Correct
AM is set low
CRC?
DR and AM are DR and AM are
set low set low
YES
DR high is
set high MCU clocks out payload via MCU clocks out payload via PAYLOAD
the SPI interface the SPI interface
TRX_CE YES RX Remains Radio enters

= HI ? On STBY
NO
Figure 4 Flowchart ShockBurstTM receive of nRF905.
5.6 Power Down Mode

In power down the nRF905 is disabled with minimal current consumption, typically
less than 2.5µA. When entering this mode the device is not active which will
minimize average current consumption and maximizing battery lifetime. The
configuration word content is maintained during power down.
5.7 Standby Mode

Standby mode is used to minimize average current consumption while maintaining
short start up times to ShockBurstTM RX and ShockBurstTM TX. In this mode part of
the crystal oscillator is active. Current consumption is dependent on crystal frequency,
Ex: IDD= 12µA @4MHz and IDD =46µA @20MHz. If the uP-clock (pin 3) of nRF905
is enabled, current consumption increases and is dependent on the load capacitance
and frequency. The configuration word content is maintained during standby.
6 DEVICE CONFIGURATION
All configuration of the nRF905 is via the SPI interface. The interface consists of five
registers; a SPI instruction set is used to decide which operation shall be performed.
The SPI interface can be activated in any mode however Nordic Semiconductor ASA
recommends the chip be in standby or power down mode.
6.1 SPI Register Configuration

The SPI interface consists of five internal registers. A register read-back mode is
implemented to allow verification of the register contents.
MISO
MOSI
SCK EN
I/O-reg
DTA STATUS-REGISTER
CSN
CLK
EN
RF - CONFIGURATION
DTA
REGISTER
CLK
EN
DTA TX-ADDRESS
CLK
EN
DTA TX-PAYLOAD
CLK
EN
DTA RX-PAYLOAD
CLK
Figure 5 SPI – interface and the five internal registers.
Status – Register
Register contains status of Data Ready (DR) and Address Match (AM).
RF – Configuration Register
Register contains transceiver setup information such as frequency and output power
ext.
TX – Address
Register contains address of target device. How many bytes used is set in the
configuration register.
TX – Payload
TM
Register containing the payload information to be sent in a ShockBurst packet.
How many bytes used is set in the configuration register.
RX – Payload
Register containing the payload information derived from a received valid
ShockBurst TM packet. How many bytes used is set in the configuration register. Valid
data in the RX-Payload register is indicated with a high Date Ready (DR) signal.
6.2 SPI Instruction Set

The available commands to be used on the SPI interface is shown below. Whenever
CSN is set low the interface expects an instruction. Every new instruction must be
started by a high to low transition on CSN.
Instruction set for the nRF905 SPI Serial Interface

Instruction Name Instruction Operation
Format
W_CONFIG 0000 AAAA Write Configuration-register. AAAA indicates which byte
(WC) the write operation is to be started from. Number of bytes
depends on start address AAAA.
R_CONFIG 0001 AAAA Read Configuration-register. AAAA indicates which byte
(RC) the read operation is to be started from. Number of bytes
depends on start address AAAA.
W_TX_PAYLOAD 0010 0000 Write TX-payload: 1 – 32 bytes. A write operation will
(WTP) always start at byte 0.
R_TX_PAYLOAD 0010 0001 Read TX-payload: 1 – 32 bytes. A read operation will
(RTP) always start at byte 0.
W_TX_ADDRESS 0010 0010 Write TX-address: 1 – 4 bytes. A write operation will
(WTA) always start at byte 0.
R_TX_ADDRESS 0010 0011 Read TX-address: 1 – 4 bytes. A read operation will
(RTA) always start at byte 0
R_RX_PAYLOAD 0010 0100 Read RX-payload: 1 – 32 bytes. A read operation will
(RRP) always start at byte 0.
CHANNEL_CONFIG 1000 pphc Special command for fast setting of CH_NO,
(CC) cccc cccc HFREQ_PLL and PA_PWR in the CONFIGURATION
REGISTER. CH_NO= ccccccccc, HFREQ_PLL = h
PA_PWR = pp
STATUS REGISTER N.A. The content of the status-register (S[7:0]) will always be
read to MISO after a high to low transition on CSN as
shown in Figure 6 and 7.
Table 7 Instruction set for the nRF905 SPI interface.
A read or a write operation may operate on a single byte or on a set of succeeding

bytes from a given start address defined by the instruction. When accessing
succeeding bytes one will read or write MSB of the byte with the smallest byte
number first.
6.3 SPI Timing

The interface supports SPI mode 0. SPI operation and timing is given in Figure 6 to
Figure 8 and in Table 8. The device must be in one of the power saving modes for the
configuration registers to be read or written to.
CSN
SCK
MOSI C7 C6 C5 C4 C3 C2 C1 C0
MISO S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8
Figure 6 SPI read operation.
CSN
SCK
MOSI C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8
MISO S7 S6 S5 S4 S3 S2 S1 S0
Figure 7 SPI write operation.
Tcwh
CSN
Tcc Tch Tcl Tcch

SCK
Tdh
Tdc
MOSI C7 C6 C0
Tcsd Tcd Tcdz

MISO S7 S0
Figure 8 SPI NOP timing diagram.
PARAMETER SYMBOL MIN MAX UNITS

Data to SCK Setup Tdc 5 ns
SCK to Data Hold Tdh 5 ns
CSN to Data Valid Tcsd 45 ns
SCK to Data Valid Tcd 45 ns
SCK Low Time Tcl 40 ns
SCK High Time Tch 40 ns
SCK Frequency Tsck DC 10 MHz
SCK Rise and Fall Tr,Tf 100 ns
CSN to SCK Setup Tcc 5 ns
SCK to CSN Hold Tcch 5 ns
CSN Inactive time Tcwh 500 ns
CSN to Output High Z Tcdz 45 ns
Table 8 SPI timing parameters (Cload = 10pF).
6.4 RF – Configuration Register Description

Parameter Bitwidth Description
CH_NO 9 Sets center freq. together with HFREQ_PLL (default = 001101100b = 108d).
fRF = ( 422.4 + CH_NOd /10)*(1+HFREQ_PLLd) MHz
HFREQ_ 1 Sets PLL in 433 or 868/915 MHz mode (default = 0).
PLL '0' – Chip operating in 433MHz band
'1' – Chip operating in 868 or 915 MHz band
PA_PWR 2 Output power (default = 00).
'00' -10dBm
'01' -2dBm
'10' +6dBm
'11' +10dBm
RX_RED_ 1 Reduces current in RX mode by 1.6mA. Sensitivity is reduced (default = 0).
PWR '0' – Normal operation
'1' – Reduced power
AUTO_ 1 Retransmit contents in TX register if TRX_CE and TXEN are high (default = 0).
RETRAN '0' – No retransmission
'1' – Retransmission of data packet
RX_AFW 3 RX-address width (default = 100).
'001' – 1 byte RX address field width
'100' – 4 byte RX address field width
TX_AFW 3 TX-address width (default = 100).
'001' – 1 byte TX address field width
'100' – 4 byte TX address field width
RX_PW 6 RX-payload width (default = 100000).
'000001' – 1 byte RX payload field width
.
TX_PW 6 TX-payload width (default = 100000).
'000001' – 1 byte TX payload field width
.
RX_ 32 RX address identity. Used bytes depend on RX_AFW (default = E7E7E7E7h).
ADDRESS
UP_CLK_ 2 Output clock frequency (default = 11).
FREQ '00' – 4MHz
'01' – 2MHz
'10' – 1MHz
'11' – 500kHz
UP_CLK_ 1 Output clock enable (default = 1).
EN '0' – No external clock signal available
'1' – External clock signal enabled
XOF 3 Crystal oscillator frequency. Must be set according to external crystal resonant-
frequency (default = 100).
'000' – 4MHz
'001' – 8MHz
'010' – 12MHz
'011' – 16MHz
'100' – 20MHz
CRC_EN 1 CRC – check enable (default = 1).
'0' – Disable
'1' – Enable
CRC_ 1 CRC – mode (default = 1).
MODE '0' – 8 CRC check bit
'1' – 16 CRC check bit
Table 9 Configuration-register description.
6.5 Register Contents
RF-CONFIG_REGISTER (R/W)
Byte # Content bit[7:0], MSB = bit[7] Init value
0 CH_NO[7:0] 0110_1100
1 bit[7:6] not used, AUTO_RETRAN, RX_RED_PWR, PA_PWR[1:0], 0000_0000
HFREQ_PLL, CH_NO[8]
2 bit[7] not used, TX_AFW[2:0] , bit[3] not used, RX_AFW[2:0] 0100_0100
3 bit[7:6] not used, RX_PW[5:0] 0010_0000
4 bit[7:6] not used, TX_PW[5:0] 0010_0000
5 RX_ADDRESS (device identity) byte 0 E7
9 CRC_MODE,CRC_EN, XOF[2:0], UP_CLK_EN, UP_CLK_FREQ[1:0] 1110_0111
TX_PAYLOAD (R/W)
0 TX_PAYLOAD[7:0] X
1 TX_PAYLOAD[15:8] X
- - X
- - X
TX_ADDRESS (R/W)
0 TX_ADDRESS[7:0] E7
RX_PAYLOAD (R)
0 RX_PAYLOAD[7:0] X
1 RX_PAYLOAD[15:8] X
- X
- X
STATUS_REGISTER (R)
0 AM, bit [6] not used, DR, bit [0:4] not used X
Table 10 RF register contents.

The length of all registers is fixed. However, the bytes in TX_PAYLOAD,
RX_PAYLOAD, TX_ADDRESS and RX_ADDRESS used in ShockBurst TM RX/TX
are set in the configuration register. Register content is not lost when the device enters
one of the power saving modes.
7 IMPORTANT TIMING DATA

The following timing must be obeyed during nRF905 operation.
7.1 Device Switching Times
nRF905 timing Max.

PWR_DWN Î ST_BY mode 3 ms
STBY Î TX ShockBurst™ 650 µs
STBY Î RX ShockBurst™ 650 µs
RX ShockBurst™ Î TX ShockBurst™ 550 1µs
TX ShockBurst™ Î RX ShockBurst™ 550 1µs
Notes to table:
1) RX to TX or TX to RX switching is available without re-programming of the RF
configuration register. The same frequency channel is maintained.
Table 11 Switching times for nRF905.
7.2 ShockBurstTM TX timing
M OSI
CSN
PW R_U P
TX_EN
TRX_CE
TX DATA
T IM E
P r o g r a m m in g o f T0 T1 T2 T3
T r a n s m it t e d D a t a 1 0 0 k b p s
C o n f i g u r a ti o n R e g is t e r
M a n c h e s te r E n c o d e d
a n d T X D a ta R e g is te r
T0 = R a d io E n a b l e d
T1 = T 0 + 1 0 u S M in im u m T R X _ C E p u ls e
T2 = T 0 + 6 5 0 u S . S t a r t o f T X D a t a t r a n s m is s io n
T3 = E n d o f D a ta P a c k e t, e n te r S ta n d b y m o d e
Figure 9 Timing diagram for standby to transmit.
After a data packet has finished transmitting the device will automatically enter
Standby mode and wait for the next pulse of TRX_CE. If the Auto Re-Transmit
function is enabled the data packet will continue re-sending the same data packet until
TRX_CE is set low.
7.3 ShockBurstTM RX timing

PW R _U P
TX_EN
TRX_CE
RX DATA
CD
AM
DR
650uS
T IM E
6 5 0 u S to e n te r R X
m o d e fro m T0 T1 T2 T3
T R X _ C E b e in g s e t
h ig h .
T 0 = R e c e iv e r E n a b l e d - L is t e n in g f o r D a t a
T 1 = C a r r ie r D e t e c t f in d s a c a r r ie r
T 2 = A M - C o rre c t A d d re s s F o u n d
T 3 = D R - D a t a p a c k e t w it h c o r r e c t A d d r e s s / C R C
Figure 10 Timing diagram for standby to receiving.
After the Data Ready (DR) has been set high a valid data packet is available in the RX
data register. This may be clocked out in RX mode or standby mode. After the data
has been clocked out via the SPI interface the Data Ready (DR) and Address Match
(AM) pins are reset to low.
The RX register is reset if the PWR_UP pin is taken low or if the device is switched
into TX mode i.e. TXEN is taken high. This will also results in the Data Ready(DR)
and Address Match (AM) pins being reset to low.
7.4 Preamble
In each data-packet transmitted by the nRF905 a preamble is added automatically.
The preamble is a predefined bit-sequence used to adjust the receiver for optimal
performance. A ten-bit sequence is used as preamble in nRF905. The length of the
preamble, tpreamble, is then 200µs.
7.5 Time On Air

The time-on-air is the sum of the radio start-up time and the data-packet length. The
length of the preamble, address field, payload and CRC-checksum give the data-
packet length while the radio start-up time is given in Table 11. While preamble
length and start-up time are fixed the user sets the other parameters in the RF-
configuration register. The below equation shows how to calculate TOA
N address + N payload + N CRC

TOA = t startup + t preamble +
BR
tstartup and tpreamble are RF-start-up time and preamble time respectively. Naddress, Npayload
and NCRC are numbers of bits in the address, payload and CRC-checksum while BR is
the bitrate, which is equal to 50kbps.
8 PERIPHERAL RF INFORMATION
8.1 Crystal Specification
Tolerance includes initially accuracy and tolerance over temperature and aging.
Frequency CL ESR C0max Tolerance @ Tolerance @

868/915 MHz 433 MHz
4MHz 8pF – 16pF 150Ω 7.0pF ±30ppm ±60ppm
Table 12 Crystal specification of nRF905.

To achieve a crystal oscillator solution with low power consumption and fast start-up
time, it is recommended to specify the crystal with a low value of crystal load
capacitance. Specifying a lower value of crystal parallel equivalent capacitance,
Co=1.5pF is also good, but this can increase the price of the crystal itself. Typically
Co=1.5pF at a crystal specified for Co_max=7.0pF.
The crystal load capacitance, CL, is given by:
C1 '⋅C 2 '
CL = , where C1 ' = C1 + C PCB1 + C I 1 and C 2 ' = C 2 + C PCB 2 + C I 2
C1 '+C 2 '
C1 and C2 are 0603 SMD capacitors as shown in the application schematics. CPCB1 and
CPCB2 are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen
into the XC1 and XC2 pin respectively; the value is typical 1pF.
8.2 External Clock Reference

An external reference clock, such as a MCU clock, may be used instead of a crystal.
The clock signal should be applied directly to the XC1 pin, the XC2 pin can be left
high impedance. When operating with an external clock instead of a crystal the clock
must be applied in standby mode to achieve low current consumption. If the device is
set into standby mode with no external clock or crystal then the current consumption
will increase up to a maximum of 1mA.
8.3 Microprocessor Output Clock

By default a microprocessor clock output is provided. Providing an output clock will
increase the current consumption in standby mode. The current consumption in
standby will depend on frequency and load of external crystal, frequency of output
clock and capacitive load of the provided output clock. Typical current consumption
values are found in Table 5.
8.4 Antenna Output

The “ANT1 & ANT2” output pins provide a balanced RF output to the antenna. The
pins must have a DC path to VDD_PA, either via a RF choke or via the center point
in a dipole antenna. The load impedance seen between the ANT1/ANT2 outputs
should be in the range 200-700Ω. The optimum differential load impedance at the
antenna ports is given as:
900MHz 225Ω+j210
430MHz 300Ω+j100
A low load impedance (for instance 50Ω) can be obtained by fitting a simple
matching network or a RF transformer (balun). Further information regarding balun
structures and matching networks may be found in the Application Examples chapter.
8.5 Output Power Adjustment

The power amplifier in nRF905 can be programmed to four different output power
settings by the configuration register. By reducing output power, the total TX current
is reduced.
Power setting RF output power DC current consumption

00 -10 dBm 9.0 mA
01 -2 dBm 14.0 mA
10 6 dBm 20.0 mA
11 10 dBm 30.0 mA
Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 400 Ω.
Table 13 RF output power setting for the nRF905.
8.6 Modulation
The modulation of nRF905 is Gaussian Frequency Shift Keying (GFSK) with a data-
rate of 100kbps. Deviation is ±50kHz. GFSK modulation results in a more bandwidth
effective transmission-link compared with ordinary FSK modulation.
The data is internally Manchester encoded (TX) and Manchester decoded (RX). That
is, the effective symbol-rate of the link is 50kbps. By using internally Manchester
encoding, no scrambling in the microcontroller is needed.
8.7 Output Frequency

The operating RF-frequency of nRF905 is set in the configuration register by CH_NO
and HFREQ_PLL. The operating frequency is given by:
f OP = (422.4 + (CH _ NO / 10)) ⋅ (1 + HFREQ _ PLL) MHz
When HFREQ_PLL is ‘0’ the frequency resolution is 100kHz and when it is ‘1’ the
resolution is 200kHz.
The application operating frequency has to be chosen to apply with the Short Range
Devise regulation in the area of operation.
Operating frequency HFREQ_PLL CH_NO

430.0 MHz [0] [001001100]
433.1 MHz [0] [001101011]
433.2 MHz [0] [001101100]
434.7 MHz [0] [001111011]
862.0 MHz [1] [001010110]

868.2 MHz [1] [001110101]
868.4 MHz [1] [001110110]
869.8 MHz [1] [001111101]
902.2 MHz [1] [100011111]

902.4 MHz [1] [100100000]
927.8 MHz [1] [110011111]
Table 14 Examples of real operating frequencies.
8.8 PCB Layout and Decoupling Guidelines

nRF905 is an extremely robust RF device due to internal voltage regulators and
requires the minimum of RF layout protocols. However the following design rules
should still be incorporated into the layout design.
A PCB with a minimum of two layers including a ground plane is recommended for
optimum performance. The nRF905 DC supply voltage should be decoupled as close
as possible to the VDD pins with high performance RF capacitors. It is preferable to
mount a large surface mount capacitor (e.g. 4.7µF tantalum) in parallel with the
smaller value capacitors. The nRF905 supply voltage should be filtered and routed
separately from the supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD
connections and VDD bypass capacitors must be connected as close as possible to the
nRF905 IC. For a PCB with a topside RF ground plane, the VSS pins should be
connected directly to the ground plane. For a PCB with a bottom ground plane, the
best technique is to place via holes as close as possible to the VSS pins. A minimum
of one via hole should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the crystal or
the power supply lines.
A fully qualified RF-layout for the nRF905 and its surrounding components,
including antennas and matching networks, can be downloaded from
www.nordicsemi.no.
9 nRF905 FEATURES
9.1 Carrier Detect.
When the nRF905 is in ShockBurst TM RX, the Carrier Detect (CD) pin is set high if a
RF carrier is present at the channel the device is programmed to. This feature is very
effective to avoid collision of packets from different transmitters operating at the
same frequency. Whenever a device is ready to transmit it could first be set into
receive mode and sense whether or not the wanted channel is available for outgoing
data. This forms a very simple listen before transmit protocol. Operating Carrier
Detect (CD) with Reduced RX Power mode is an extremely power efficient RF
system. Typical Carrier Detect level (CD) is typically 5dB lower than sensitivity, i.e.
if sensitivity is –100dBm then the Carrier Detect function will sense a carrier wave as
low as –105dBm. Below –105dBm the Carrier Detect signal will be low, i.e. 0V.
Above –95dBm the Carrier Detect signal will be high, i.e. Vdd. Between
approximately -95 to -105 the Carrier Detect Signal will toggle.
9.2 Address Match

When the nRF905 is in ShockBurst TM RX mode, the Address Match (AM) pin is set
high as soon as an incoming packet with an address that is identical with the device’s
own identity is received. With the Address Match pin the controller is alerted that the
nRF905 is receiving data actually before the Data Ready (DR) signal is set high. If the
Data Ready (DR) pin is not set high i.e. the CRC is incorrect then the Address Match
(AM) pin is reset to low at the end of the received data packet. This function can be
very useful for an MCU. If Address Match (AM) is high then the MCU can make a
decision to wait and see if Data Ready (DR) will be set high indicating a valid data
packet has been received or ignore that a possible packet is being received and switch
modes.
9.3 Data Ready

The Data Ready (DR) signal makes it possible to largely reduce the complexity of the
MCU software program.
In ShockBurst TM TX, the Data Ready (DR) signal is set high when a complete packet
is transmitted, telling the MCU that the nRF905 is ready for new actions. It is reset to
low at the start of a new packet transmission or when switched to a different mode i.e.
receive mode or standby mode.
In ShockBurst TM TX Auto Retransmit the Data Ready (DR) signal is set high at the
beginning of the pre-amble and is set low at the end of the preamble. The Data Ready
(DR) signal therefore pulses at the beginning of each transmitted data packet.
In ShockBurst TM RX, the signal is set high when nRF905 has received a valid packet,
i.e. a valid address, packet length and correct CRC. The MCU can then retrieve the
payload via the SPI interface. The Data Ready (DR) pin is reset to low once the data
has been clocked out of the data buffer or the device is switched to transmit mode.
9.4 Auto Retransmit

One way to increase system reliability in a noisy environment or in a system without
collision control is to transmit a packet several times. This is easily accomplished with
the Auto Retransmit feature in nRF905. By setting the AUTO_RETRAN bit to “1” in
the configuration register, the circuit keeps sending the same data packet as long as
TRX_CE and TX_EN are high. As soon as TRX_CE is set low the device will finish
sending the packet it is currently transmitting and then return to standby mode.
9.5 RX Reduced Power Mode

To maximize battery lifetime in application where the nRF905 high sensitivity is not
necessary; nRF905 offers a built in reduced power mode. In this mode, the receive
current consumption reduces from 12.5mA to only 10.5mA. The sensitivity is reduced
to typical –85dBm, ±10dB. Some degradation of the nRF905 blocking performance
should be expected in this mode. The reduced power mode is an excellent option
when using Carrier Detect to sense if the wanted channel is available for outgoing
data.
10 PACKAGE OUTLINE
nRF905 uses the QFN 32L 5x5 green package with a mat tin finish. Dimensions are in
mm. Recommended soldering reflow profile can be found in application note
nAN400-08, QFN soldering reflow guidelines, www.nordicsemi.no.
Package Type A A1 A2 b D E e J K L
QFN32 Min 0.8 0.0 0.65 0.18 3.2 3.2 0.3
(5x5 mm) typ. 0.23 5 BSC 5 BSC 0.5 BSC 3.3 3.3 0.4
Max 0.9 0.05 0.69 0.3 3.4 3.4 0.5
Figure 11 nRF905 package outline.
10.1 Package marking
n R F B X
D D D D D D
Y Y W W L L
Figure 12 nRF905 package marking layout
Abbreviations:
DDDDDD – Product number, e.g. 905
B Build Code, i.e. unique code for silicon revision, production site,
package type and test platform
X – "X" grade, i.e. Engineering Samples (optional)
YY – 2 digit Year number
WW – 2 digit Week number
LL – 2 letter wafer lot number code
11 APPLICATION EXAMPLES
11.1 Differential Connection to a Loop Antenna
aaaaaaaa
VDD
C7 C5 C6
10nF 33pF 4.7nF
0603 0603 0603
32
31
30
29
28
27
26
25
J1
Loop Antenna, 433MHz
R2 35x20mm
TXEN
VSS
VSS
VSS
VSS
VSS
DVDD_1V2
VDD
22K C12
0603 27pF C9
TXEN
1 24 3.9pF
TRX_C E TRX_C E VSS
2 nRF905 23
PWR_UP PWR_UP IR EF
3 22
uPCLK uPCLK VSS
aaaaaaaa
4 21
VDD VDD ANT2 C10
aaaaaaaa
5 20
CD VSS ANT1 6.8pF
6 19
AM CD VDD_PA
7 18 C3
DR AM VSS
8 17 180pF
SPI_MISO DR VDD VDD
SPI_MOSI C11
MOSI
MISO
C13 4.7pF
SCK
CSN
SPI_SC K
XC1
XC2
VSS
VSS
SPI_C SN 27pF
U1
nRF905
9
10
11
12
13
14
15
16
C8
33pF
0603
C4
3.3nF
0603
X1
16 MHz
R1
1M
C1 C2
22pF 22pF
0603 0603
aaaaaaaa
Figure 13 nRF905 Application schematic, differential connection to a loop antenna

(433MHz).
Component Description Size Value Tol. Units

C1 NP0 ceramic chip capacitor, (Crystal oscillator) 0603 22 ±5% pF
C3 NP0 ceramic chip capacitor, (PA supply decoupling) 0603 180 ±5% pF
C4 X7R ceramic chip capacitor, (PA supply decoupling) 0603 3.3 ±10% nF
C5 NP0 ceramic chip capacitor, (Supply decoupling) 0603 33 ±5% pF
C6 X7R ceramic chip capacitor, (Supply decoupling) 0603 4.7 ±10% nF
C7 X7R ceramic chip capacitor, (Supply decoupling) 0603 10 ±10% nF
C9 NP0 ceramic chip capacitor, (Antenna tuning) 0603 3.9 ±0.1 pF
C12 NP0 ceramic chip capacitor, (Antenna tuning) 0603 27 ±5% pF
C13 NP0 ceramic chip capacitor, (Antenna tuning) 0603 27 ±5% pF
R1 0.1W chip resistor, (Crystal oscillator bias) 0603 1 ±5% MΩ
R2 0.1W chip resistor, (Reference bias) 0603 22 ±1% kΩ
U1 nRF905 Transceiver QFN32L/5x5
X1 Crystal, CL = 12pF LxWxH = 16 ±60ppm MHz
4.0x2.5x0.8
Table 15 Recommended external components, differential connection to a loop

antenna (433MHz).
11.2 PCB Layout Example; Differential Connection to a Loop Antenna
Figure 14 shows a PCB layout example for the application schematic in Figure 13. A
double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on
the bottom layer. Additionally, there are ground areas on the component side of the
board to ensure sufficient grounding of critical components. A large number of via
holes connect the top layer ground areas to the bottom layer ground plane. There is no
ground plane beneath the antenna.
No components in bottom layer
a) Top silk screen b) Bottom silk screen
c) Top view d) Bottom view
Figure 14 PCB layout example for nRF905, differential connection to a loop antenna.
www.nordicsemi.no.
Ω antenna
11.3 Single ended connection to 50Ω
aaaaaaaa
868/915MHz 433MHz
C3 33pF, ±5% 180pF, ±5%
C9 3.9pF, ±0.25pF 18pF, ±5%
C10 3.9pF, ±0.25pF 18pF, ±5%
C11 Optional Optional
C12 2.2pF, ±5% 6.8pF, ±5%
VDD C13 Optional Optional
L1 12nH, 5% 12nH, 5%
C7 C5 C6
10nF 33pF 4.7nF L2 18nH, 5% 39nH, 5%
L3 18nH, 5% 39nH, 5%
32
31
30
29
28
27
26
25
C9 C13
R2
VSS
VSS
VSS
VSS
VSS
DVDD_1V2
TXEN
VDD
22K Optional
C12
aaaaaaaa
L2
TXEN
1 24 50 ohm RF I/O
TRX_CE TRX_CE VSS
2 nRF905 23
PWR_UP PWR_UP IREF
3 22
uPCLK uPCLK VSS L1
4 21 C11
VDD VDD ANT2
5 20
aaaaaaaa
CD VSS ANT1 Optional

6 19
AM CD VDD_PA
7 18 L3
DR AM VSS C3
8 17
SPI_MISO DR VDD VDD
SPI_MOSI
MOSI
MISO
SPI_SCK
SCK
CSN
XC1
XC2
VSS
VSS
SPI_CSN C10
U1
nRF905
9
10
11
12
13
14
15
16
C8
33pF
C4
3.3nF
X1
16 MHz
R1
1M
C1 C2
22pF 22pF
aaaaaaaa
Figure 15 nRF905 Application schematic, single ended connection to 50Ω antenna by

using a differential to single ended matching network.
It is recommended to add pull up or pull down resistors on signals that can enter a
floating state. For the nRF905 it is recommended to have pull up on the CSN signal
and pull down on the MOSI and SCK signal.
Component Description Size Value Tol. Units

C3 NP0 ceramic chip capacitor, (PA supply decoupling) ±5%
@ 433MHz 0603 180 pF
@ 868MHz 33
@ 915MHz 33
C4 X7R ceramic chip capacitor, (PA supply decoupling) 0603 3.3 ±10% nF
C6 X7R ceramic chip capacitor, (Supply decoupling) 0603 4.7 ±10% nF
C7 X7R ceramic chip capacitor, (Supply decoupling) 0603 10 ±10% nF
C9 NP0 ceramic chip capacitor, (Impedance matching) 0603 pF
@ 433MHz 18 ±5%
@ 868MHz 3.9 <±0.25pF
@ 915MHz 3.9 <±0.25pF
@ 433MHz 18 ±5%
@ 868MHz 3.9 <±0.25pF
@ 915MHz 3.9 <±0.25pF
C11 NP0 ceramic chip capacitor, (Impedance matching) 0603 Not fitted pF
@ 433MHz 6.8 ±5%
@ 868MHz 2.2 ±5%
@ 915MHz 2.2 ±5%
@ 433MHz Not fitted
@ 868MHz Not fitted
@ 915MHz Not fitted
L1 Chip inductor, (Impedance matching) 0603 ±5% nH
@ 433MHz: SRF> 433MHz 12
@ 868MHz: SRF> 868MHz 12
@ 915MHz: SRF> 915MHz 12
L2 Chip inductor, (Impedance matching) 0603 nH
@ 433MHz: SRF> 433MHz 39 ±5%
@ 868MHz: SRF> 868MHz 18 ±5%
@ 915MHz: SRF> 915MHz 18 ±5%
L3 Chip inductor, (Impedance matching) 0603 nH
@ 433MHz: SRF> 433MHz 39 ±5%
@ 868MHz: SRF> 868MHz 12 ±5%
@ 915MHz: SRF> 915MHz 12 ±5%
R1 0.1W chip resistor, (Crystal oscillator bias) 0603 1 ±5% MΩ
R2 0.1W chip resistor, (Reference bias) 0603 22 ±1% kΩ
U1 nRF905 Transceiver QFN32L/5x5
X1 Crystal, CL = 12pF LxWxH = 16 ±30ppm MHz
4.0x2.5x0.8
Table 16 Recommended external components, single ended connection to 50Ω

antenna.
Ω Antenna
11.4 PCB Layout Example; Single Ended Connection to 50Ω
Figure 16 shows a PCB layout example for the application schematic in Figure 15. A
double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on
the bottom layer. Additionally, there are ground areas on the component side of the
board to ensure sufficient grounding of critical components. A large number of via
holes connect the top layer ground areas to the bottom layer ground plane.
No components in bottom layer
b) Bottom silk screen

a) Top silk screen
c) Top view d) Bottom view
Figure 16 PCB layout example for nRF905, single ended connection to 50Ω antenna
by using a differential to single ended matching network.
www.nordicsemi.no.
12 ABSOLUTE MAXIMUM RATINGS

Supply Voltages
VDD.............................. - 0.3V to + 3.6V
VSS .....................................................0V
Input Voltage
VI ..........................- 0.3V to VDD + 0.3V
Output Voltage
VO .........................- 0.3V to VDD + 0.3V
Total Power Dissipation

PD (TA=85°C) ................................ 200mW
Temperatures
Operating temperature ........................................... - 40°C to + 85°C
Storage temperature .............................................. - 40°C to + 125°C
Note: Stress exceeding one or more of the limiting values may cause permanent
damage to the device.
ATTENTION!
Electrostatic sensitive device.
Observe precaution for handling.
13 GLOSSARY OF TERMS
Term Description
ADC Analog to Digital Converter
AM Address Match
CD Carrier Detect
CLK Clock
CRC Cyclic Redundancy Check
DR Data Ready
GFSK Gaussian Frequency Shift Keying
ISM Industrial-Scientific-Medical
kSPS kilo Samples per Second
MCU Micro Controller Unit
PWR_DWN Power Down
PWR_UP Power Up
RX Receive
SPI Serial Programmable Interface
CSN SPI Chip Select Not
MISO SPI Master In Slave Out
MOSI SPI Master Out Slave In
SCK SPI Serial Clock
SPS Samples per Second
STBY Standby
TRX_EN Transmit/Receive Enable
TX Transmit
TX_EN Transmit Enable
Table 17 Glossary of terms.
14 DEFINITIONS
Product Specification Identification Product Status Definition
Objective Product Specification Planned or Under Development. This specification contains
the design objectives for product development.
nRF: Specifications may change in any manner without
notice.
Preliminary Product Specification Engineering Samples and Pre Production series. This
specification contains preliminary data.
nRF: Nordic Semiconductor reserves the right to make
changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification The product is qualified for production. Changes will be
notified according to industry standard criteria for
Product/Process Change Notifications.
Obsolete Product Specification Not In Production. This specification contains specifications
on a product that has been discontinued by Nordic
Semiconductor. The specification is printed for reference
information only.
Table 18 Product status definitions
Nordic Semiconductor ASA reserves the right to make changes without further notice
to the product to improve reliability, function or design. Nordic Semiconductor does
not assume any liability arising out of the application or use of any product or circuits
described herein.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic Semiconductor ASA customers using or selling these products for use
in such applications do so at their own risk and agree to fully indemnify Nordic
Semiconductor ASA for any damages resulting from such improper use or sale.
Product specification revision date: 06.12.2005

Datasheet order code: 061205nRF905
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder.
YOUR NOTES
Nordic Semiconductor ASA – World Wide Distributors
For Your nearest dealer, please see http://www.nordicsemi.no
Main Office:
Vestre Rosten 81, N-7075 Tiller, Norway
Phone: +47 72 89 89 00, Fax: +47 72 89 89 89
Visit the Nordic Semiconductor ASA website at http://www.nordicsemi.no
Appendix C
Source Code
delay.h 10/07/2006
/*
delay.h
*/
#ifndef __DELAY_H
#define __DELAY_H
//20MHz
#define dly200n asm("nop")
#define dly400n dly200n;dly200n
#define WaitFor1Us dly200n; dly200n; dly200n; dly200n; dly200n
#define Jumpback asm("goto $ - 2")
#define dly1u dly200n; dly200n; dly200n; dly200n

#define dly2u dly1u; dly1u
void DelayUs(unsigned char x);
void DelayMs(unsigned char cnt);
#endif
1
delay.c 30/07/2006
/*****************************************************************************
*
File: delay.c
Date: July 10, 2006
Author: Dennis Leote
Compiler: Hi-Tech PICC, Hi-Tech Software (http://www.htsoft.com)
Description: This program provide the functions to perform delays between
0 - 255 us, and 0 - 255 ms for a PIC 16f877A u controller with a
20 MHz crystal.
*****************************************************************************
*/
#ifndef __DELAY_C
#define __DELAY_C
#include <pic.h>
#include "delay.h"
unsigned char delayus_variable;
/*
* Function: DelayUs
* Input: 8-bit value which defines the delay time (0 - 255 us)
* Output: None
*
* Description: Will delay execution of further instructions (except
Interrupts)
* for a length of 0 - 255 us defined by x
*/
void DelayUs(unsigned char x)
{
delayus_variable=x;
WaitFor1Us;
asm("decfsz _delayus_variable,f");
Jumpback;
}
/*
* Function: DelayMs
* Input: 8-bit value which defines the delay time (0 - 255 ms)
* Output: None
*
* Description: Will delay execution of further instructions (except
Interrupts)
* for a length of 0 - 255 ms defined by x
*/
void DelayMs(unsigned char cnt)
{
unsigned char i;
do {
i = 4;
do {
DelayUs(250);
DelayUs(57); // fine tuning
} while(--i);
} while(--cnt);
}
#endif
1
mainRx.c 30/07/2006
/*****************************************************************************
*
File: main.c
Date: July 10, 2006
Description: This program runs on th PIC 16f877A uController for use with an
nRF24L01 tranceiver Module configured as a receiver. Information
is accepted in a 30-byte array and each byte is output to a PC
via the UART in 0.5 ms intervals.
*****************************************************************************
*/
#include <pic.h>
#include "Rx24L01.h"
#include "C:\ekg\includes\delay.h"
#include "C:\ekg\includes\uart.h"
#include "C:\ekg\includes\spi.h"
void main(void)
{
spiConfig(); // configure 16f877A SPI
SetupComPort(); // configure 16f877A UART
configure16f877_for_24L01(); // configure 16f877A I/O
configure_Rx24L01(); // configure nRF24L01 receiver
TRISB1 = 0;
RB1 = 0;
while(1) {
while(IRQ); // wait for next received data packet
Rx24L01(); // receive the next data packet and output to PC
}
}
1
mainTx.c 30/07/2006
/*****************************************************************************
*
File: main.c
Date: July 10, 2006
Author: Dennis Loete
Description: This Program performs an A/D conversion on three input channels
into the PIC 16f877A uController in regular 0.5ms intervals and
saves the data in an 30-byte array. Once the array is full. The
information is sent to an nRF24L01 tranceiver via the SPI
interface on the PIC.
*****************************************************************************
*/
#include <pic.h>
#include "Tx24L01.h"
#define CHAN1 1
#define CHAN2 2
#define CHAN3 3
void ekgTxInit(void);
char getData(char);
void convertByteToBits(char);
main()
{
char leads[30], dataToSend[30];
int i, j = 0;
ekgTxInit();
SetupComPort();
configure16f877_for_24L01();
configure_Tx24L01();
PORTD = 0x00;
while(1){
// obtain 10 bytes of data from each of the A/D input channels
for (i = 0; i < 30;) {
leads[i++] = getData(CHAN1); // lead I data
leads[i++] = getData(CHAN2); // lead II data
leads[i++] = getData(CHAN3); // lead III data
// delay 0.5 ms until next conversion.
if (i != 30) {
DelayUs(250);
DelayUs(250);
}
}
// transmit data through nRF24L01
Tx24L01(leads);
// wait until transmission complete

while (IRQ);
}
}
/*
* Function: ekgTxInit
* Input: None
1
mainTx.c 30/07/2006
* Output: None
*
* Description: Configure the PIC A/D for three input channels.
* RA0 = Lead I, RA1 = Lead II, RA5 = Lead III
* RA2 = reference voltage - 0V
* RA3 = reference voltage - 5V
*/
void ekgTxInit(void){
TRISD = 0x00; // output A/D result

TRISA0 = 1; // A/D channel 0
TRISA2 = 1; // Vref-
TRISA3 = 1; // Vref+
ADCON0 = 0x81; // set Fosc/32 and channel 0 (RA0)
ADCON1 = 0x09; // RA0 = Analogue input, Vref+/Vref- = VDD/VSS;
}
/*
* Function: getData
* Input: channel - chooses which channel to perform the A/D conversion
* Output: Result of A/D conversion. Stored in an 8-bit char
*
* Description: Performs the A/D conversion on a single channel defined by
* "channel" input and obtains the lower 8 bits of the 10 bit
* result.
*/
char getData(char channel) {
// select channel
switch(channel) {
case CHAN1: ADCON0 = 0x81; break;
case CHAN2: ADCON0 = 0x89; break;
case CHAN3: ADCON0 = 0xA1; break;
default: break;
}
// begin conversion
DelayUs(50);
ADGO = 1;
while(ADGO);
return ADRESH;
}
/*
* Function: convertByteToBits
* Input: byte_value = single byte
* Output: None
*
* Description: Takes a byte and displays a the value in 8 bits - xxxxxxxx.
* The bits are displayed by sending ascii '0' or '1' through
* the serial port on a PC. PC would use Hyperterminal or some
* similiar software to display the value
*/
void convertByteToBits(char byte_value)
{
char tmp;
char i;
// parse the byte bit-by-bit and send the appropriate '0' or '1' to UART
for (i = 128; i > 0;) {
tmp = byte_value & i;
if (tmp == 0) uartTx('0');
else uartTx('1');
i >>= 1;
2
mainTx.c 30/07/2006
}
uartTx(32);
NEW_LINE; // move cursor to next line
}
3
Rx24L01.c 30/07/2006
/*****************************************************************************
*
File: Rx24L01.c
Date: July 10, 2006
Description: This program provides the functions necessary to interface with
the Nordic Semiconductor nRF24L01 Transceiver modules. The
is configured as a receiver with a 5-byte datapipe address,
datarate of 2Mbps, CRC, Retransmit, and Enhanced Shockburst.
*****************************************************************************
*/
#include <pic.h>
#include "Rx24L01.h"
void byteToBits(char);
/*
* Function: configure16f877_for_24L01
* Input: None
* Output: None
*
* Description: Configures the PIC 16f877A uController to interface with the
* transceiver through the SPI.
*/
void configure16f877_for_24L01(void)
{
spiConfig();
TRISB5 = 1; // IRQ pin
TRISC2 = 0; // CE pin
TRISC1 = 0; // CSN pin
CE = 0;
CSN = 1;
}
/*
* Function: configure_Rx24L01
* Input: None
* Output: None
*
* Description: Configures the nRF24L01 transceiver to perform as a receiver
*/
void configure_Rx24L01(void)
{
wReg(0x00, 0x09); // set this device as PRX
wReg(0x01, 0x3F); // enable auto acknowledge (Tx)
wReg(0x02, 0x03); // enable auto acknowledge (Rx)
wReg(0x03, 0x03); // set address width to 5 Bytes
wReg(0x04, 0x1F); // disable retransmit
wReg(0x05, 0x02); // set channel 2 (default value)
wReg(0x06, 0x0F); // set data rate = 2 Mbps
// set Rx (pipe 1) address to E7E7E7E7E7

CSN = 0;
spiTx(0x2A);
spiTx(0xE7);
spiTx(0xE7);
spiTx(0xE7);
spiTx(0xE7);
spiTx(0xE7);
CSN = 1;
1
Rx24L01.c 30/07/2006
DelayUs(10);
// set Rx (pipe 1) address to C2C2C2C2C2
CSN = 0;
spiTx(0x2B);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
CSN = 1;
DelayUs(10);
wReg(0x11, 0x1E); // set # bytes in payload (pipe 0)
wReg(0x12, 0x1E); // set # bytes in payload (pipe 1)
wReg(0x00, 0x0B); // power up
CE = 1;
}
/*
* Function: Rx24L01
* Input: None
* Output: None
*
* Description: Receives a 30 byte array and sends the information through the
* PIC UART for display on a PC in 0.5 ms intervals.

*/
void Rx24L01(void)
{
int i, data[3];
char status;
CE = 0; // Power down RF front end
CSN = 0;
status = spiTx(0x61); // receive payload
for (i = 0; i < 30;) {
// LeadI data
data[i] = spiRx();
uartTx(data[i++]);
// LeadII data
data[i] = spiRx();
uartTx(data[i++]);
// LeadIII data
data[i] = spiRx();
uartTx(data[i++]);
// delay 0.5 ms
if (i != 30) {
DelayUs(250);
DelayUs(250);
}
}
RB1 ^= 1;
CSN = 1;
DelayUs(10);
flushRx(); // flush Rx FIFO
wReg(0x07, 0x7F); // clear previous interrupts
CE = 1; // power up RF front end
2
Rx24L01.c 30/07/2006
}
/*
* Function: getStatus
* Input: None
* Output: Value of the nRF24L01 Staus register
*
* Description: Obtains the value of the nRF24L01 status register for
debugging
* purposes.
*/
char getStatus(void)
{
char status;
CSN = 0;
status = spiTx(0xFF);
CSN = 1;
DelayUs(10);
return status;
}
/*
* Function: showStatus
* Input: None
* Output: Value of the nRF24L01 Status register
*
* Description: Obtains and displays Status register and sends the value to
* the PIC 16f877A UART for display on PC
*/
char showStatus(void)
{
char status;
CSN = 0;
CSN = 1;
DelayUs(10);
byteToBits(status);
return status;
}
/*
* Function: wReg
* Input: address - addr of nRF24L01 register, value - byte value to be
written
* register at "address"
* Output: Value of Staus register
*
* Description: This function writes an 8-bit value to one of the
configuration
* registers of the nRF24L01. The contents of the "Status"
register
* is returned for debugging purposes.
*/
char wReg(char address, char value)
{
char addr, status;
addr = address | 0x20;

CSN = 0;
status = spiTx(addr);
spiTx(value);
CSN = 1;
DelayUs(10);
3
Rx24L01.c 30/07/2006
return status;
}
/*
* Function: rReg
* Input: address - addr of configuration register to be read
* Output: Contents of the register being addressed.
*
* Description: This function reads the value of the configuration register
* at "address"
*/
char rReg(char address)
{
char reg_value;
CSN = 0;
spiTx(address);
reg_value = spiRx();
CSN = 1;
byteToBits(reg_value);
DelayUs(10);
return reg_value;
}
/*
* Function: flushTx
* Input: None
* Output: None
*
* Description: Flushes the Transmit Stack of any values currently being
stored
*/
void flushTx(void)
{
// flush tx stack
CSN = 0;
spiTx(0xE1);
CSN = 1;
DelayUs(10);
}
/*
* Function: flushRx
* Input: None
* Output: None
*
* Description: Flushes the Receive Stack of any values currently being stored
*/
void flushRx(void)
{
// flush rx stack
CSN = 0;
spiTx(0xE2);
CSN = 1;
DelayUs(10);
}
/*
* Function: readRegisters
* Input: None
* Output: None
*
* Description: Reads the values of the first seven configuration registers
for
* debugging purposes.
*/
void readRegisters(void)
{
4
Rx24L01.c 30/07/2006
uartTx('R');
NEW_LINE;
rReg(0x00);
rReg(0x01);
rReg(0x02);
rReg(0x03);
rReg(0x04);
rReg(0x05);
rReg(0x06);
}
/*
* Function: ByteToBits
* Output: None
*
*/
void byteToBits(char byte_value)
{
char tmp;
char i;
for (i = 128; i > 0;) {

else uartTx('1');
i >>= 1;
}
NEW_LINE;
}
5
Rx24L01.h 29/06/2006
#ifndef __RX24L01_H
#define __RX24L01_H
#define CE RC2 // Chip Enable

#define CSN RC1 // Chip Select NOT
#define IRQ RB5 // Interrupt Request
#define COMMAND 1
#define DATA 0
void configure16f877_for_24L01(void);
void configure_Rx24L01(void);
void Rx24L01(void);
void readRegisters(void);
char getStatus(void);
char showStatus(void);
char wReg(char, char);
char rReg(char);
void flushTx(void);
void flushRx(void);
#endif
1
spi.c 30/07/2006
/*****************************************************************************
*
File: spi.c
Date: July 10, 2006
Description: This file rovides the functions necessary to use the PIC 16f877A
SPI interface running on a 20MHz crystal oscillator.
*****************************************************************************
*/
#include <pic.h>
#include "spi.h"
#include "delay.h"
/*
* Function: spiConfig
* Input: None
* Output: None
*
* Description: Configures the 16f877 SPI
*/
void spiConfig(void)
{
STAT_CKE = 1; // Data transmitted on rising edge of SCK
STAT_SMP = 0; // Input data sampled at middle of data output
time
CKP = 0; // Idle state for clock is a low level
SSPEN = 1; // Enables serial port and configrues SCK, SDO,

SDI, and SS as the source of the serial port pins
SSPM0 = 1; // SPI Master mode, clock = Fosc/16
TRISC5 = 0; // SDO
TRISC3 = 0; // SCK
}
/*
* Function: spiTx
* Input: 8-bit data value
* Output: Value of the nRF24L01 Staus register
*
* Description: This function sends one byte of data to an nRF24L01 tranceiver
* module through the SPI interface. The value of the Status
* register is returned
*/
char spiTx(char data)
{
char buf_value;
SSPBUF = data;
while(!SSPIF);
buf_value = SSPBUF;
SSPIF = 0;
return buf_value;
}
/*
* Function: spiRx
* Input: None
* Output: 8-bit value
*
* Description: Obtains one byte of data from the nRF24L01 tranceiver module
*/
char spiRx(void)
{
1
spi.c 30/07/2006
char value;
TRISC5 = 1;
value = spiTx(0x00);
TRISC5 = 0;
return value;
}
2
spi.h 28/06/2006
#ifndef __SPI_H
#define __SPI_H
void spiConfig(void);
char spiTx(char);
char spiRx(void);
#endif
1
Tx24L01.c 30/07/2006
/*****************************************************************************
*
File: Tx24L01.c
Date: July 10, 2006
Description: This program provides the functions necessary to interface with
the Nordic Semiconductor nRF24L01 Transceiver modules. The
is configured as a transmitter with a 5-byte datapipe address,
datarate of 2Mbps, CRC, Retransmit, and Enhanced Shockburst.
*****************************************************************************
*/
#include <pic.h>
#include "Tx24L01.h"
/*
* Function: configure16f877_for_24L01
* Input: None
* Output: None
*
* Description: Configures the PIC 16f877A uController to interface with the
* transceiver through the SPI.
*/
void configure16f877_for_24L01(void)
{
spiConfig(); // configure the SPI with clock = 20MHz / 16
TRISB5 = 1; // IRQ pin
TRISC2 = 0; // CE pin
TRISC1 = 0; // CSN pin
CE = 0;
CSN = 1;
// RB0 used for debugging

TRISB1 = 0;
RB0 = 0;
}
/*
* Function: configure_Tx24L01
* Input: None
* Output: None
*
* Description: Configures the nRF24L01 transceiver to perform as a
transmitter
*/
void configure_Tx24L01(void)
{
CE = 0;
CSN = 0;
wReg(0x00, 0x08); // set PTX

wReg(0x01, 0x3F); // enable auto acknowledge (Tx)
wReg(0x02, 0x03); // enable auto acknowledge (Rx)
wReg(0x03, 0x03); // set address width to 5 Bytes
wReg(0x04, 0x1F); // four retransmit attempts
wReg(0x05, 0x02); // set channel 2 (default value)
wReg(0x06, 0x0F); // set data rate = 2 Mbps
// set Rx address to E7E7E7E7E7
1
Tx24L01.c 30/07/2006
CSN = 0;
spiTx(0x2A);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
CSN = 1;
DelayUs(50);
// set Tx address to E7E7E7E7E7
CSN = 0;
spiTx(0x30);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
spiTx(0xC2);
CSN = 1;
DelayUs(50);
}
/*
* Function: Tx24L01
* Input: 30-byte array
* Output: None
*
* Description: Transmits the input array
*/
void Tx24L01(char leads[])
{
int i;
wReg(0x07, 0x7F); // clear previous interrupts
wReg(0x00, 0x0A); // power up
flushTx();
// Transmit data
CSN = 0;
spiTx(0xA0);
for(i = 0; i < 30; i++) {
spiTx(leads[i]);
}
CSN = 1;
DelayUs(10);
CE = 1;
DelayUs(20);
CE = 0;
}
/*
* Function: showStatus
* Input: None
* Output: None
*
* Description: Sends the contents of the nRF24L01 status register through
* the UART for display in Hyperterminal - Used for debugging
*/
void showStatus(void)
{
char status;
CSN = 0;
2
Tx24L01.c 30/07/2006
CSN = 1;
DelayUs(10);
byteToBits(status);
}
/*
* Function: wReg
* Input: address - addr of nRF24L01 register, value - byte value to be
written
* register at "address"
* Output: Value of Staus register
*
* Description: This function writes an 8-bit value to one of the
configuration
* registers of the nRF24L01. The contents of the "Status"
register
* is returned for debugging purposes.
*/
char wReg(char address, char value)
{
char addr, status;
addr = address | 0x20;

CSN = 0;
status = spiTx(addr);
spiTx(value);
CSN = 1;
DelayUs(10);
return status;
}
/*
* Function: rReg
* Input: address - addr of configuration register to be read
* Output: Contents of the register being addressed.
*
* Description: This function reads the value of the configuration register
* at "address"
*/
char rReg(char address)
{
char reg_value;
CSN = 0;
spiTx(address);
reg_value = spiRx();
CSN = 1;
byteToBits(reg_value);
DelayUs(10);
return reg_value;
}
/*
* Function: flushTx
* Input: None
* Output: None
*
* Description: Flushes the Transmit Stack of any values currently being
stored
*/
void flushTx(void)
{
// flush tx stack
CSN = 0;
spiTx(0xE1);
CSN = 1;
3
Tx24L01.c 30/07/2006
DelayUs(10);
}
/*
* Function: flushRx
* Input: None
* Output: None
*
* Description: Flushes the Receive Stack of any values currently being stored
*/
void flushRx(void)
{
// flush rx stack
CSN = 0;
spiTx(0xE2);
CSN = 1;
DelayUs(10);
}
/*
* Function: readRegisters
* Input: None
* Output: None
*
* Description: Reads the values of the first seven configuration registers
for
* debugging purposes.
*/
void readRegisters(void)
{
uartTx('R');
NEW_LINE;
rReg(0x00);
rReg(0x01);
rReg(0x02);
rReg(0x03);
rReg(0x04);
rReg(0x05);
rReg(0x06);
}
/*
* Function: ByteToBits
* Output: None
*
*/
void byteToBits(char byte_value)
{
char tmp;
char i;
for (i = 128; i > 0;) {
else uartTx('1');
i >>= 1;
}
NEW_LINE;
}
4
Tx24L01.h 29/06/2006
#ifndef __TX24L01_H
#define __TX24L01_H
#define CE RC2 // Chip Enable

#define CSN RC1 // Chip Select NOT
#define IRQ RB5 // Interrupt Request
#define COMMAND 1
#define DATA 0
void configure16f877_for_24L01(void);
void configure_Tx24L01(void);
void Tx24L01(char data[]);
void readRegisters(void);
void showStatus(void);
char wReg(char, char);
char rReg(char);
void flushTx(void);
void flushRx(void);
#endif
1
uart.c 30/07/2006
/*****************************************************************************
*
File: uart.c
Date: July 10, 2006
Description: This file provides the functions necessary to use the PIC
16f877A
Universal Asynchronous Receiver Transmitter (UART) interface.
*****************************************************************************
*/
#include <pic.h>
#include "uart.h"
/*
* Function: SetupComPort
* Input: None
* Output: None
*
* Description: Will setup COM port for 20Mhz clk with 115200 Baud
*/
void SetupComPort(void)
{
char dummy;
TRISC6 = 1;
TRISC7 = 1;
SPBRG = 10; // 115200 Baud
// SPBRG = (20000000/(16UL * 19200) -1); // 19200 Baud
BRGH = 1; // High data rate for sending

TX9 = 0; // 8-bit transmission
RX9 = 0; // 8-bit reception

SYNC = 0; // Asynchronous
SPEN = 1; // Enable serial port pins
RCIF = 0; // Clear the RCIF interrupt flag

CREN = 1; // Enable reception
TXEN = 1; // Enable the transmitter
dummy = RCREG; // Clear the RCREG

}
/*
* Function: uartTx
* Input: One byte value to transmit
* Output: None
*
* Description: Will transmit a given character defined by txChar
*/
void uartTx(char txChar)
{
while(!TXIF); // Wait while other transmission is over
TXREG = txChar; // Place the given character in tx buffer
ResetRx(); // Clears Interrupt flags
}
/*
* Function: uartRx
* Input: None
1
uart.c 30/07/2006
* Output: One byte value received by UART

*
* Description: Receive a character from object interfaced to by UART
*/
char uartRx(void)
{
char dummy = '\0';
if (RCIF) // If receive interrupt flag is set

{
dummy = RCREG; // Get the character stored in rx buffer
ResetRx(); // Clears the interrupt flags
ResetTx(); // Clears the interrupt flags
}
return dummy;
}
/*
* Function: uartTxLine
* Input: String to be transmitted
* Output: None
*
* Description: Sends a string of characters through the UART one byte at a
time
*/
void uartTxLine(char *line_out)
{
int i;
while(line_out[i] != '\0') {uartTx(line_out[i++]);}
}
/*
* Function: ResetTx
* Input: None
* Output: None
*
* Description: Resets the interrupt flags associated with the UART to prepare
* for next transmission.

*/
void ResetTx(void)
{
TXEN = 0;
TXEN = 1;
}
/*
* Function: ResetRx
* Input: None
* Output: None
*
* Description: Resets the interrupt flags associated with the UART to prepare
* for next reception.
*/
void ResetRx(void)
{
CREN = 0;
CREN = 1;
}
2
uart.h 28/06/2006
#ifndef __UART_H
#define __UART_H
#define NEW_LINE uartTx(10);uartTx(13)

void SetupComPort(void); // Setup for 19200 Baud
void uartTxLine(char*); // Transmit a line
void ResetTx(void); // Reset Transmitter
void ResetRx(void); // Reset Receiver
char uartRx(void); // Receieve a char
void uartTx(char); // Transmit a char
#endif

Wireless ECG Monitoring System Using PIC 16F877A and nRF905

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Wireless ECG Monitoring System Using PIC 16F877A and nRF905

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The University of Victoria

Wireless ECG/EKG Monitoring System

Submitted to Dr. Pan Agathoklis

July 28, 2006

Abstract ------------------------------------------------------------------------------ Page 1

Objective ----------------------------------------------------------------------------- Page 2

Project Design ----------------------------------------------------------------------- Page 3

Hardware ---------------------------------------------------------------------------- Page 3

The Power Supply --------------------------------------------------------- Page 4

Instrumentation Amplifier ----------------------------------------------- Page 5

Operational Amplifiers --------------------------------------------------- Page 5

Filters ------------------------------------------------------------------------ Page 6

Microcontroller ------------------------------------------------------------ Page 8

Transceivers ---------------------------------------------------------------- Page 8

MAX232 -------------------------------------------------------------------- Page 9

Software ------------------------------------------------------------------------------ Page 10

Transmitter Module ------------------------------------------------------- Page 10

Programming the PIC16F877A --------------------------------- Page 10

Analog to Digital Conversion (ADC) ---------------- Page 10

Sampling Rate -------------------------------------------- Page 11

Formatting ------------------------------------------------ Page 11

SPI --------------------------------------------------------- Page 11

RF Transmitter ---------------------------------------------------- Page 12

Receiver Module ---------------------------------------------------------- Page 12

RF Receiver ------------------------------------------------------- Page 12

PC Display ------------------------------------------------------------------ Page 13

X Plot --------------------------------------------------------------- Page 14

Y Plot --------------------------------------------------------------- Page 15

Reliability Considerations ------------------------------------------------ Page 15

Discussion and Recommendations ----------------------------------------------- Page 15

Figure 1 – ECG/EKG Lead Placement ------------------------------------------- Page 1

Figure 2 – Ideal I-Waveform ------------------------------------------------------ Page 1

Figure 3 – Present Day ECG -------------------------------------------------------Page 2

Figure 4 – Excessive Amount of Wires in the Operating Room -------------- Page 2

Figure 5 – Block Diagram of Transmitter and Receiver ----------------------- Page 3

Figure 6 – Power Supply Circuit ------------------------------------------------- Page 4

Figure 7– An Instrumentation Amplifier ---------------------------------------- Page 5

Figure 8 – The AD620 ------------------------------------------------------------- Page 5

Figure 9 – ECG Waveform with 60 Hz not removed -------------------------- Page 6

Figure 10 – High Pass RC Filter -------------------------------------------------- Page 6

Figure 11 – Low Pass RC Filter --------------------------------------------------- Page 6

Figure 12 – 2nd Order Active Butterworth Filter -------------------------------- Page 7

Figure 13 – RS232 voltages --------------------------------------------------------Page 9

Figure 14 – Transmitter Module Block Diagram ------------------------------- Page 10

Figure 15 – Activity Diagram for Transmitter Module ------------------------ Page 12

Figure 16 – Receiver Module Block Diagram ---------------------------------- Page 12

Figure 17 – Single Lead Display (Lead I) --------------------------------------- Page 13

Figure 18 – Multiple Lead Display -----------------------------------------------Page 14

Table 1 – Voltage Requirements ------------------------------------------------- Page 4

Table 2 – Filter Values ------------------------------------------------------------- Page 7

Table 3 – Data Format -------------------------------------------------------------- Page 11

Figure 1 – ECG/EKG Lead Placement

As mentioned above, currently the ECG/EKG machines consist of a minimum of 3 pads

Figure 3 – Present Day ECG

Figure 4 – Excessive Amount of

Figure 5 – Block Diagram of Transmitter and Receiver

Table 1 – Voltage Requirements

Point A is regulated by the 5.1V Zener

Point B, which is regulated to 3.3V,

Figure 7– An Instrumentation Amplifier

The AD620 is an instrumentation amplifier that

Figure 8 – The AD620

Figure 9 – ECG Waveform with 60 Hz not removed