Akai Sansui Manual

Models:
LTA-26C902
LTA-32C902
LTA-37C902
www.akai.ru
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Energy Saving Mode if there is no signal input.
● Multi Language On-Screen Display menu
Ordinary and graphical user interface makes the menu operation more user-friendly
● Power Energy Saving Mode (power management mode)
In PC mode, the LCD TV will automatically power off within 30 seconds and enter into the Power
Energy Saving Mode if there is no VGA signal input. It will automatically exit from the Power Energy
Saving Mode and work again when it received a valid VGA signal or press any button on the
panel/remote control.
● Plug and Play
It is no need to equip any installation software when the product is used as computer terminal display
equipment
● Legerity, convenience, low power consumption
● Digital Photo Album Function(Only for CHD-W260F8P/CHD-W270F8P/ CHD-W320F8P/
CHD-W370F8P)
● Built-in DVD Module（Only for CHD-TD260F8 /CHD-TD270F8/CHD-TD320F8/CHD-TD370F8）
⑴Entirely Compatible to DVD、SVCD、VCD、CD、MP3
⑵Compatible to PAL/NTSC Discs
⑶High quality digital audio coaxial input enable you to feel as if sit in the theatre with the perfect classical
hi-fidelity experience
⑷Automatically delete unsuitable parts according to the chosen play levels (max.8 )(only for DVD discs
with play level control)
⑸As many as 32 subtitles
⑹As many as 8 audios
Unit IC Compositions：
LS08 chassis LCD TV is mainly composed of regulator IC、RF IC、video processor IC、Power Amplify
IC、Analog Video IC、System Control IC and Key Control IC, see this IC frame as below:
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PCB Assembly：
It is mainly composed of TV Board、Remote Control Receiver(Signal Receiver) 、Side AV Board、
K Board and Main Board. Hereunder function introduction to every PCB Assembly：
Numbe Parts Description

r
1 Main Board It is the core of signal processing for LCD TV, which takes responsibility of
Assembly transforming outer signal into the uniform digital signal identified by LCD display
with use of System Control IC. TV and AV signals input from TV Board are
decoded by UOCIII to transport RGB signal which is to be transformed by
TDA8759 modulus to transport 24bit RGB digital signal, then it is to be
transformed by GM1601/GM1501 to produce LVDS signal displayed on the
screen, in addition, signals input from VGA、DVI would directly enter into
GM1501 procedure 、format transformation and on screen display.
5
2 TV Board It is mainly composed of two tuners (main and sub tuners) 、AV/S 、HD signal
Assembly terminals and some peripheral processing IC. The main tuner demodulates RF
signal to IF signal, and the sub tuner produces CVBS signal, all signals are sent to
the main board after transfer.
3 Remote t is composed of one indicator light and one remote control receiver, which enable
Control Users operate the TV conveniently and know its current working status simply with
Receiver a remote control..
Assembly
4 Built-in Power It can transform AC 220V into DC for ICs, including +24V，+12V，+5V and +5VS
Board power supply in standby mode.
Assembly
5 K Board It consists of 7 function buttons by which users can operate the TV freely.
Assembly
6 Screen Screens for LS08 have the built-in adverse transformer which change DC into high
Assembly voltage AC signal to lighten the back light; The LCD screen is used to display the
image after the image signal has been processed by the main board.
,
7 Side AV Board It is used for earphone output, AV input, S input
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CHAPTER TWO MAIN ICs FUNCTION INTRODUCTION
GENERAL INTRODUCTION:
TV Board
Number Location Type Main Function
1 UT1 TMI4-C22P2RW Audio and image intermediate frequency signal
output
2 UT2 TAD5-C2IP1RW Sub picture CVBS signal output
Main Board
3 U302，U303 24LC21A T/SN EEPROM
4 U701 24LC32A T/SN Buffer
5 U306,U307,UA3 FSAV330QSCX Switch selection
6 K201 K7262N Audio surface filter
7 K202 K9352N Audio surface filter
8 U6 TPA3002D2PHPR Audio amplifier
9 U801 AM29LV800DT-70EC Flash，control program inside
10 U700 GM1501-BD Video processor
11 U201 TDA15063H-N1B06557 AV decoder
12 U402 SAA7115HL/V1 Sub channel video decoder
13 U305 SM5302AS-G-ET High definition signal filter
14 U400 TDA8759HV/8/C1 Video signal modulus transformer
15 U5 TDA9178T/N1 Video signal picture amendment
16 U600 MT46V2M32LG-4 Frame buffer
.ICs FUNCTION INTRODUCTION IN DETAILS
Main Tuner (TMI4-C22P2RW)

Pin Definition Description
1 AGC Auto gain control
2 UT NC
3 ADD Ground
4 SCL IIC bus (Clock)
5 SDA IIC bus (Data)
6 NC NC
7 +5V Power supply
8 NC NC
9 30V To produce 0~30V tune voltage
10 NC NC
11 IF Intermediate frequency TV signal
Intermediate frequency TV signal
Sub Tuner (TAD5-C2IP1RW):

Pin Definition Description
2 NC NC
7
3 ADD Ground
4 SCL IIC bus (Clock)
5 SDA IIC bus (Data)
6 NC NC
7 +5V Power supply
8 NC NC
9 33V To produce 0~30V tune voltage
10 NC NC
11 IF Intermediate frequency output (NC)
12 IF Intermediate frequency output (NC)
13 SW0 Band control
14 SW1 Band control
15 NC NC
16 SIF NC
18 VEDIO CVBS signal output
19 +5V Power supply
20 AUDIO NC
GM1501
GM1501is a kind of processing chassis for dual channels image and video, which is mainly used for
LCD displays and integrative TV products. With the resolution of WUXGA, it not only supports PIP
technique, but possesses some IC functions applied to image catch 、process and clock display. It
integrates high velocity AD converter, PLL, high reliability DVI receiver, X86 series miccontrol and LCDS
inverter. See the features as below:
Main Features
● High quality image zoom function;
● Analog RGB signal input interface;
● Intelligent output signal auto identification;
● Integrated high-power PLL output;
● High-reliable self-adaptive DVI input interface;
●4:4:4/4:2:2/CCR656/601 8/16/24bit digital video interface;
● Embedded IC for adjustments of gain、contrast、brightness、color saturation、hue and fleshtone;
● Efficiency in reducing EMI electromagnetism inference;
● Inclined grain processing with small angle;
● High quality video processing;
● Programmable output format;
● Embedded LVDS transport;
● Advanced OSD;
● Embedded micro controller
Pin Description :
Pin Name Description

Analog Signal Input Port
8
L3 AVSYNC ADC vertical synchronization signal input
L4 AHSYNC ADC horizontal synchronization signal input
N2 VGA-SCL VGA lock input
N1 VGA-SDA VGA digital input
D1、D2 RED+、RED- Red analog signal input
C3 SOG Green synchronization signal
C1、C2 GREEN+、- Green analog signal input
B1、B2 BLUE+、BLUE- Blue analog signal input
A2,B3,E3,D3 ADC3.3 ADC3.3Vpower supply
A3，A4 ADC1.8 ADC1.8Vpower supply
A5，B4 ADC-DGND ADC digital ground
C4，D4，E1，E2，E4 ADC-AGND ADC analog ground
DVI Input Output Port
N4 DVI-SCL DDC interface , serial clock signal
N3 DVI-SDA DDC interface ，serial data signal
A6，B6 RXC+，RXC- DVI clock input signal
A8～A10 RX0+～RX2+ DVI input port
B8～B10 RX0-～RX2-
B11 REXT Exterior exit resistance
C6～C11 DVI-3.3 DVI 3.3V power supply
D6、D8～D10 DVI-1.8 DVI 1.8V power supply
A7,A11,B5,B7,C7,D7 DVI-GND DVI ground
D11
Low Bandwidth ADC Port
C13 LBADC-33 ADC3.3Vpower supply
A12，B12，C12 LBADC_IN1～ ADC analog input channel
LBADC_IN3
D12 LBADC_RETURN Channel analog ground
D13 LBADC-GND Power supply voltage analog ground
OCM IC Port
AA1~AA3,Y1~Y3, OCMADDR0～ Address input output port
W1~W3,V1~V4, OCMADDR19
U1~U4,T1~T3
AB1~AB3,AC1~AC3, OCMDATA0~ Data input output port
AD1~AD4,AE1~AE3, OCMDATA15
AF1~AF3
OCM Port Control Signal
R1，T4，P1，P2 ROM_CSn~ Part selection signal
ROM_CS2n
R2 OCM_REn Read enable signal
R3 OCM_WEn Write enable signal
L1 OCM_INT2 Interrupt
L2 OCM_INT1
M1 OCM_UDO OCM data output
M2 OCM_UDI OCM data input
D25 OCM_TIMER1 OCM timer input
9
Standard Definition Video Control Port
D16 SVCLK SV pels clock input
C14 SVHSYNC SV horizontal synchronization signal input
B14 SVVSYNC SV vertical synchronization signal input
A14 SVODD Scan status input
A17 SVDV SV data input
Standard Definition Video Data Port
D14,D15,A15,A16, SVDATA7~ SV ITU656 data input
B15,B16,C15,C16 SVDATA0
Video Control Port
A20 VCLK Video pels clock signal
D19 VHS_CSYNC Video horizontal synchronization signal input
C20 VVS Video vertical synchronization signal input
B20 VODD Scan status input
D20 VDV (VSOG) Video data input
B17 VCLAMP Video clamp enable output
A21,A22,A23,B21, VGRN7~ VGRN0 Green signal or Y signal input
B22,C21,C22,D21
C17,C18,C19,A18 VRED7~ VRED0 Red signal or V/Cr/Pr signal input
A19,B18,B19,D18
B23,B24,B25,A24 VBLU7~ VBLU0 Blue signal or U/Cb/Pb signal input
A25,C23,C24,D24
Screen Control Port
A26 PPWR Screen power control
B26 PBIAS Screen bias control
D26，C25，C26 PWM2 ~PWM0 Pulse width modulation output
AC7 DCLK Pels clock output
AC16 OEXTR Connect external LVDS bias resistance
LVDS Port
AE14~AE16,AE19~ A0-~A3-, A0+~A3+ Low voltage difference data input
AE23,AF13~AF16 B0-~B3-, B0+~B3+
AF19~AF23,AF11
AD14,AD11,AE13 LVDS_SHIELD[5] ~ Low voltage difference protect output
AE11,AC11,AF10 LVDS_SHIELD[0]
AE12,AF12, AC+,AC-,BC+,BC- Low voltage difference protect input
AF20,AE20
Screen Port Power Supply
AD12,AD13,AC12 LVDSB_3.3 LVDS B channel power supply
AC13,AC14,AC15 LVDSB_GND B channel ground
AC20,AC21,AC22 LVDSA_3.3 LVDS A channel power supply
AD19,AC19,AC20 LVDSA_GND A channel ground
AE17 VDDD33_LVDS Analog power supply
AD17 VSSD33_LVDS Analog ground
Clock Composite and Power Supply
G4 XTAL crystal oscillator interface
10
F2 VDDD33_PLL， Digital power supply
H1 VDDD33_SDDS
J1 VDDD33_DDDS
G2 VSSD33_PLL Digital ground
J4 VSSD33_SDDS
K4 VSSD33_DDDS
F4 VDDA33_RPLL Analog power supply
G1 VDDA33_FPLL
H3 VDDA33_SDDS
J3 VDDA33_DDDS
F3 VSSA33_RPLL Analog ground
H4 VSSA33_FPLL
H2 VSSA33_DDDS
J2 VSSA33_DDDS
G3 TCLK Reference clock signal input
K2 ACS_RSET_HD External resistance port
System Signal
K1 RESETn Reset signal
M3，M4 IR0，IR1
P4 MSTR_SCL Main clock output signal
P3 MSTR_SDA Main data output/input signal 信号
R4 EXTCLK External clock input
Frame Storage Interface
U24,U23 FSCLKp,FSCLKn Fine storage clock output
V24,V25 FSRAS,FSCAS Address output
V26 FSWE Write enable port
W26 FSCKE Read enable port
J24 FSVREF Reference voltage input
K26 FSVREFVSS Reference voltage ground
W25 FSVREF Reference voltage input
W24 FSVREFVSS Reference voltage ground
L26 FSDQS Data filter
F24~F26,G23~G26 FSDATA31~ Data input output port
H24~H26,J25,J26, FSDATA0
R24~R26,P24~P26
N23~N26,…….
T24,T25,U25,U26 FSDQM3~ FSDQM0 Data output mark
Y26 FSBKSEL1， Layer address
Y25 FSBKSEL0
AA24~AA26 FSADDR11~ Range address output
AB24~AB26, FSADDR0
AC24~AC26
AD24~AD26
E23, F23, H23, J23, FS_2.5 2.5V power supply
L23,M23,P23, R23,
T23,V23,W23,Y23,
11
AA23,AB23,AC23
K23 VDDA18_DLL 1.8V power supply
K25 VSSA18_DLL Power supply ground
Digit power supply
K10,K11,K16,K17, CORE_1.8 1.8V power supply
L11,L16,T11,T16,
T17,U10,U11,U16,U17
D23, W4,Y4, AA4, IO_3.3 3.3V power supply
AB4,AC4,AC6,D17,
D22,AC8,AC10
K12,K13,K14,K15, D_GND Power ground
L10,L12,L13,L14,
L15,L17,M10,M11,
M12,M13。。。。。。
A1，AC，D5，AC17， NO_CONNECT NC
K3，F1
GM1501Internal Diagram：
TDA8759：
TDA8759 is a triple 8-bit video converter interface. The IC converts a RGB analog signal into a 24bit
RGB or YUV or YCbCr digital signal , or converts a YUV or YCbCr analog signal into a YUV or RGB digital
signal with a sampling rate up to 81 Msps. The IC supports resolutions from 480i and VGA to HDTV and
XGA.
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Main Features:
● Triple 8-bit Analog-to-Digital Converter (ADC)
●Three independent analog video sources up to 81 Msps selectable by I2C-bus
●Auto check on interval scan video signal
●1.8Vand 3.3Vsupplies
● Low gain variation with temperature
●Output format RGB 4:4:4, YUV 4:4:4, YUV 4:2:2 ,CCIR 656 or YUV 4:2:2 semi-planar standard on
output bus；
●I²C bus control
●Programmable clock phase adjustment cells
●Amplifier bandwidth of 100 MHz
●Integrated PLL divider
●Power-Downmode
TDA8759 Internal Diagram：
Pin Description：
1 HREF Horizontal reference output
2 VCLK Video clock output
3,13,21,29, VDDO Video port output supply voltage
37,45,164
13
4,14,22,30 OGND Video port output
38,46,165 ground
7，8，9，10， VPA0~VPA7 Video port A
15，16，17，18
11,116,130,132 VDDC Power supply port
12,117,159 CGND Ground
23~28,31,32 VPB0~VPB7 Video port B
35,36,39~44 VPC0~VPC7 Video port C
47,53,57,58,55 AGND Analog ground
60,66,70,71,75
81,83,85,86,
48,54,59,61,67 VDDA Power supply port
69,76,82,85,87,88
49 REFB/Pb Blue/blue-chrominance channel reference input
52,51,50 B/Pb1~ B/Pb3 Blue/blue-chrominance channel analog input

56 BIAS Bias input
62 REFG/Y Green/green-chrominance channel reference
input
65,64,63 G/Y1~G/Y3 Green/green-chrominance channel analog input
74,73,72 SOG/Y1~SOG/Y3 Sync on green//brightness channel input
77 REFR/Pr Red/red-chrominance channel reference input
80,79,78 R/Pr1~ R/Pr3 Red/red-chrominance channel analog input
89~92,97~101 TST0~TST17 Reserved for test
112,121,122,
124,125,160~163
93 PD Power-down control input
94 OE Output enable input
96 A0 I²C bus address control input
102 COAST PLL control input
103 GAIN Gain input
104 CLAMP Clamp input
105~107 VSYNC1~VSYNC3 Vertical synchronization input
108~110 H(C)SYNC1~ Horizontal (composite)synchronization input
H(C)SYNC3
111 CKEXT External clock input
113 TCLK Reserved for test
114 DIS I²C bus disable control input
118 SDA I²C bus data input/output
119 SCL I²C bus clock input
120,126,127,131 IGND Input digital ground
133,142,148,
123,138,139,145 VDDI Input digital supply voltage
151,157
166 PL PLL disable belock output
167 DE Data enable output
14
168 HS Horizontal synchronization input
169 VS vertical synchronization input
170 CS Color synchronization output
171 ORR/V Red / chrominance ADC output
172 ORB/U Blue /chrominance ADC output
173 ORG/Y Green / chrominance ADC output
174 VAI Video dynamic indication output
175 FREF Scan output
17 VREF Vertical channel reference input
TPA3002D2：
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the TPA3002D2
eliminates the need for external heatsinks when playing music.
Main Features：
● 9W /Ch into an 8Ω load from 12Vsupply;
● Efficient, class D operation eliminates heatsinks and reduces power supply requirements;
●32-step DC volume control from -40db~36db;
●Line outputs for external headphone;
●Thermal and short-circuit protection
Pins Functions：
26, 30 AGND Analog ground for digital/analog cells in core
33 AVCC High-voltage analog power supply（8~14V）
29 AVDD 5V regulated output capable of 100mA output
7 AVDDREF Reference 5V output
13 BSLN Bootstrap I/O left channel

24 BSLP
48 BSRN Bootstrap I/O right channel
37 BSRP
28 COSC I/O for charge/discharge currents onto capacitor for ramp generator
triangle wave
6 LINN Negative differential audio input for left channel
5 LINP Positive differential audio input for left channel
16，17 LOUTN Class-D 1/2-H-bridge negative output for left channel
20，21 LOUTP Class-D 1/2-H-bridge positive output for left channel
34 MODE Input for MODE control. A logic high on this pin places the amplifier in
the variable output mode and the Class-D outputs are disabled. A logic
low on this pin places the amplifier in the Class-D mode and Class-D
stereo outputs are enabled. Variable outputs (VAROUTL and
VAROUTR) are still enabled in Class-D mode to be used as line-level
outputs for external amplifiers.
35 MODE_OUT Output for control of the variable output amplifiers. When the MODE pin
15
(34) is a logic high, the MODE_OUT
pin is driven low. When the MODE pin (34) is a logic low, the
MODE_OUT pin is driven high. This pin is
intended for MUTE control of an external headphone amplifier. Leave
unconnected when not used for
headphone amplifier control.
18,19,42,4 PGNDR,PGNDL Power ground for left channel H-bridge Power ground for right
3 channel H-bridge
14,15,22,2 PVCCL Power supply for left channel H-bridge (tied to pins 22 and 23
3 internally), not connected to PVCCR or AVCC.
38,39,46,4 PVCCR PVCCL 22, 23 – Power supply for left channel H-bridge (tied to pins 14
7 and 15 internally), not connected to PVCCR or AVCC.
PVCCR 38,39 – Power supply for right channel H-bridge (tied to pins 46
and 47 internally), not connected to PVCCL or AVCC.
PVCCR 46, 47 – Power supply for right channel H-bridge (tied to pins
38 and 39 internally), not connected to PVCCL or AVCC.
12 REFGND Ground for gain control circuitry. Connect to AGND. If using a DAC to
control the volume, connect the DAC ground to this terminal.
32 RINP Positive differential audio input for right channel
2 RINN Negative differential audio input for right channel
27 ROSC Current setting resistor for ramp generator. Nominally equal to 1/8*
44,45, ROUTN, ROUTP Class-D 1/2-H-bridge negative output for right channel
40,41 ROUTP 40, 41 O Class-D 1/2-H-bridge positive output for right channel
1 SD Shutdown signal for IC (low = shutdown, high = operational). TTL logic
levels with compliance to VCC.
9 VARDIFF DC voltage to set the difference in gain between the Class-D and
VAROUT outputs. Connect to GND or AVDDREF if VAROUT outputs
are unconnected.
10 VARMAX DC voltage that sets the maximum gain for the VAROUT outputs.
Connect to GND or AVDDREF if VAROUT outputs are unconnected.
31 VAROUTL Variable output for left channel audio. Line level output for driving
external HP amplifier.
32 VAROUTR VAROUTR 32 O Variable output for right channel audio. Line level
output for driving external HP amplifier.
25 VCLAMPL VCLAMPL 25 – Internally generated voltage supply for left channel
bootstrap capacitors.
36 VCLAMPR Internally generated voltage supply for right channel bootstrap
capacitors.
11 VOLUME DC voltage that sets the gain of the Class-D and VAROUT outputs.
8 VREF Analog reference for gain control section.
4 V2P5 2.5-V Reference for analog cells, as well as reference for unused audio
input when using single-ended inputs.
TPA3002D2 Internal Diagram：
16
SM5301AS ：
order Butterworth lowpass filter configuration. The filter characteristics have been optimized for
minimal overshoot and flat group delay, it has a variable cutoff frequency and guaranteed driver-stage
channel gain difference and phase difference values.
Main Features:
● supply voltage：5V±10%；
● _DC voltage level restore sync clamp function
● Output buffer gain switching function: 0, 6dB (input-to-output AC signal gain)
● Channel-to-channel gain difference: 0.5dB(±5% supply voltage variation)；
● Channel-to-channel phase difference: 3.5 degree
● Output signal harmonic distortion (all channels):1.5%
● Cutoff frequency: 5.8 to 37MHz variable
SM5301AS Internal Diagram：
17
Pin Description：
2 GSG1 GOUT/UOUT output buffer gain set input
1 GINA/UINA Analog GINA or UINA signal input. Sync signal is input on SYNCIN
3 GINB/UINB pin.
Analog GINB or UINB signal input. Sync signal is input on SYNCIN
pin.
5 BINA/VINA Analog BINA or VINA signal input. Sync signal is input on SYNCIN
7 BINB/VINB pin.
Analog BINB or VINB signal input. Sync signal is input on SYNCIN
pin
6 GSB1 BOUT/VOUT output buffer gain set input
9 DISABLE Power save function. Built-in pull-down resistor.
10,13,16,19 GND Ground
11 BOUT/VOUT B/V signal output
14 GOUT/UOUT Analog 5V supply
17 ROUT/YINB R/Y signal output
12,15,18,24 VCC Analog 5V supply
20 RFC LPF (lowpass filter) cutoff frequency setting resistor connection
21 VFC LPF (lowpass filter) cutoff frequency setting voltage input
22 MUXSEL Input select signal
23 SYNCIN Filter channel external H-Sync signal input.
26 GSR1 ROUT/YOUT output buffer gain set input
25 RINA/YINA Analog RINA or YINA signal input. Sync signal is input on SYNCIN
27 RINB/YINB pin.
Analog RINB or YINB signal input. Sync signal is input on SYNCIN
pin.
18
4,8,28 NC No connection(leave open or connect to ground)
SAA7115：
The SAA7115 is a video capture device for various applications ranging from small screen products like
e.g. digital set top boxes, personal video recording applications to big screen devices like e.g. LCD
projectors due to it’s improved comb filter performance and 10 bit video output capabilities.
Main Features:
●Six analog inputs, internal analog source selectors;
●Two improved 9 Bit CMOS analog-to-digital converter in differential CMOS style;
●Automatic Clamp Control (ACC) for CVBS, Y and C;
●Enhanced Horizontal and vertical Sync Detection;
●PAL delay line for correcting PAL phase errors;
●Automatic TV/VCR detection;
SAA7115 Internal Diagram：
Pin Function：
1,8,11,17,23,25,33 VDD Supply voltage port
43,51,58,68,75,83
93
2 TDO Test Data Output for Boundary Scan Test (2)
3 TDI Test Data Input for Boundary Scan Test (with internal pull-up)(2)
4 XTOUT crystal oscillator output signal, auxiliary signal
6 XTALO 24.576 (32.11) MHz crystal oscillator output; not connected if XTALI is
19
7 XTALI driven
by an external single-ended oscillator.
Input terminal for 24.576 (32.11) MHz crystal oscillator or connection
of external oscillator with TTL compatible square wave clock signal.
6 VXDD Crystal oscillator power supply

10,12,14,16 AI21~AI24 Analog signal input 21~24
13 AI2D differential input for ADC channel 2 (pins AI24, AI23, AI22, AI21)
19 AI1D differential input for ADC channel 1 (pins AI12, AI11)
20 AI11 analog input 11
18 AI12 analog input 12
5,9,15,21,24,26,38 AGND ground
50,63,76,88,100 VSS
22 AOUT Analog test output (do not connect)
27 CE Chip Enable or RESET input (with internal pull up)
28 LLC line-locked system clock output (27 MHz nominal), for backward
29 LLC2 compatibility,
do not use for new applications
line locked clock/2 output (13.5 MHz nominal) for backward
compatibility, do
not use for new applications
30 RESON RESet Output Not signal
31 SCL IIC serial clock line (with inactive output path)
32 SDA IIC serial data line
34 RTS0 real time status or sync information, controlled by subaddr. “11h and
35 RTS1 12h”
RTS1 35 O real time status or sync information, controlled by
subaddr. “11h and 12h”
36 RTCO Real time control output
37 AMCLK Audio master clock output
39 ASCLK Audio serial clock output
40 ALRCLK Audio lift/right clock output
41 AMXCLK Audio master external clock input
42 ITRDY Target ready input, image port(with internal pull up)
45 ICLK clock output signal for image-port, LCLK of LPB image port mode, or
optional
asynchron. backend clock input
46 IDQ output data qualifier for image port (optional: gated clock output)
47 ITRI image-port output control signal, effects all I-port pins incl. ICLK,
enable and active polarity is under software control (bits IPE in
subaddr. “87”) output path used for Testing: scan output
48 IGP0
20
49 IGP1 general purpose output signal 0; image-port (controlled by subaddr.
“84”,”85”)
general purpose output signal 1; image-port (controlled by subaddr.
“84”,”85”),
same functions as IGP0
52 IGPV multi purpose vertical reference output signal; image-port
(controlled by subaddr. “84”,”85”)
53 IGPH multi purpose horizontal reference output signal; image-port
(controlled by subaddr. “84”,”85”)
54~57,59~62 IPD0~IPD7 image port data output
64~67,69~72 HPD0~HPD7 Host port data I/O, carries UV chrominance information in 16 bit video
I/O modes
80 XTRI X-port output control signal, effects all X-port pins (XPD[7:0], XRH,
XRV, XDQ
and XCLK) enable and active polarity is under software control (bits
XPE in subaddr. “83”)
81,82,84,85, XPD0~XPD7 expansion-port data
89,90,86,87 expansion-port data
91 XRV vertical reference I/O expansion-port:
In ten bit video output mode: this signal represents the video bit 0.
92 XRH horizontal reference I/O expansion-port:
In ten bit video output mode: this signal represents the video bit 1.
94 XCLK clock I/O expansion port
95 XDQ data qualifier I/O expansion port
96 XRDY task flag or read signal from scaler, controlled by XRQT (subaddr.
83H)
97 TRSTN Test ReSeT Not for Boundary Scan Test (with internal pull-up); for
board design
without Boundary Scan connect TRSTN to ‘ground’(1)
98 TCK Test Clock for Boundary Scan Test (with internal pull-up)(2)
99 TMS Test Mode Select for Boundary Scan Test or Scan Test (with internal pull-up)(2)
UOCⅢ(TDA15063H)：
The UOCIII series combines the functions of a Video Signal Processor (VSP) together with a FLASH
embedded TEXT/Control/Graphics 　-Controller (TCG 　-Controller) and US Closed Caption decoder.
Main Features:
●DVB/VSB IF circuit for preprocessing of digital TV signals;
●Video switch with 3 external CVBS inputs and a CVBS output;
●Automatic Y/C signal detector;
●Adaptive digital (4H/2H) PAL/NTSC comb filter for optimum separation of the luminance and the
chrominance signal;
●Picture improvement features with peaking (with switchable center frequency, depeaking, variable
positive/negative peak ratio, variable pre-/overshoot ratio and video dependent coring), dynamic skin tone
control, gamma control and blue and black stretching. All features are available for CVBS, Y/C and
RGB/YPBPR signals.
21
The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to the
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external
band-pass filters can be omitted. In the stereo versions of UOCIII the use of this demodulator is optional
for special applications.
Normally the FM demodulators of the stereo demodulator/decoder part are used (see below).
●The FM-PLL demodulator can be set to centre frequencies of 4.72/5.74 MHz so that a second sound
channel can be demodulated. In such an application it is necessary that an external bandpass filter is
inserted.
●The vision IF and mono intercarrier sound circuit can be used for the demodulation of
FM radio signals. With an external FM tuner also signals with an IF frequency of 10.7
MHz can be demodulated. For the QIP90 versions this is valid only for the “stereo”
versions
●Built-in adaptable brightness delay circuit
●switchable brightness signal transmission rate
Pin Description：
1,2,12,18,28,40 VSS,GND ground
68,81,89,92,95,101
121,125
3,4,45,69,82,88,90, VDD Power supply
91,93,94,96,100,
110,117,118,124
5 VREF_POS_LSL SDAC input signal
6 VREF_NEG_LSL+HPL
7 VREF_POS_LSR+HPR
8 VREF_NEG_HPL+HPR
9 VREF_POS_HPR
10 XTALIN Crystal oscillator input
11 XTALOUT Crystal oscillator output
13 VGUARD/SWIO V-guard input / I/O switch
14 DECDIG decoupling digital supply
15 VP1 decoupling digital supply
16 PH2LF phase-2 filter
17 PH1LF phase-1 filter
19 SECPLL SECAM PLL decoupling
20 DECBG bandgap decoupling
21 EWD/AVL East-West drive output or AVL capacitor
22 VDRB vertical drive B output
23 VDRA vertical drive A output
24 VIFIN1 IF input 1
25 VIFIN2 IF input 2
27 IREF reference current input
29 SIFIN1/DVBIN1 SIF input 1 / DVB input 1 SIF
30 SIFIN2/DVBIN2
31 AGCOUT tuner AGC output
22
32 EHTO EHT / overvoltage protection input
33 AVL/SWO/SSIF/REFO/REFIN Automatic Volume Levelling / switch output reference
output / external reference signal DVB operation
34 AUDIOIN5L audio-5 input (left signal)
35 AUDIOIN5R audio-5 input (right signal)
36 AUDOUTSL audio output for SCART/CINCH (left signal)
37 AUDOUTSR audio output for SCART/CINCH (right signal)
38 DECSDEM decoupling sound demodulator
39 QSSO/AMOUT/AUDEEM QSS intercarrier output / AM output / deemphasis
41 PLLIF PLL filter
42 SIFAGC/DVBAGC AGC sound IF / internal-external AGC for DVB
applications
43 DVBO/IFVO/FMRO Digital Video Broadcast output / IF video output
44 DVBO/FMRO
46 AGC2SIF AGC capacitor second sound IF
47 VP2 2nd supply voltage TV processor (+5 V)
48 IFVO/SVO/CVBSI video output / selected CVBS output / CVBS
49 AUDIOIN4L audio-4 input (left signal)
50 AUDIOIN4R audio-4 input (right signal)
51 CVBS4/Y4 CVBS/Y input
52 C4 chroma-4 input
53 AUDIOIN2L/SSIF
54 AUDIOIN2R
56 AUDIOIN3L
57 AUDIOIN3R
30 AUDOUTLSL Audio input
61 AUDOUTLSR
62 AUDOUTHPL
63 AUDOUTHPR
59 C2/C3 chroma-2/3 input
64 CVBSO/PIP CVBS/PIP signal output
65 SVM scan velocity modulation output
66 FBISO/CSY flyback input/sandcastle output or composite H/V
67 HOUT horizontal output
70 VIN (R/PRIN2/CX) V-input for YUV interface
71 UIN (B/PBIN2) U-input for YUV interface
72 YIN (G/YIN2/CVBS-YX) Y-input for YUV interface
73 YSYNC Y-input for sync separator
74 YOUT Y-output (for YUV interface)
75 UOUT (INSSW2) U-output for YUV interface
76 VOUT (SWO1) V-output for YUV interface
77 INSSW3 3rd RGB / YPBPR insertion input
23
78 R/PRIN3 3rd R input / PR input
79 G/YIN3 G input / Y input
80 B/PBIN3 3rd B input / PB input
83 BCLIN beam current limiter input
85 RO Red output
86 GO Green output
87 BO Blue output
97 INT0/P0.5 external interrupt 0 or port 0.5 (4 mA current sinking
direct drive of LEDs)
98,99,102~109 P0.0~ P0.4 Data port
111~116,119,120 P1.0~P1.7,P2.0~P2.5,
122,123,126~ 128 P3.0~P3.3
UOCⅢ Internal Diagram：
CHAPTER THREE SIGNAL FLOW ANALYSIS AND KEY POINT
MEASURE DATA
The chapter mainly introduces the receipt and dispose of the AV signal , the power
supply system and system control process of this TV.
Signal Flow Analysis
1.Video signal flow：
24
the AV/S and IF signal which is demodulated by main demodulator are sent by TV plank into video
decode chassis UOCⅢ for decoding ,then the output analog video signal is sent into analog-to-digital
converter TDA8759HV/8/C1 for A/D transform to produce R、G、B digital signals which are transformed in
format by GM1601/GM1501, then, it transformed the different input formats into the uniform up-screen
signal format.
The signal demodulated by sub demodulator is directly sent into submenu video decoder
SAA7115HL/V1 for video decoding and A/D conversion，then again sent into GM1601/GM1501 to do
format transform, the output up-screen is used for submenu display.
After selection, the PC、 HDTV(YPBPR) and DVI signals are sent directly into GM1601/GM1501 for
processing to form uniform up-screen signal.
2.Accompanying sound flow:

TV accompanying sound：RF signal is demodulated by main demodulator to SIF(companying
sound intermediate frequency) signal, SIF is sent into UOCⅢ for demodulation and sound disposal，then,
the output audio signal is zoomed in by D class TPA3002D2PHPR and is sent into the speaker at last.
AV companying sound：the audio signal input by AV is directly disposed by UOCⅢ and zoomed in
by TPA3002D2PHPR,then transported to the speaker.
After the companying sound of PC、DVI、YPbPr are selected by MC74LVX4052DR2 , then they are
disposed by UOCⅢ and zoomed in by TPA3002D2PHPR to make the speaker work.
3.、TV power supply system：

4 channels voltage are transported from the power supply board, they are +24V，+12V，+5V and
+5VS. +24V is provided for inverter of LCD panel, +12V is provided for PA, +5V is transformed by the
manostat into 3.3V、2.5V and 1.8V for IC, it may be turned down under standby mode, while +5VS is
provided for MCU、infrared receiver、EEPROM.
5V is divided into two ways, one way is provided for other IC and apparatus, the 5V will be turned
down under standby mode, but can not be cut off.. The other 5V is provided for MCU、infrared receiver、
EEPROM and so on, it would not be cut off under standby mode.
25
The composition and distribution of the TV power supply：（please see the next page）
26
The Manostat Pin Voltage in Main Board Schedule
Name Type PIN1(V) PIN2(V) PIN3(V) PIN4(V) PIN5(V)

UP7 LM1117-1.8V 0 1.8 5 1.8
UP1 LM1117-3.3V 0 3.3 5 3.3
UP6 LM2596-5.0 24 5 0 5 0
U405 LM1117-3.3 0 3.3 5 3.3
U3 78M08 12 0 8
U403 LM1117-1.8V 0 1.8 5 1.8
U503 LM1806-3.3 0 3.3 5 3.3
U505 LM1117-2.5 0 2.5 5 2.5
U506 LM1117-3.3 0 3.3 5 3.3
U501 LM2596-5.0 12 5 0 5
U502 LM2596-5.0 24 5 0 5 0
U504 LM1117-1.8V 0 1.8 5 1.8
Main Components and Socket Locations and Definitions:
27
Outlet Definition:
Number Name Connected Object Function Description

1 JP5 TV plane
2 JP2 Side AV
3 JP6 DVD AV output
4 JP7 Speaker
5 JP8 loudhailer
6 JP4 DVD decode board
7 JP3 outside AV input
8 JP9 Up screen(screen
inverter input）
9 JP10 Up screen(screen
inverter input)
10 JP12 power supply plane GND，GND，GND，+12V，+12V，+12V
28
11 J171 Prepare to use
13 JP11 power supply plane +12V，+12V，GND，GND，GND，GND，24V，24V
14 JP1 power supply plane SB，GND，GND，5V，5V，5V，GND，GND，12V，
12V
15 J700 Prepare to use
16 CN702 Prepare to use
17 CN700 remote control
18 CN701 K plane
21 JP701 display
23 AVP303 DVI audio input
24 CN300 DVI port
25 AVP300 VGAaudio input
26 CN301 VGA port
Main Components explanation:

Number Name Components Function Description
A U201 TDA15063H-N1B06557 Audio/video decoder
B U400 TDA8759HV/8/C1 Video signal AD converter
C U402 SAA7115HL/V1 Sub channel video decoder
D U600 MT46V2M32LG-4 Frame buffer memorizer
E U700 GM1601/GM1501-BD Video processor
F U305 SM5302AS-G-ET HD signal filter
G U801 AM29LV800DT-70EC Flash，the TV control procedure put in it
H U6 TPA3002D2PHPR Audio PA
I U5 TDA9178T/N1 Video signal image improve
J K202 K9352N Sound surface filter
K K201 K7262N Sound surface filter
L UA3 FSAV330QSCX Select switch
M U701 24LC32A T/SN Buffer
N U307 FSAV330QSCX Select switch
O U306 FSAV330QSCX Select switch
P U302 24LC21A T/SN EEPROM
Q U303 24LC21A T/SN EEPROM
Main Point Wave Picture:

1 RF input color stripe signal, TV signal wave in the 19th pin of sub tuner UT1,The wave of
P P
the 10th of SAA7115 also like this:

P P
29
2 RF input color stripe signal,the Pin85,Pin86,Pin87 of U201 output R,G,B signal wave,the
E pole wave of Q171,Q172,Q173:
3 RF input color stripe signal, I²C bus clock signal UOCIII_SCL, the wave of the 98th pin of
P P
U201,the 11th pin of U5,the 4th pin of parent/sub RF tuner:

P P P P
30
.4 RF input color stripe signal, UOC vertical sync signal, the wave of the 22th pin of
U201,the 105th pin of U400:
P P
.5 RF input color stripe signal，UOC vertical sync signal , the wave of the 22th pin of
U201,the 105th pin of U400:
P P
RF input color stripe signal，UOC vertical sync signal , the wave of the 22th pin of U201,the
105th pin of U400:
P P
31
.6 RF input gray ladder signal, the TV signal wave in the 19th pin of SAA7115:
P P
The wave in the 10th of SAA7115 also like this:

P P
32
7 The 1KHz sound signal input, the wave of the 60th 、61th pin of U201, the wave of the
P P
2th、6th pin of U6 also like this:

P P
8 The 1KHz sound signal input, the wave of 16th、17th、20th 、2140th 、41th 、44th 、
P P P P P P P P P P
45th pin of U6 and pins:

P P
33
Location Type PIN1(V) PIN2(V) PIN3(V) PIN4(V) PIN5(V)
No.
UP7 LM1117-1.8V 0 1.8 5 1.8
UP1 LM1117-3.3V 0 3.3 5 3.3
UP6 LM2596-5.0 24 5 0 5 0
U405 LM1117-3.3 0 3.3 5 3.3
U3 78M08 12 0 8
U403 LM1117-1.8V 0 1.8 5 1.8
U503 LM1806-3.3 0 3.3 5 3.3
U505 LM1117-2.5 0 2.5 5 2.5
U506 LM1117-3.3 0 3.3 5 3.3
U501 LM2596-5.0 12 5 0 5
U502 LM2596-5.0 24 5 0 5 0
U504 LM1117-1.8V 0 1.8 5 1.8
34
CHAPTER FOUR SYMPTOMS AND CORRECTION
Symptom One：Display card of PC no image in DVI.

Reason and Resolve: If some display card of DVI can not receive the data when turning on
the TV, there is no output; if pull out the DVI line abruptly, there is also no DVI output; Before
starting PC, connect the DVI line with LCD TV steadily, So DVI can receive the correct date
from DDC（ Display Data Channel） when turning on the TV,DDC is in chassis 24LC21.
Symptom Two： No picture but sound, on LOGO when turning on the TV, background light is
bright.
Reason and Resolve: Check the connect line in up screen, and connect the line.
Symptom Three：No picture、no sound ,no snowflake in TV mode, but AV is normal.

Reason and Resolve: Check the outside of high frequency (also bus and power supply),
there is no problem ,but no output from high frequency, so the tuner is disabled.
Symptom Four：LCD TV can not be controlled.(inc red lamp is on but the TV is off, remote
control and local keys can not control the TV ,etc.)
Reason and Resolve：the LCD TV can not work abruptly, power off and turning it on again.
35
CHAPTER FIVE BREAKABLE AND MAINTENANCE PARTS
This list is provided for reference, all the parameters of those maintenance parts are subject to change without
notice for future improvement, please refer the latest models and specifications as the standard.
Akai LTA-26C902
Breakable
Assembly Assembly
NO. Name PCB Number Ratio
Code Number
（‰）
1. Front frame 8807400311J JUJ8.074.031-1 0.1
2. Faceplate 8808100160J JUJ8.081.016 0.1
3. Back cover 8807400501J JUJ8.074.050-1 0.1
4. Base decoration board 8735600050J JUJ7.356.005 0.1
5. Base 8807000130J JUJ8.070.013 0.1
6. Main board assembly 86690003521J JUJ6.690.035-21 PCB JUJ7.820.088 1
7. 8669300150J JUJ6.693.015 PCB JUJ7.820.103 0.5
8. TV board assembly 8669700040J JUJ6.697.004 PCB JUJ7.820.128 1
Remote receive board
9.
assembly 8669400180J JUJ6.694.018 PCB JUJ7.820.104 0.5
Key-press board
10.
11. Buttons 8833700110J JUJ8.337.011 0.1
Built-in power supply
12. 0.1
module 67128017905 FSP179-4F01
13. TFT panel 68212600105 LC260W01 1
14. Electronic tuner 8289100454E TAD5-C2IP1RW 1
TMI4-C22P2RW(JU
15. 2
Electronic tuner 8289100063E E2.891.006-3)
16. Electric speaker 56224605080 Y2929-01-5W-8Ω 2
17. Electric speaker 562D6608082 Y50138-01-8W-8Ω 1
18. Remote controller
Akai LTA-32C902
Breakable
Assembly
NO. Name Assembly Code PCB NO. Ratio
Number
（‰）
1 Front frame 8807400410J JUJ8.074.041 0.1
2 Back cover 8807400422J JUJ8.074.042-2 0.1
36
3 Base decoration board 8735600040J JUJ7.356.004 0.1
4 Base 8807000160J JUJ8.070.016 0.1
Main board assembly
5
（LG screen） 8669000350J JUJ6.690.035 PCB JUJ7.820.088 1
Main board assembly
6
（SAMSUNG screen） 8669000354J JUJ6.690.035-4 PCB JUJ7.820.088 1
7 AV board assembly 8669300150J JUJ6.693.015 PCB JUJ7.820.103 0.5
8 TV board assembly 8669700040J JUJ6.697.004 PCB JUJ7.820.128 1
Remote receive board
9
10 Key press board assembly 8669400190J JUJ6.694.019 PCB JUJ7.820.091 0.5
11 Buttons 8833700110J JUJ8.337.011 0.1
12 0.1
module 67128017905 FSP179-4F01
13 TFT panel 68219632010 LC320W01 LG screen
14 Electronic tuner 8289100063E TMI4-C22P2RW 1
15 Electronic tuner 8289100454B TAD5-C2IP1RW 1
16 Electric speaker 56224605080 Y2929-01-5W-8Ω 2
Y50138-01-8W-8
17 2
Electric speaker 562D6608082 Ω
18 Remote controller KLC5A 1
Akai LTA-37C902
Assembly Assembly BBreakable

NO. Name PCB NO.
Code Number Ratio （‰）
1 Frame 8807400430J JUJ8.074.043 0.1
2 Back cover 8807400442J JUJ8.074.044-2 0.1
3 Base 8807000160J JUJ8.070.016 0.1
4 Main board assembly 8669000354J JUJ6.690.035-9 PCB JUJ7.820.088 1
5 AV board assembly 8669300150J JUJ6.693.015 PCB JUJ7.820.103 0.5
6 TV board assembly 8669700040J JUJ6.697.004 PCB JUJ7.820.128 1
Remote receiver board
7
8 Key press board assembly 8669400240J JUJ6.694.024 PCB JUJ7.820.091 0.5
9 5
module 67128024105 FSP241-4F01
10 TFT panel 68213700105 LC370W01 0.1
11 Suspending screen 886400063E TMI4-C22P2RW 0.1
12 Electronic tuner 8289100063E TMI4-C22P2RW 1
13 Electronic tuner 8289100454E TAD5-C2IP1RW 1
37
14 Sound boxes 56232971081 Y3297-L-10W-8Ω 1
15 Sound boxes 56232971082 Y3297-R-10W-8Ω 1
14 Electric speaker 56232971082 Y3297-R-10W-8Ω 1
15 Electric speaker 56239390580 Y3939-01-5W-8Ω 2
16 Remote controller 8201803510L KLC5A 1
DVD maintenance parts( only for models with DVD module):

DVD touch key label 8661800060J JUJ6.618.006
DVD output board
assembly 8669300120J JUJ6.693.012
DVD decoding board
assembly 8669300130J JUJ6.693.013
Converter board
assembly 8669100080J JUJ6.691.008
DVD driver 59C11060850 TDR-085
CHAPTER SIX FACTORY MODE AND NOTICE

Enter into factory menu
1. Enter into child lock of main menu in TV mode, press “OK, the password input box will appear;
2. Use remote control to input the follows in order:7,red key,9,blue key, then you can enter into factory
mode menu. After entering into factory mode menu, sign of the factory menu M will appear.
factory menu and setup
1. factory menu display is below:
M
Index: 1
HWUC_BRI 0x1F
The M denotes entering into factory mode now, the figures of index denotes the index number now,the
HWUC_BRI denotes the name of adjusting item now, the 0X1F denotes the numerical value.
2. Each adjusting item have only one index number ,the operator press the numeric key or press P+/P-
directly.
3. Optional and adjustable items, the corresponding relation of index number and adjusting item is below:
(Index) Operating
Name Item Meanings Remark
Key
1 HWUC_BRI UocIII subsidiary Adjust subsidiary brightness
V+/V-
brightness
2 HWUC_SAT UocIII saturation V+/V- Adjust subsidiary saturation
3 HWUC_CON UocIII contrast V+/V- Adjust subsidiary contrast
4 HWUC_AGC UocIII AGC V+/V- Adjust AGC
5 PIP Brightness 7115 subsidiary Activate sub picture When
V+/V-
brightness adjusting it
6 PIP VGA 7115 contrast V+/V- Activate sub picture When
38
Contrast adjusting it
7 Balance Sound balance The tuning value is 50，-50，
V+/V-
0
8 Volume Sound Volume V+/V- Step is 10
9 Sound System Sound System V+/V- DK/I/BG/M
10 Auto Search Auto searching V+/ok Source of Signal is TV
11 White Balance White balance V+/ok
12 AutoColor Auto color revise Source of Signal VGA
V+/ok
/YpbPr /TV
13 DVD DVD preset V+/V- 1 represents preset
14 BBE BBE preset V+/V- 1 represents preset
15 TruSurround TruSurround preset V+/V- 1 represents preset
16 SALESFOR SALESFOR V+/V- Set the target country
17 Factory Out initialization V+/ok Leave factory set
18 Clear EEProm initialize EEPRom V+/ok Initialize the storage date
19 D Mode Enter into design Adjustable design mode all
V+/ok
mode the parameter
20 DPF DPF preset V+/V- 1 represents preset
21 BBE_CONT BBE plus set V+/V- Adjust BBE plus
22 BBE_PROC BBE plus set V+/V- Adjust BBE plus
23 Newcom Newcom set V+/V- 1 represents preset
notice：
1、if no especial demand, please do not enter into the 20th item(design mode);
P P
2 、 when tuning the 16th item ,the storage data will be cleaned off, therefore, if not
P P
necessary ,please do not adjust it, the items of index number 1,2,3,4,5,6 are not necessary to adjust.
Adjustment methods for factory menu

1. Select the adjusting item
You can skip to the adjusting items by pressing the number key, also can select the adjusting item in
the order of P+/P-.when pressing the number key, if the adjusting item is 1~9,input the corresponding
number keys and press down “OK”, if the adjusting items tens digit, input a tens digit. For example ,press
number key 8 when adjusting the volume, you can see the color which become green, then press down
“OK”, the color of index number turns red, So you already selected corresponding volume adjusting item.
If adjust DVD preset, first input 1,then input 3,you can adjust DVD preset.
2. Adjustment methods
Adjust it according to the operating key in above list. For one act operation ,press OK/V+.
example Auto Color, for some variable add/reduce, Example Volume, press V+/V- .
3. The illuminate of white balance and AutoColor adjustment method

Index 11 is corresponding to manual balance ,press “OK” or “V+” to display three corresponding
variable, press “P+/P-”to select, press “V+/V-” to adjust, press down menu key to exit.
The index of AutoColor is 12,press “OK”or “V+” to do color revision, then the adjusted value will display.
39
4. BBE plus adjustment
Index number of BBE plus adjustment is 22 and 23,adjust it by adjusting “V+/V-”,the value of W270F8E
and W320F8E are set 0X09,but the W370F8E is set 0X0F.
5. Press down the【DISPLAY】 first before switching the program number in factory mode, press P+/P- to
switch before the display content do not disappear;
6. All menu functions are on in factory mode, if necessary you can use menu to check the items and effect
test.
Factory debug item
1. Auto color revise（AutoColor）
Firstly finish auto color revise first before factory debug. Revise in TV、YPBPR and PC respectively.
① Requisite Meter
PC one
HD signal source one
② Debug（Revise in TV、YPBPR and PC respectively）
Park the channel in C-3 under TV mode TV, then do AutoColor.
Input color stripe signal in YPBPR and do AutoColor.
Input window signal in PC, the window is white, black signal around.
The result will appear in screen after AutoColor adjustment,make the adjustment results of Rgain、
Ggain and Bgain close to 0 × 80,if the difference is too great,adjust the value of
HWUC_CON(auxiliary saturation),and readjust the AutoColor.
2. White balance, color temperature adjustment
① Requisite Meter
CHROMA 7120 color analyze instrument（or same function instrument,contain color coordinate –
chroma diversion card） one
White balance adjusting frock（request the video output range 0-1V is adjustable,750hm load）
one
② Prepare
A. connect all equipments, switch the condition of LCD TV to AV.
B. Set the picture of LCD TV for standard condition
C. Set the distance of light receiver of white balance from center place of LCD display screen for
15cm±3cm .
D. Make sure that the environmental brightness is below 2cd/m2 P P
③ White balance, color temperature adjustment

Before adjusting it, put the first LCD TV in AV condition, and the image in standard condition, white
balance adjust frock send the white vertical signal output from video into AV, adjust output range of
balance adjust frock, make the brightness of the LCD TV 200±20cd/m2 (use CHROMA 7120 color
P P
analyze instrument to obtain the brightness ),then fix the video output range of white balance adjust
frock(until all the LCD TV are adjusted).
Enter into white balance adjusting item of factory mode, change R,G,B value(try best to adjust this 3
value biggest) .
Make color temperature coordinate value accord with that of the table below (error value within
±4%) ：
Z X Y
40
K12000 0.270 0.277
Note：The color temperature and color coordinate are contented for above request, you should judge the
exist of color windage phenomenon, namely the value of Δuv is 0 or not
If Δuv is not 0 , readjust R,G,B value to 0,and meet color coordinate request.
41
1 2 3 4 5 6
D D
FSDATA[0..31]
RGB/YPbPr_SEL
Ls08-Frame Memory-02
Ypbpr/RGB_EN
Ls08-Frame Memory-02 Ls08-AD convert-01
FSDQS
FSDQM[0..3] Ls08-AD convert-01 LS08-Gm1601-03 ls08-Graphics_Components In-04
PWM3
FSDATA[0..31] FSDQM[0..3]
FSCKE MSTR_SDA MSTR_SCL LS08-Gm1601-03 ls08-Graphics_Components In-04
HV_SEL
FSDQS FSCKE MSTR_SDA MSTR_SCL
FSBKSEL1 VGRN[7..0] /OCM_WE GREEN+ BLUE-
23SDD[31..0] FSBKSEL1 VGRN[7..0] /OCM_WE GREEN+ BLUE- RGB/YPbPr_SEL
/FSCAS 23SDD[31..0] /FSRAS RXC- VGA_SDA
/FSCAS 23SDD[31..0] /FSRAS RXC- VGA_SDA PWM3
/FSRAS 23SDCLK OCMADDR[0..19] AHS BLUE+
/FSRAS 23SDCLK OCMADDR[0..19] AHS BLUE+ Ypbpr/RGB_EN
/FSWE 23SDDQM MSTR_SCL RED-
/FSWE 23SDDQM MSTR_SCL RED- HV_SEL
FSBKSEL0 23SDCS# FSCLK+ VGA_SCL GREEN+
FSBKSEL0 23SDCS# FSCLK+ VGA_SCL GREEN+
FSCLK- 23SDBA0 /FSCAS SVCLK DVI_CAB
FSCLK- 23SDBA0 /FSCAS SVCLK DVI_CAB
FSCLK+ 23SDBA1 OCMDATA[0..7] RXC+ RX1+
FSCLK+ 23SDBA1 OCMDATA[0..7] RXC+ RX1+
23SDA[10..0] 23SDCAS# MSTR_SDA GREEN- GREEN-
23SDA[10..0] 23SDCAS# MSTR_SDA GREEN- GREEN-
23SDDQM 23SDCAS# /ROM_CS ITRU[7..0] RX1-
23SDDQM 23SDRAS# /ROM_CS ITRU[7..0] RX1-
23SDBA0 23SDWE# PBIAS RED+ RX0-
23SDBA0 23SDWE# PBIAS RED+ RX0-
23SDBA1 23SDA[10..0] /FSWE BLUE- RED+
23SDBA1 23SDA[10..0] /FSWE BLUE- RED+
23SDWE# DVI_SDA BLUE+ RXC-
23SDWE# DVI_SDA BLUE+ RXC-
23SDCAS# FSCKE RX1- RX2-
23SDCAS# FSCKE RX1- RX2-
23SDRAS# VVS VGA_SDA DVI_SCL RX2+
23SDRAS# VVS VGA_SDA DVI_SCL RX2+
23SDCS# VCLK FSDQS RX1+ RXC+
23SDCS# VCLK FSDQS RX1+ RXC+
23SDCLK FSBKSEL1 RX2+ RX0+
23SDCLK FSBKSEL1 RX2+ RX0+
FSADDR[0..11] VHS FSCLK- RX2- DVI_SCL
FSADDR[0..11] VHS FSCLK- RX2- DVI_SCL
VBLU[7..0] FSBKSEL0 VGA_CAB
VBLU[7..0] FSBKSEL0 VGA_CAB
VRED[7..0] FSDATA[0..31] RX0- DVI_SDA
VRED[7..0] FSDATA[0..31] RX0- DVI_SDA
Scart2_CIn PPWR AVS VGA_SCL
Scart2_CIn PPWR AVS VGA_SCL
Scart2_VideoIn /OCM_RE RX0+ SOG
Scart2_VideoIn /OCM_RE RX0+ SOG
Video1_C_IN FSADDR[0..11] RED- AVS
Video1_C_IN FSADDR[0..11] RED- AVS
Video1_Y_IN PWM3 SOG AHS
Video1_Y_IN PWM3 SOG AHS
C SubchannelTV FSDQM[0..3] Scart2_CIn C
SubchannelTV FSDQM[0..3] Scart2_CIn
ITRU[0..7] SEC_SDA Scart2_VideoIn
ITRU[0..7] SEC_SDA Scart2_VideoIn
7115_RSON VGA_CAB Video1_C_IN
7115_RSON VGA_CAB Video1_C_IN
ls08-Memory I_F-05 SVCLK RGB/YPbPr_SEL DVI_CAB Video1_Y_IN
SVCLK RGB/YPbPr_SEL DVI_CAB Video1_Y_IN
ls08-Memory I_F-05 POWER_OFF SubchannelTV
POWER_OFF SubchannelTV
/ROM_CS SAA7115_EN Set_tristate2 VCLK Scart1VideoIN
/ROM_CS SAA7115_EN Set_tristate2 VCLK Scart1VideoIN
/OCM_RE Tv_BOUT Set_tristate2 VVS Set_tristate2
/OCM_RE Tv_BOUT Set_tristate1 VVS Set_tristate2
/OCM_WE Tv_GOUT ChannelSel2 VHS Set_tristate1
/OCM_WE Tv_GOUT ChannelSel2 VHS Set_tristate1
OCMADDR[0..19] Tv_ROUT ChannelSel1 ChannelSel2
OCMADDR[0..19] Tv_ROUT ChannelSel1 SCRT2-FSEL ChannelSel2
OCMDATA[0..7] TV_Csync Sel_HsVs ChannelSel1
OCMDATA[0..7] TV_Csync Sel_HsVs CC_INT1 ChannelSel1
Scart1VideoIN Teltext_MUTE VRED[7..0] Sel_HsVs
Scart1VideoIN Teltext_MUTE VRED[7..0] Sel_HsVs
Yout Communication VGRN[7..0] Yout
Yout Communication VGRN[7..0] Yout
PRout AudioSelADDB VBLU[7..0] PRout
PRout AudioSelADDB VBLU[7..0] PRout
PBout AudioSelADDA ITRU[7..0] PBout
PBout AudioSelADDA ITRU[7..0] PBout
8759PowerDown SAA7115_EN SVCLK AudioSelADDA
8759PowerDown SAA7115_EN SVCLK AudioSelADDA
AVS 8759PowerDown AudioSelADDB
AVS 8759PowerDown AudioSelADDB
LS08-Power_Display-06 SVCLK 7115_RSON Teltext_MUTE
SVCLK 7115_RSON Teltext_MUTE
LS08-Power_Display-06 AHS IRDATA Ypbpr/RGB_EN IRDATA
AHS IRDATA Ypbpr/RGB_EN IRDATA
PBIAS SAA7115_EN M_SCL HV_SEL Communication
PBIAS SAA7115_EN M_SCL HV_SEL Communication
PPWR M_SDA
PPWR M_SDA
POWER_OFF
POWER_OFF
B B
NEW5-ls08-Sound Amplifier
NEW5-ls08-Sound Amplifier.Sch
NEW1-ls08-12029 MOL
MOL
NEW1-ls08-12029 NEW2-ls08-INPUT PORT MOR
MOR
SC1_RIN SC_AVOUT NEW2-ls08-INPUT PORT MUTE
SC1_RIN SC_AVOUT MUTE
SC1_GIN AV_R
SC1_GIN TV_Rout SCOL AV-R
SC1_BIN AV_L
SC1_BIN TV_Gout SCOR AV-L
FBLIN1 SC_AVOUT FBLIN1
FBLIN1 TV_Bout SC_AVOUT FBLIN1
C_3D TV_Csync UOC_SW1 AVS1
C-3D TV_Csync UOC_SW1 AVS1
Y_3D AGC UOC_SW2 SC1_Laudio
Y-3D AGC UOC_SW2 SC1_Laudio
AV_R AGC SC1_Raudio
AV-R SCOL AGC SC1_Raudio
AV_L UOCIII_SDA AVS2
AV-L SCOR UOCIII_SDA AVS2
AVS2 MOL UOCIII_SCL Scart2_Cin
AVS2 MOL UOCIII_SCL Scart2__CIn
UOCIII_SCL MOR SubchannelTV Scart2_VideoIn
UOCIII_SCL MOR SubchannelTV Scart2_VideoIn
SC1_Laudio 3D_IN MM_SCL Video1_Y_IN
SC1_Laudio 3D_IN MM_SCL Video1_Y_IN
SC1_Raudio Communication MM_SDA Video1_C_IN
SC1_Raudio Communication MM_SDA Video1_C_IN
MUX_L UOC_SW1 Scart1VideoIN
MUX_L UOC_SW1 Scart1VideoIN
MUX_R UOC_SW2
MUX_R UOC_SW2 Scart1_R
PH-SW DVD_id
PH-SW DVD_id Scart1_G
Scart2_Cin 3D_reset
Scart2_CIn 3D_reset Scart1_B
Scart2_VideoIn SC2_LIN
Scart2_VideoIn SC2_LIN
Video1_C_IN SC2_RIN
Video1_C_IN SC2_RIN
Video1_Y_IN SC1_RIN
Video1_Y_IN SC1_RIN
Scart1VideoIN SC1_GIN
Scart1VideoIN SC1_GIN
AVS1 SC1_BIN
AVS1 SC1_BIN
SC2_LIN
SC2_LIN DVD_id
SC2_RIN Tuner_IF NEW3-ls08-POWER
SC2_RIN Tuner_IF
Tuner_IF R_YPBPR NEW3-ls08-POWER.SCH
Tuner_IF R_YPBPR
MM_SCL Y_YPBPR Power_off
MM_SCL Y_YPBPR Power_off
MM_SDA B_YPBPR Backlight_on_off
MM_SDA B_YPBPR Backlight_on_off
MUTE YPBPR_R DVD_On/Off
MUTE YPBPR_R DVD_On/Off
UOCIII_SDA YPBPR_L IRDATA/SCL
UOCIII_SDA YPBPR_L IRDATA/SCL
A State/SDA A
State/SDA
Title
Size Number Revision

C
Date: 13-Apr-2005 Sheet of
File: E:\USER\MJ\LP08\YLT-chn\LS08_MAIN_TDA8759-20050223.Ddb
Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6
+5VOUT
VCC5A CA6
0.1uF
RA35
4.7k
RA18
CA20
10k SC1_GIN
SC1_GIN
+
VCC5A QA6
JP3 10uF 2SC1815Y
9
D 8 Video1Y_IN RA36 D
7 CA1 0.1uF 4.7k RA45
6 Video1C_IN 330
5
4 AVR RA19
3 10k
2 AVL +5VOUT
1 VCC5A VCC5A
CON-9 RA16 RA17 To UOCIII&Tuner Board. RA37

4.7k
10k 10k
CA21
QA7 To GM1601 Board.
SC1_BIN 2SC1815Y
SC1_BIN Scart1_G
+
Scart1_G
+5VOUT 10uF
RA20 RA21 RA38 Scart1_B
10k 10k CA5 4.7k Scart1_B
0.1uF RA46
330 Scart1_R
RA33 Scart1_R
4.7k
CA19 QA5
SC1_RIN
SC1_RIN 2SC1815Y
+
Video1_C_IN
Video1_C_IN 10uF
Video1_Y_IN
DVD_id Video1_Y_IN RA34
DVD_id 4.7k
VCC5A
CON-12 RA44
1 16
JP4 SEL VCC 330
C 1 DVD_C 2 15 CA4 RA34A C
1B1 /OE 0
2 0.1uF
3 DVD_Y 3 14 DVD-L To Board Side.
4 1B2 4B1
5 DVD-L RA9 4 13 AVL
1A 4B2
6 75
7 DVD-R 5 12 AV-L JP5
8 2B1 4A AV-L
9 DVD_Video RA13 6 11 DVD-R SC1_BIN Y_YPBPR
75 2B2 3B1 1 26 Y_YPBPR
10
11 SPDIF 7 10 AVR AVS1 B_YPBPR
2A 3B2 AVS1 2 27 B_YPBPR
12
8 9 AV-R SC1_GIN R_YPBPR
GND 3A AV-R 3 28 R_YPBPR
SC1_RIN SC1_Laudio
4 29 SC1_Laudio
JP6
UA3
The DVD Player Must Output With DC-LEVEL Signal. FBLIN1
FBLIN1
5 30
SC1_Raudio
SC1_Raudio
CON-7
FSAV330M
Scart1VideoIN YPBPR_L
Scart1VideoIN 6 31 YPBPR_L
7 +5VOUT
6 YPBPR_R
7 32 YPBPR_R
5
+12V_dc
4 RA10 SCOL
8 33 SCOL
3 470
2 RA49 9 34
1 220
SCOR
1035 SCOR
1136
VCC5A
SC_AVOUT
B SC_AVOUT B
1237
QA12
UA1 CA8 2SC1015Y
0.1u 1338
MC14016BDR2 +32V
SC2_RIN
M_SDA 1 14 SC2_RIN 1439
A1 VCC GND
2 B1 C1 13 SC2_LIN
VGA_SDA1 3 12 SC2_LIN 1540
A2 C4
MM_SDA 4 11
MM_SDA B2 B4 AVS2
5 10 VGA_SCL1 AVS2 1641
C2 A4
6 C3 B3 9 Scart2_CIn
7 8 M_SCL Scart2_CIn 1742
GND A3 +5VB
GND 1843
Scart2_VideoIn
Scart2_VideoIn 1944
UOCIII_write_ctrl
VCC5A +5VOUT SubchannelTV
2045 SubchannelTV
VCC5A RA47
MM_SCL MM_SCL 22
2146
R322 UOC_SW1
10K 2247 UOC_SW1
CA7 CA9 2348 UOC_SW2 UOC_SW2

R352 CA31
3
47K 0.1uF 10V220uF 0.1uF UOCIII_SDA Tuner_IF

UOCIII_SDA 2449 Tuner_IF
1
Q308 UOCIII_SCL UOCIII_SCL 2550 AGC AGC
2SC1815Y
2
SDA-7166102050
A A
UOCIII_write_ctrl= +5V, UOC CONNECT WITH 1601 GND
UOCIII_write_ctrl= 0V, UOC CONNECT WITH VGA
Title

B
Drawn By:
1 2 3 4 5 6
C204 U201B
To TDA9178
SC1_RIN 0.1uF 78
SC1_RIN R3/Pr 100 YY_out
YOUT 74 RT11
SC1_GIN C203 79 75 RT12 100 U_out V1_8V1_A L1 V1_8V1
SCART1 RGB INPUT SC1_GIN G3/Y UOUT/INSSW2 100 V_out L201 U201A
0.1uF C211 76 RT13 VCC5A 10uH
SC1_BIN 0.1uF 80 VOUT/SWO1 10uH VDD5A_1 15 124
SC1_BIN B3/Pb 64 100 3D_IN VDD5A_1 VDDC 100
CVBSO/PIP R265 VDDC
R202 77 C215 C218 C221 117 C226 C227 C228
SCART1 RGB CONTROL FBLIN1 FBLIN VDDC
10K ROUT 85 R205 100 TV_Rout 10V47uF 0.1uF 0.1uF 0.1uF 0.1uF C231 C256
GOUT 86 R206 100 TV_Gout 0.1uF VSSC 101 10V47uF 0.1uF
C-3D C-3D CT1 0.1uF 70 V/R2/Pr BOUT 87 R207 100 TV_Bout 18 GNDA1 VSSC 121
125
upc64084 OUTPUT U_IN CT2 0.1uF 71 83 C212 10V47uF L202 VDD5A_2 47 VSSC V3_3A
U/B2/Pb BCLIN 10uH VDD5A_2 90
VREF
Y-3D Y-3D CT3 0.1uF 72 Y/G2/Y BLKIN 84 A1 C213 C216 C222A C222 L204
R201 100 SVM 65 1000pF R208 C219 2.2uF C224 10uH
YY_out C207 0.1uF 73 YSYNC FBISO 66 100 TV_Csync TV_Csync 0.1uF 10V47uF 0.1uF 0.1uF
40
R204 VCC5A GNDA2 89 L205
Scart1VideoIN C201 C208 0.1uF 55 VCC5A 27K D201 L203 82 VSS_REF 10uH VCC5A
SCART1 VIDEO INPUT Scart1VideoIN CVBS2/Y2 VDD5A_3
VIDEO1/Y INPUT Video1_Y_IN 0.1uF 58 CVBS3/Y3 HOUT 67 uoc_hs R210 2CK75D 10uH VCOMB 69 VCOMB
SCART2 VIDEO/Y INPUT Scart2_VideoIn Scart2_VideoIn C209 0.1uF 51 CVBS4/Y4 10K R211 C217 C220 C223
C202 59 R266 C225
S-VIDEO1 C INPUT Video1_C_IN C2/C3 4.7K 68K 10V47uF
Scart2_Cin 0.1uF C210 0.1uF 52 0.1uF 0.1uF C230
SCART2-C INPUT Scart2_Cin C4 31 R212 10k AGC 81 0.1uF 10V47uF
AGC 43 AGC GNDA3 68
IFVO R209 VSSCOMB
SC_AVOUT R203 1K 48 SVO/CVBSI FMRO 44 680 C214 V3_3A 1 GNDA L212
SCART OUTPUT 10nF C248 10uH V1_8ANA
VIFIN1 24 VIFIN1 PLLIF 41 R221 C247 16V22uF L207 VDD3A 4 VDD3A VADC 96
390 0.1uF 10uH
VIFIN2 25 C249 C257 C261 C264
VIFIN2 42 C243 1uF C253
29 SIFAGC 0.1uF 10V47uF 0.1uF 0.1uF 0.1uF
SIF1
SIF1
AGC2SIF 46 C244 1uF 12 GNDA VSSADC 95
SIF2 30 SIF2
C238 2.2uF 53 36 R217 1K SCOL L208 88 93 L213
AV-L C234 2.2uF 54 AUDIO2_INL AUDOUTSL SCOL 10uH VDD3 VDDA 10uH
AV-R C239 2.2uF 56 AUDIO2_INR 37 R218 1K SCOR C250 C258 C262 C265
MUX_L AUDIO3_INL AUDOUTSR SCOR
MUX_R C235 2.2uF 57 AUDIO3_INR C255
VDD5A_1 R213 47K 21 EWD/AVI AUDIO_OUT_LSL 60 R219 100 MOL MOL 0.1uF 10V47uF 0.1uF 0.1uF 0.1uF
C240 50V220nF 19 Sound Amplifier 92
SECPLL 61 R220 100 MOR GNDAUD
AUDIO_OUT_LSR MOR V1_8V1
62 L209 110 3 L211 10uH
AUDIO_OUT_HPL VDDP VDDC
SC2_LIN C241 2.2uF 49 AUDIO4_INL D3.3V VCC5A 10uH L218 V3_3A
SC2_RIN C236 2.2uF 50 AUDIO4_INR AUDIO_OUT_HPR 63 C251 C259 VDD3A 94 VDD3A_94
10uH
C242 2.2uF 34 R225 R238 0.1uF 0.1uF C263A C263 C263B
SC1_Laudio C237 2.2uF 35 AUDIO5_INL 97 C266
SC1_Raudio AUDIO5_INR INT0 10K 10K
33 0.1uF 0.22uF 10V100uF 0.1uF
SSIF
P00/I2SDI1/0 106 V1_8V1_A
R214 4.7K 105 R227 R234 L210 118
P01/I2SDO1 100 100 VDD18
23 VDRA P02/I2SDO2 104 IRDATA/SCL IRDATA/SCL To DVD IR 10uH VSSC 2 +5VB
uoc_vs 22 103 DVD_On/Off C260
20 VDRB P03/I2SCLK 102 C252 5 45 VDD5A_2
DECBG P04/I2SWS 2.2uF 0.1uF VREF_SDAC1 V8SWTCH RT201
C232 C233 R216 39K 27 98 R224 47 UOCIII_SCL 10K
IREF P10/INT1 UOCIII_SCL
C273 50V220nF 26 VSC P11/T0 99 R237 47 UOCIII_SDA UOCIII_SDA QT201
10V10uF 0.1uF P12/INT2 126 R253 C288 DECDIG V1.8CONTROL
R231 100K 32 107 +5VB V3_3A 6 2SC1815Y
28 EHT P13/T1 127 R222 100 10K DVD_id GREF_SDAC1 0.22uF
GNDIF P14/RX 128 DVD_id L216 7 14 RT202
17 P15/TX 108 R235 100 MM_SCL 10uH VREF_SDAC2 DECDIG
PH1LF P16/SCL MM_SCL 47K
R228 P17/SDA 109 R236 100 MM_SDA MM_SDA C279 C280
C268 12K C271 R232 1K 16 PH2LF C278 10
6.8nF 111 R262 100 Communication 0.1uF
10V10uF
0.1uF
XIN
1uF C276 P20/TPWM 112 Communication 8 Y201
10V4.7uF 38 P21/PWM0 113 100 UOC_SW2 GREF_SDAC2 11 24.576MHz
DECSDEM P22/PWM1 R261 UOC_SW2 VCC5A XOUT
114 9
P23/PWM2 100 VREF_SDAC3
C277 39 QSSO P24/PWM3 122 R260 UOC_SW1 UOC_SW1 C281 C282
3900pF 123 R270 100 SAW_SW CT11 RT21 22pF
P25/PWM4 NC(15K) 22pF
91 SUB-TUNER SWITCH TDA15063H-N1B06557
REFAD 115 100 AVS1 1000pF Select Y2 -- Saronix 9922 520 20264
P30/ADC0 R259 AVS1
C270 13 116 R258A 100 MUTE
10V100uF C274 VGUARD P31/ADC1 119 100 AVS2 MUTE
P32/ADC2 R258 AVS2 U3
4
0.1uF P33/ADC3 120 5VSW RT20
RT15 MC78M08CDT
100 NC
GND 4
TDA15063H-N1B06557 R239 R243
OUT
10K V3_3A VCC5A
10K
IN
VIFIN2 VCC5A VCC5A +12V_3A LT1 10uH
VCC5A
3
VIFIN1
K201 R223 R226
R240 22K 22K
R229 K3953M(K7262D CHINA) 10K R241 R242 20
L214 3216M800MT R233 L215 CT4 CT9 CT5 YY_out 6 VCC
10uH 4.7K 4.7K CT4A CT8 YIN
1
2
3
4
5
180 1uH R271

C269 10K 0.1uF 100uF16V
0.1uF 100uF16V 0.1uF U_out 8 19 Y-3D
UOCIII_SDA
MM_SDA
C286
UOCIII_SCL
10V100uF UIN YOU
MM_SCL
nc
C272 C275 R247 V_out 9 VIN UOUT 17 U_IN
0.1uF 0.01uF 4.7K
R250 C287 16 C-3D
R263 R263A TV_Csync 1 VOUT
nc 4700 CHINA:R263 0; R264 NC SC
0 NC CT7
Tuner_IF Tuner_IF Q201 CHINA:R263 NC; R264 0 0.1uF
2SC388 CT6 CT10 UOCIII_SDA RT3 100 14 SDA DECDIG 15
R244 C284 100pF 100pF
0 0.01uF UOCIII_SCL RT4 100 11 7
L217 SW SCL ADR 10
100ohm R246 SIF filter TP 18
VEE
1
2
3
4
5
3.3K MM_SDA RT5 100 3 2

C285 R252 ADCEXT1 NC
NC 27 MM_SCL JP201 RT6 100 4 ADCEXT2 NC 23
RT7 100 5 24
CON-4 ADCEXT3 NC
R264 R264A K202 4 U5
NC K9656M(K9352M/D CHINA)) VCC5A R256
10 TDA9178T UOCIII TAD12019H
R248 0 3
4.7K UOCIII TAD12019H
D205
R245 2CK75D 2
+12V_DC 100
R254 1
R249 22K Title
2.2K Q202 SAW_SW
C283 R251 2SC1815Y
0.01uF 2.2K
H: L' L:BG/DK/I (EUROPE) Size Number Revision
2
H: BG/DK/I L:M/N (CHINA) A2
Drawn By:
1 2 3 4 5 6 7 8
DVI CONNECTOR
CN300
TP308 TP316
TP300
25
1 RX2-
RX2- RX2- GND GND
2 RX2+
RX2+ RX2+ TP309 TP317
3
GND
4
RX4-
5 TP305
RX4+ GND GND
6 DVISCL
SCL
7 DVISDA
SDA TP310 TP318
8
VS
TP301
9 RX1-
RX1- RX1- GND GND
10 RX1+
RX1+ RX1+
11 Static Protection.
GND TP311 TP319
12
RX3-
13 TP306
RX3+ DVI Test Points are just SMTobservation points on the traces with no stub
14 R300 GND GND
5V
15 10K/5%
GND R304 TP312 TP320
16 HOT_PLUG
D HP DVI_CAB D
TP302 1K
17 RX0-
RX0- RX0- GND GND
18 RX0+
RX0+ RX0+
19 R305
GND TP313 TP321
20 TP303 100K
RX5-
21
RX5+
22 TP304
GND GND GND
23 RXC+
RXC+ RXC+
24 RXC-
RXC- RXC-
TP314 TP322
C1 +5V GND
RED CN303
C2 TP307 +5V_ANG
GRN
C3 1
BLU GND GND The Teltext is controned by GM1601 or UOCIII .
2
C4 2
HS D300
C5 UOCIII_SCL R308 20 Tel_SCL 3
GND TP315 TP323
UOCIII_SDA R309 20 Tel_SDA 4
26
2 DVI_5V 3 3 3 3 3 3 3 3 3 3 5
IRDATA 6
GND GND
3 D301 D302 D303 D304 D305 D306 D307 D308 D309 D310 Teltext_MUTE 7
GND DVI-I GND BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L BAV99L Teltext_R 8
BAV99L
1 TP327 IRDATA
1
+5V
R302 R303 Teltext_MUTE
GND CON8
10K/5%
10K GND
BASY3 GND
CN304
DVISCL R301 100 DVI_SCL
DVI_SCL
DVISDA R314 100 DVI_SDA Teltext_G 1
DVI_SDA
VGA_SCL Teltext_B 2
VGA_SCL
VGA_SDA Teltext_R 3
VGA_SDA
4
Teltext_HS 5
U303
Teltext_VS 6
1 8 Static protection.+5V can be changed to +5V_ANG according to PCB layer. 7
A0 VCC
2 7 3D_IN 8
A1 WP
3 6 C301 +5V
A2 SCL
4 5
GND SDA GND CON8
0.1uF
GND 24LC21
2
GND D313A
DIGITAL DDC D313 D314 D315 D317 500 Page Teltext interface.
BAV99L BAV99L BAV99L BAV99L BAV99L
3 3 3 3 3 3 3 3 3
U311 +5V
VGA_SDA1 1 14
A1 VCC D312A D312 D316 D318
2 13
B1 C1 C358 BAV99L BAV99L
3 12 BAV99L BAV99L
A2 C4 0.1uF
1
4 11
B2 B4
5 10
C2 A4
6 9 GND
C3 B3 GND GND
7 8
GND A3
C VGA_SDA2 VGA_SCL2 A-BLUE A-GREEN A-RED A-HS C
VGA_SCL1
A-VS
MC14016BDR2
GND GND
VGA_5V
+5V UOCIII_write_ctrl R315
VGA_CAB
+5V 10K R317 R320
2
22uF/6.3V 5K +5V_MUX +5V_ANG 100K

Graphic Inputs 1%
D311 RA12 R313 R312 R354
10K 47 47 CN301 47K C302 C304 C305 C306
BASY3 GND
DB15 HD 0.1uF 0.1uF 10uF/16V C308 C309
S2
GND C307
GND 0.1uF 10uF/16V 0.1uF 0.1uF
3
R399
VGA_SCL2
VGA_SDA2
15 5
3
1k GND
10
1 GND
A-VS 14 4 C303 GND
9 R316
Q309
C300 A-HS 13 3 A-BLUE 5K
2SC1815Y
2
8 1% TP324 +5V_AUD
GND
0.1uF R311 12 2 A-GREEN
R310 C310 0.01uF
U302 22K 7 R318 470 SOG Q300
3
22K TP328 GND SOG
1 8 11 1 A-RED 2SC1815Y R350
A0 VCC
2 7 GND 6 R319 20 C311 0.01uF BLUE+ 47K
A1 WP BLUE+ 1 YPBPR_L
3 6 TP329 C328 0.01uF BLUE- YPBPR_L
A2 SCL BLUE-
+
4 5 +5V_MUX R333 TP325
GND SDA
GND 0.1uF 5K R339 20 C329 0.01uF GREEN+ C333
GREEN+
2
+5V 1% C330 0.01uF GREEN- L300 YPbPr_LL 47uF/16V
S1
24LC21 C326 GREEN-

GND U306 TP326 22uH/0.5A/<1R
ANALOG DDC +5V_ANG +5V_AUD
R325 R340 20 C331 0.01uF RED+ R349 R351
+3.3V_SW FSAV330M RED+
GND 5K R331 C332 0.01uF RED- 2.2K 47K
RED-
C323 1% 75 R334 +5V_MUX
R306 0.1uF R330 5K 1 16 GND +5V_AUD
SEL VCC C335
R342
R343
R344
75 1% C334
10K
RED_GR 2 15 10uF/16V
1B1 /OE 0.1uF
R326 R332 C324
R396
1
3
5K 75 22uF/6.3V Pr_FIL 3 14 Q301 R366 C348
10K +5V_ANG +5V_FIL 1B2 4B1 GND
1% GND 2SC1815Y 47k 47uF/16V
56
56
56
4 13 GND 1 YPBPR_R
1A 4B2 YPBPR_R
MSTR_SDA 3 2 GNDGND GND YPbPr_RR
+
L301 C319 5*%6, * 1 $ / * 1 ' VD
PP
W U
I RP UHVSHFW
LYH 5*%VHULHV&DSDFLW
RUV
R335 GRN_GR 5 12
100uF/6.3V 2B1 4A
U312 2N7002E GND 0.1uF 5K
2
22uH/0.5A/<1R 1% Y_FIL 6 11 BLU_GR GND GND GND
C327 2B2 3B1 R367
R327 R365 47K +5V_AUD
U309
5K 7 10 Pb_FIL
+3.3V_SW 1% 2A 3B2 1 16 2.2K
+5V_FIL This pin set H indicate output is set to tristate. NO0B VCC
3
R336 8 9 R384
C318 GND 3A 2 15 GND
R307 +3.3V_SW 5K R338 R341 NO1B NO1A Q304 47K
47uF/6.3V R337 1
C320 1% GND NC NC 2SC1815Y
10K NC MUX_R 3 14
+
C314 C315 C316 330nF C325 MUX_R COMB NO2A
B B
R398 22uF/6.3V C354
1% DPF_Raudio4 13 VGA_L
1
2
C317 0.1uF 0.1uF 0.1uF NO3B COMA 47uF/16V
10k
0.1uF GND
5 12
GND C321 NO2B NO0A R385
R380
MSTR_SCL 3 2 GND 100uF/6.3V R328 GND 47K
C366 6 11 DPF_Laudio 2.2K
C365 C367 5K Inhibit NO3A
10uF/6.3V
U313 10uF/6.3V 10uF/6.3V +5V_AUD
7 10 GND
2N7002E VEE ADDB
GND GND GND R357 1
U305 8 9
GND GND ADDA 10K
R386 2
3
1 28 A-HS Q305 R356
REF1 REF2 GND NLAS4052 47k
2SC1815Y 22K 3
2 27 A-VS VGA_R 1 AVP300
VDD REF3
R345 100 AV-1
+
R397 100 U307 FSAV330M Set_tristate1 DVI_R GND
3 26 +5V_MUX Set_tristate1
SDA VCC1 R346 C355 R358
1 16 100 ChannelSel1 GND
VGA Audio Input
2
R360 100 SEL VCC ChannelSel1 47uF/16V 10K
4 25 Y_OUT
SCL OUT1A R321 R323 R347 100
Teltext_R 2 15 This pin set H indicate output is set to tristate. ChannelSel2 +5V_AUD R383
47K 47K 1B1 /OE ChannelSel2 R391
5 24 Set_tristate2 2.2K
C359 VSS OUT1B +5V_MUX Set_tristate2 47K R375
Scart1_R 3 14 R348 100 R387
3
2.2uF/6.3V 1B2 4B1 22K
6 23 47K
MUXSEL GND1 GNDGND GND
4 13 C347 GND
1A 4B2 MUX_L 1
7 22 10uF/16V MUX_L
Component Video Inputs ADS VCC2
+
+5V_MUX Teltext_G 5 12 R348A
C312 0.1uF 2B1 4A
Y_YPBPR GND 8 21 PB_OUT R348B C356
Y_YPBPR IN1A OUT2A 100
GND
2
Scart1_G 6 11 Teltext_B U308 47uF/16V
2B2 3B1 100 Q306
C360 DPF_G 9 20 1 16
IN1B OUT2B NO0B VCC DELETE BUFFER 2SC1815Y
2.2uF/6.3V R362 7 10 Scart1_B R388
R359 2A 3B2 R373
10 19 5K Teltext_VS 2 15 Teltext_HS R381 47K
ISET GND2 NO1B NO1A 10k 1
1% 8 9 SN74LVC14AD SN74LVC14AD 2.2K
1.8k GND 3A
B_YPBPR GND 11 18 C339 3 14 DPF_H U310A U310C +5V_AUD 2
B_YPBPR IN2A VCC3 COMB NO2A GND
0.1uF GND
3
C313 DPF_B 12 17 PR_out 4 13 1 2 5 6 R372
IN2B OUT3A FSAV330M Truth Table NO3B COMA AHS AVP303
0.1uF 22K
GND AV-1
3
R_YPBPR 13 16 R363 S /OE FUNCTION DPF_V 5 12 Q307 R389
R_YPBPR IN3A OUT3B NO2B NO0A C357 GND
5K U310B U310D +5V_AUD 2SC1815Y 47k
C336 X H DISCONNECT 47uF/16V R374 DVI Audio Input
1% Schmitt Triggers
TAB1
TAB2
DPF_R 14 15 6 11 1 10K
0.1uF IN3B GND3 Inhibit NO3A
L L A=B1 3 4 9 8
+
C361 Low:Select VGA HS/VS. AVS R369
7 10 DVI_L
2.2uF/6.3V L H A=B2 VEE ADDB 2.2K
SM5301AS C338 L302 High:Select TeltextHSVS. +5V_MUX
2
R376
100uF/6.3V GND +5V_ANG 22uH/0.5A/<1R +5V_MUX 8 9 SN74LVC14AD SN74LVC14AD
29
30
GND ADDA R382 R390 22K

C362
R5 2.2K 47K
2.2uF/6.3V NLAS4052 GND
4.7K
GND GND GND GND
+5V_MUX
C340 C341 C342 C343 C344 HV_SEL
C345 10uF/16V 0.1uF 0.1uF 0.01uF 0.01uF GND
CN306 0.1uF C363 R4
1 DPFR 2.2uF/6.3V DPF_R
4.7K
3
2 R364 +5V_AUD Q303
3 DPFG Sel_HsVs 2SC2712Y
R377 GND
4 100 1 R371 AudioSelADDB
75 U301 R368 AudioSelADDB
5 DPFB C349
0.1uF DPF_G EL1883L 2.2K 10K
A 6 C351 +5V_MUX A
3
+3.3V_DIG R392
7 DPF_H 0.1uF 1 8
2
Teltext_HS 620 CYSNCout VDD
8 DPF_V GND Scart1VideoIN 2 7 Q302 GND
Video-in HSYNCout 1 R370 AudioSelADDA
9 R379 3 6 2SC1815Y AudioSelADDA
Teltext_VS VSYNCout RESET 10K
10 DPF_Raudio 75 4 5
C364 C346 GND Burst/Porchout R393
11 C353 C352
2.2uF/6.3V
2
12 DPF_Laudio R355 R361 680K
GND 0.1uF 470pF 0.1uF GND
13 47K 47K
GND
DPF_B
CON-13 R324 R395
C350 R394
GND 47K 47K GND GND
0.1uF GNDGND GND GND
47K NLAS4052 Truth Table
R355A R329 R378
B A FUNCTION
0 47K 75
GND 0 0 COMA=NO0A; COMB=NO0B
GND Title
GND 0 1 COMA=NO1A; COMB=NO1B
GNDGND GND
GND
1 0 COMA=NO2A; COMB=NO2B
R361A Size Number Revision
1 1 COMA=NO3A; COMB=NO3B
0 Orcad D
Inhabit=1:All output is open.
Drawn By:
1 2 3 4 5 6 7 8
RN700
1 2 3 4 5 6 7 8
22X4 RN701
FSDATAU0 5 4 FSDATA0
22X4
FSDATAU1 6 3 FSDATA1 FSCKEU 5 4 FSCKE
FSCKE
FSDATAU2 7 2 FSDATA2 /FSRASU 6 3 /FSRAS
/FSRAS
FSDATAU3 8 1 FSDATA3 /FSCASU 7 2 /FSCAS FSDQM[0..3]
/FSCAS FSDQM[0..3]
C701 C700 C702 C703 +1.8V_CORE FSDATAU4 5 4 FSDATA4 FSDQMU1 8 1 FSDQM1
47uF/6.3V 47uF/6.3V 0.1uF 0.1uF FSDATAU5 6 3 FSDATA5 /FSWEU 5 4 /FSWE
/FSWE
C704 C705 C706 C707 C708 C709 C710 FSDATAU6 7 2 FSDATA6 FSDQMU2 6 3 FSDQM2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +3.3V_LBADC FSDATAU7 8 1 FSDATA7 FSDQMU3 7 2 FSDQM3
C711 C712 C713 C714 C715 FSDQMU0 8 1 FSDQM0
RN700A
22X4 RN701A
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +1.8V_CORE +3.3V_I/O_BGA +2.5V_DDR +3.3V_LVDSB +3.3V_LVDSA
+3.3V_LVDS FSVREF +1.8V_DVI +3.3V_DVI
+1.8V_ADC +3.3V_ADC +3.3V_PLL FSDATAU[0..31] RN702 22X4
FSDATA[0..31]
22X4 FSDATA[0..31]
GND
AA23
AD12
AD13
AD20
AC10
AB23
AC23
AC12
AC22
AC21
7 2
AE17
FSDATAU10 FSDATA10
AA4
W23
W25
AC4
AC6
AC8
AB4
M23
K17
U17
U11
K10
K16
U16
U10
K11
K23
D17
D23
D22
H23
V23
Y23
D10
C13
R23
C11
C10
L16
T16
T17
L11
T11
L23
T23
E23
P23
F23
W4
J23
J24
U700 FSDATAU11 8 1 FSDATA11
Y4
D6
D8
D9
A3
A4
A2
D3
G1
H3
H1
C9
C8
C6
B3
E3
F4
F2
J3
J1
GM1601 RN703
+2.5V_DDR FSDATAU13 6 3 FSDATA13
22X4
BGA416 FSDATAU14 7 2 FSDATA14 FSADDRU9 5 4 FSADDR9
FSVREF
FSVREF
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
FS_2.5
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
IO_3.3
VDDA33_PLL
VDDA33_FPLL
VDDA18_DLL
LVDSA_3.3
LVDSA_3.3
LVDSA_3.3
LVDSB_3.3
LVDSB_3.3
LVDSB_3.3
DVI_1.8
DVI_1.8
DVI_1.8
DVI_1.8
DVI_3.3
DVI_3.3
DVI_3.3
DVI_3.3
DVI_3.3
VDDA33_RPLL
LBACD-33
VDDD33_LVDS
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
CORE_1.8
VDDA33_SDDS
VDDA33_SDDS
VDDA33_DDDS
VDDA33_DDDS
ADC_1.8
ADC_1.8
ADC_3.3
ADC_3.3
ADC_3.3
ADC_3.3
C716 C718 C719 C720 C721 C722 C723 C724 C725 C726 FSDATAU15 8 1 FSDATA15 FSADDRU4 6 3 FSADDR4
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF FSADDRU5 7 2 FSADDR5
RN702A
C727 C728 C729 E24 FSDATAU0 FSADDRU6 8 1 FSADDR6
FSDATA0 22X4
E25 FSDATAU1 FSADDRU7 5 4 FSADDR7
FSDATA1
0.1uF 0.1uF 0.1uF N4 E26 FSDATAU2 FSADDRU8 6 3 FSADDR8
D DVI_SCL DVI_SCL FSDATA2 D
N3 G26 FSDATAU3 FSBKSELU1 7 2 FSBKSEL1
DVI_SDA DVI_SDA FSDATA3 FSBKSEL1
A8 G24 FSDATAU4 FSBKSELU0 8 1 FSBKSEL0
RX0+ RX0+ FSDATA4 22X4 FSBKSEL0
B8 H26 FSDATAU5
RX0- RX0- FSDATA5 RN704A RN703A 22X4
GND A9 H24 FSDATAU6 FSDATAU16 5 4 FSDATA16
RX1+ RX1+ FSDATA6
B9 J25 FSDATAU7 FSDATAU17 6 3 FSDATA17 RN705
RX1- RX1- FSDATA7 22X4
+3.3V_I/O_BGA A10 T26 FSDATAU8 FSDATAU18 7 2 FSDATA18
RX2+ RX2+ FSDATA8
B10 R25 FSDATAU9 FSDATAU19 8 1 FSDATA19 5 4
RX2- RX2- FSDATA9
A6 P24 FSDATAU10 FSDATAU20 5 4 FSDATA20 6 3 FSADDR[0..11]
RXC+ RXC+ FSDATA10 FSADDR[0..11]
B6 P26 FSDATAU11 FSDATAU21 6 3 FSDATA21 FSADDRU0 7 2 FSADDR0
RXC- RXC- FSDATA11
C735 C736 C737 C738 C739 C740 C741 C742 C743 R700 D5 N24 FSDATAU12 FSDATAU22 7 2 FSDATA22 FSADDRU1 8 1 FSADDR1
NO_CONNECT FSDATA12
C733 270 C5 N26 FSDATAU13 FSDATAU23 8 1 FSDATA23 FSADDRU2 5 4 FSADDR2
NO_CONNECT FSDATA13
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF B11 M25 FSDATAU14 RN704 FSADDRU3 6 3 FSADDR3
+3.3V_DVI REXT FSDATA14 22X4
L24 FSDATAU15 FSADDRU10 7 2 FSADDR10
FSDATA15
L25 FSDATAU16 FSADDRU11 8 1 FSADDR11
FSDATA16 22X4
BLUE- B1 M26 FSDATAU17
BLUE- BLUE- FSDATA17 RN706 RN705A
GND BLUE+ B2 M24 FSDATAU18 FSDATAU24 5 4 FSDATA24
BLUE+ BLUE+ FSDATA18 22X4
+1.8V_DVI GREEN- C1 N25 FSDATAU19 FSDATAU25 6 3 FSDATA25
GREEN- GREEN- FSDATA19
GREEN+ C2 N23 FSDATAU20 FSDATAU26 7 2 FSDATA26
GREEN+ GREEN+ FSDATA20
RED- D1 P25 FSDATAU21 FSDATAU27 8 1 FSDATA27
RED- RED- FSDATA21
RED+ D2 R26 FSDATAU22 FSDATAU28 5 4 FSDATA28
RED+ RED+ FSDATA22
C746 C747 C748 C749 SOG C3 R24 FSDATAU23 FSDATAU29 6 3 FSDATA29
SOG SOG FSDATA23
A1 K24 FSDATAU24 FSDATAU30 7 2 FSDATA30 3ODFH 6HULHV WHUP LQDW
LRQUHVLVW
RUV RQDOOD GGUHVV DQG FRQWUROOLQHV YH U \ FO
R VH W
R JP %* $
NO_CONNECT FSDATA24 Unloaded trace impedance on this interface is 90 Ohm
0.1uF 0.1uF 0.1uF 0.1uF +3.3V_PLL GND +3.3V_PLL VGA_SCL N2 J26 FSDATAU25 FSDATAU31 8 1 FSDATA31 Loaded trace impedace with DRAM load is 65 Ohm (for 2.5 inch total trace
VGA_SCL VGA_SCL FSDATA25
VGA_SDA N1 H25 FSDATAU26 length) +5V_4A
R701 VGA_SDA VGA_SDA FSDATA26 RN706A RPT1 RPT2
AHS L4 G23 FSDATAU27
AHS AHSYNC FSDATA27 22X4
C756 C757 10K/5% AVS L3 G25 FSDATAU28 4.7K 1K
AVS AVSYNC FSDATA28
3
GND R4 F24 FSDATAU29

EXTCLK FSDATA29
22pF 22pF F25 FSDATAU30 GND
FSDATA30 RPT8
+3.3V_DVI 2 1 GND F26 FSDATAU31 FSADDRU[0..11]
FSDATA31
XTAL G4
XTAL Place Series termination resistors on bidirectional lines-DATA and DQS midway between gm1601 BGA and memory 0
TCLK G3
TCLK RPT7
X700 F1
NO_CONNECT
C752 C753 C754 C755 14.318MHz K3 AD25 FSADDRU0 NC
NO_CONNECT FSADDR0 Max trace length on this interfce is 2.5 inches
C750 ACS_RSET_HD K2 AD26 FSADDRU1
ACS_RSET_HD FSADDR1 0LQLPL]H WUDFH OHQJ K
W GL I IHUHQFH E HW ZHHQ' 46 DQ GGDW
D DQG
DPRQJ W
KH GDW
D OLQHV RPT6
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF AC24 FSADDRU2 To OS Driving of Sharp
FSADDR2
VRED0 C19 AC25 FSADDRU3 CONPT1
VRED0 FSADDR3 0
R703 VRED1 B19 AB26 FSADDRU4 Pin 2\4\6 Should Be Set 3.3V 7
VRED1 FSADDR4
3.3K VRED2 A19 AA24 FSADDRU5 6
VRED2 FSADDR5
GND VRED3 D18 AA25 FSADDRU6 5
VRED3 FSADDR6
VRED[7..0] VRED4 C18 AA26 FSADDRU7 4
VRED[7..0] VRED4 FSADDR7 RPT4
VRED5 B18 Y24 FSADDRU8 3
VRED5 FSADDR8
VRED6 A18 AB25 FSADDRU9 2
VRED6 FSADDR9 0
GND VRED7 C17 AC26 FSADDRU10 FSCLK+, FSCLK- should be routed like a differentail pair 1
2 S W L R Q D O )LOWH U &DSV LQ EHWZ HHQ D S DLU RQ /%$'& G LIIHUHQ WLDO W U D F N V FORVH W R WKH 0DOLEX FKLS VRED7 FSADDR10 RPT3
AB24 FSADDRU11
FSADDR11
VGRN0 A23
VGRN0 NC
VGRN1 C22 U24 FSCLK+
VGRN1 FSCLKp FSCLK+
VGRN2 B22 U23 FSCLK-
VGRN2 FSCLKn FSCLK-
VGRN[7..0] VGRN3 A22
VGRN[7..0] VGRN3
VGRN4 D21 L26 FSDQSU R705 FSDQS
VGRN4 FSDQS FSDQS
VGRN5 C21 33
VGRN5
VGRN6 B21 T25 FSDQMU0
VGRN6 FSDQM0 R71 NC
C VGRN7 A21 U25 FSDQMU1 C
VGRN7 FSDQM1 JP701
U26 FSDQMU2
FSDQM2 +5V_4A R72 NC
VBLU0 B25 T24 FSDQMU3 1
VBLU0 FSDQM3
Set VOL- 、 VOL+、 CH- 、 CH+、 AV/TV、 MENU and POWER totally 7keys on Keyboard. VBLU1 A25
VBLU1 FSWE
V26 /FSWEU 2
VBLU[7..0] VBLU2 D24 V25 /FSCASU 3
VBLU[7..0] VBLU2 FSCAS J700
VBLU3 C24 V24 /FSRASU 4
VBLU3 FSRAS R704
+3.3V_DIG VBLU4 B24 W26 FSCKEU PanelP 5 +3.3V_SW 1
VBLU4 FSCKE
VBLU5 A24 Y25 FSBKSELU0 NC 6 +5V_SW 2
VBLU5 FSBKSEL0
VBLU6 C23 Y26 FSBKSELU1 7 3
VBLU6 FSBKSEL1 R740 100
C760 VBLU7 B23 8 MSTR_SCL 4
47uF/6.3V VBLU7
TXA3+ 9 MSTR_SDA 5
C799 C798 TP700 VCLK A20 C730 + C731Panel_Power JP700 TXA3- 10 6
VCLK VCLK R741 100
GND 0.1uF 0.1uF Q700 B20 0.1uF 20PIN TXAC+ 11 C290 C291
VODD
2SC1815Y VVS C20 0.1uF TXAC- 12 0.1uF 0.1uF
VVS VVS CON6
VHS D19 AC18 1 13
VHS VHS_CSYNC GPIO_G06_B0
CN700 Q701 TP711 TP712 CHKARM D20 AD18 2 14 GND
R706 VDV GPIO_G06_B1
CN-5 1 GND GND 2SC1815Y ENBARM B17 Gm1601 AE18 3 R708GND R729 R730 GND TXA2+ 15 GND GND
220 VCLAMP GPIO_G06_B2
2 LED1_KEYPAD AF18 GNDL 4 NC NC NC R732 TXA2- 16
GPIO_G06_B3
3 LED2_KEYPAD C26 AE19 TXA3+ 5 R728 R731 NC TXA1+ 17
R719 1K PWM0 A3+
4 IRDATA PWM1 C25 AF19 TXA3- 6 NC NC TXA1- 18
PWM1 A3-
5 PWM2 D26 AE20 TXAC+ 7 TXA0+ 19
R707 PWM2 AC+
PWM3 D25 AF20 TXAC- 8 TXA0- 20 Panel_Power
220 R711 1K OCM_TIMER1 AC-
GND GNDL 9 21
CN701
To programable filter. DVDKEY A12 LCD TV / MONITOR CONTROLLER 10 22
LBADC_IN3
1 ADC_IN2 B12 AD21 11 23 PanelP
CN-4 LBADC_IN2 GPIO_G05_B0
2 ADC_IN1 C12 AD22 12 24
LBADC_IN1 GPIO_G05_B3
3 D12 AE21 TXA2+ 13 PanelP 25 U1
LBADC_RETURN A2+ R734 R3
4 C796 C797 AF21 TXA2- 14 26 IRF7314
A2- C1 3.3K
ITRU0 C16 AE22 TXA1+ 15 R733 27 1 8
SVDATA0 A1+ 0.1 S D
470pF 470pF R717 R718 GND ITRU1 B16 AF22 TXA1- 16 0 0 R737 28 2 7
SVDATA1 A1- S D
R717A 10K/5% ITRU[7..0] ITRU2 A16 AE23 TXA0+ 17 0 29 3 6
GND GND GND 10K/5% ITRU[7..0] SVDATA2 A0+ S D
100K ITRU3 D15 AF23 TXA0- 18 30 4 5
SVDATA3 A0- G D
ITRU4 C15 19
SVDATA4
ITRU5 B15 AD23 R702 20
+3.3V_DIG SVDATA5 GPIO_G04_B0 22k R735 R736 FLATCABLE30 R2
ITRU6 A15 AD24
IRDATA SVDATA6 GPIO_G04_B1 3.3K Q1
+5V +3.3V_DIG ITRU7 D14 AE24 +3.3V_DIG GND 0 0 GNDL
SVDATA7 GPIO_G04_B2 2SC1815Y
To KeyControlBoard. +3.3V_DIG
GPIO_G04_B3
AF24
TP701 A17 AF25
R746 R738 RXD A14
SVDV
SVODD
GPIO_G04_B4
GPIO_G04_B5
AF26 For LG LC300W01 panel. +3.3V
0 NC TXD B14 AE25 R726 R720
R739 SVVSYNC GPIO_G04_B6
C760A C14 AE26 4.7k 22K
NC SVHSYNC GPIO_G04_B7 R715
C732 100pF +5V SVCLK D16
CN703 SVCLK SVCLK R1 GNDL
C795 0.1uF AE8 22 M_SCL TP777
R738A GPIO_G07_B0 M_SCL
0.1uF GND AF8 M_SDA 1K M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
1 100 GPIO_G07_B1 R716 M_SDA
M1 AC9 8759PowerDown PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP
2 OCM_UDO GPIO_G07_B2 8759PowerDown
M2 AD9 22 LCD-ON
3 OCM_UDI GPIO_G07_B3
GND GND AE9 SAA7115_EN
4 R738B GPIO_G07_B4 SAA7115_EN
U702 AF9 AudioSelADDA
100 GPIO_G07_B5 AudioSelADDA
3 HEADER 4 K1 AD10 AudioSelADDB
VCC GND GPROBE GND /RESET GPIO_G07_B6 AudioSelADDB
M4 AE10 Communication
IR1 GPIO_G07_B7 Communication
2 /RESET3.3V M3
RSTN IR0
MSTR_SCL P4
B MSTR_SCL MSTR_SCL B
GND
1
MSTR_SDA
MSTR_SDA P3
MSTR_SDA LVDS_SHIELD[0]
AF10 HIGH:
LVDS_SHIELD[1]
AC11 8759PowerDown
AD11
LVDS_SHIELD[2]
MAX809LEN GND +3.3V_DIG AE11
SOT23 LVDS_SHIELD[3] / 9 ' 6 3DQHFR
O QQHFW
RU,QW
HUIDFHVGLUHFW
O
\ W
R6; * $ DQG8; * $ / 9' 6 3DQHO
V
TP709 TP710 /OCM_WE R3 AF11
/OCM_WE /OCM_WE B3+ MA30 MA31 MA32 MA33
/OCM_RE R2 AF12
/OCM_RE /OCM_RE B3- PP PP PP PP
C717A /ROM_CS R1 AE12
/ROM_CS /ROM_CS BC+
CN702 1000pF CC_INT1 L1 AF13
/OCM_INT2 BC-
CON3 CC_INT L2
/OCM_INT1
TP702 /OCM_CS2 P2
/OCM_CS2
1 TP703 /OCM_CS1 P1 +3.3V_I/O_BGA
GND /OCM_CS1
2 /OCM_CS0 T4 AE13
/OCM_CS0 LVDS_SHIELD[4]
3 AD14
LVDS_SHIELD[5]
TP704 OCMADDR[0..19] AF14 +5V
OCMADDR[0..19] B2+
C717 OCMADDR19 T3 AE14 Reserved The Route.
OCMADDR19 B2- MA34 MA35 MA36 MA37
GND OCMADDR18 T2 AF15
OCMADDR18 B1+ PP PP PP PP
1000pF OCMADDR17 T1 AE15 R744 R745
OCMADDR17 B1-
OCMADDR16 U4 AF16 10K 10K TP705 TP706 TP707 TP708 +3.3V_DIG
GND OCMADDR16 B0+
FSVREF +1.8V_ADC OCMADDR15 U3 AE16 H1
OCMADDR15 B0-
OCMADDR14 U2 PPP10
OCMADDR14
OCMADDR13 U1
OCMADDR13 R742 R710
OCMADDR12 V4 R709
10
1
2
3
4
5
6
7
8
9
OCMADDR12 MA38 MA39 MA40 MA41
C767 C768 C769 C770 OCMADDR11 V3 AC7 100 NC DCLK 2.7K
OCMADDR11 DCLK PP PP PP PP
OCMADDR10 V2 AF17 DHS RESET_2310
OCMADDR10 GPIO_14
0.1uF 0.1uF 0.1uF 0.1uF OCMADDR9 V1 AD16 DVS
OCMADDR9 GPIO_15
OCMADDR8 W3 AD7 DEN Standby
OCMADDR8 GPIO_16
OCMADDR7 W2
OCMADDR7 R743
OCMADDR6 W1 TP714
GND GND OCMADDR6
OCMADDR5 Y3 100
OCMADDR5
OCMADDR4 Y2
OCMADDR4
+3.3V_ADC +3.3V_DIG OCMADDR3 Y1 AD8 JTAG_TRST
OCMADDR3 GPIO_G08_B5/JTAG_RESET
OCMADDR2 AA3 AF7
OCMADDR2 GPIO_G08_B4/JTAG_TDO
OCMADDR1 AA2 AE7
OCMADDR1 GPIO_G08_B3
TP758 OCMADDR0 AA1 AF6 MEC1 MEC2 MEC3 MEC4 MEC5 MEC6 MEC7
OCMADDR0 GPIO_G08_B2/JTAG_TDI
C772 C773 C774 C775 C776 AE6 PP PP PP PP PP PP PP
GPIO_G08_B1/JTAG_MODE R723 R727 R727A
47uF/6.3V C771 AD6 100 10K
GPIO_G08_B0/JTAG_CLK
0.1uF 0.1uF 0.1uF 0.1uF AF5 100 IRDATA/SCL
0.1uF GPIO_G09_B5
POWER_OFF AB3 AE5 State/SDA
POWER_OFF OCMDATA15 GPIO_G09_B4 R724
RGB/YPbPr_SEL AB2 AD5 MUTE
OCMDATA14 GPIO_G09_B3 +5V
+3.3V_PLL Set_tristate1 AB1 AC5 100
Set_tristate1 OCMDATA13 GPIO_G09_B2 HV_SEL
GND GND Set_tristate2 AC3 AF4 VGA_CAB R721 R722
Set_tristate2 OCMDATA12 GPIO_G09_B1 VGA_CAB
ChannelSel1 AC2 AE4 DVI_CAB 4.7K 4.7k
ChannelSel1 OCMDATA11 GPIO_G09_B0 DVI_CAB
ChannelSel2 AC1 +3.3V_DIG
ChannelSel2 OCMDATA10 R725
C778 C779 C780 C781 C782 C783 C784 Sel_HsVs AD1
Sel_HsVs OCMDATA9 100
C777 Teltext_MUTE AE1
Teltext_MUTE OCMDATA8
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF OCMDATA7 AF1 A26 PPWR C785
OCMDATA7 PPWR PPWR
OCMDATA6 AD2 B26 PBIAS
OCMDATA6 PBIAS PBIAS I2C address: A2H and A3H
OCMDATA5 AE2 R712 R713 0.1uF
OCMDATA5
OCMDATA4 AF2 AC17 +3.3V_DIG 2.7K 2.7K
OCMDATA4 NO_CONNECT
GND +3.3V_LVDSA +3.3V_LVDS OCMDATA3 AD3 AC16 OEXTR U701
OCMDATA3 OEXTR
OCMDATA2 AE3 AD15 8 1
OCMDATA2 D_GND VCC A0
A C786 OCMDATA1 AF3 7 2 A
OCMDATA1 WP A1
C788 C789 C790 OCMDATA0 AD4 R714 MSTR_SCL6 3
OCMDATA0 SCK A2
C787 0.1uF 3.3K MSTR_SDA5 4
SI VSS
47uF/6.3V 0.1uF 0.1uF 0.1uF
24LC32A-I/SN
VSSA33A_LVDS
VSSA33A_LVDS
VSSA33A_LVDS
VSSA33_DDDS GND SOIC8 (150mil BODY) GND

VSSD33_DDDS
VSSD33_LVDS
VSSA33_SDDS
VSSD33_SDDS
VSSA33_RPLL
LBADC_GND
VSSA33_FPLL
LVDSB_GND
LVDSB_GND
LVDSB_GND
GND GND
VSSA18_DLL
ADC_DGND
ADC_AGND
ADC_AGND
ADC_DGND
ADC_AGND
ADC_AGND
ADC_AGND
VSSD33_PLL
FSVREFVSS
FSVREFVSS
GND +3.3V_LVDSB GND

DVI_GND
DVI_GND
DVI_GND
DVI_GND
DVI_GND
DVI_GND
DVI_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
D_GND
C792 C793 C794

C791 OCMDATA[0..7]
OCMDATA[0..7]
47uF/6.3V 0.1uF 0.1uF 0.1uF
E2
E1
E4
M15
M11
M13
M12
M16
M14
M10
M17
F3
A13
U14
U15
N11
N17
N10
K12
N12
U12
N13
K14
N14
K25
K15
N15
N16
K13
U13
K26
A11
D11
D13
AD19
AD17
R15
R11
R10
R13
B13
R16
R12
R14
R17
AC13
AC14
AC15
AC19
AC20
J4
J2
L15
L12
T12
L13
L10
T13
T10
L14
T14
T15
L17
P15
P16
P12
P14
P13
P11
P17
P10
D4
A5
A7
D7
G2
H4
H2
K4
W24
B4
C4
B7
C7
B5
Title
GND
GND GND
Orcad D
Drawn By:
1 2 3 4 5 6 7 8
PQFP208
1 2 3 4
RN401 22X4
R406A ADUB00 4 5 VBLU0
ADUB11 3 6 VBLU1
75 U400A
ADUB22 2 7 VBLU2
TDA8759
C420 ADUB33 1 8 VBLU3
R406 49 ADUB44 4 5 VBLU4
REF_B/Pb
Q172 c4119 75 10n 22X4 ADUB55 3 6 VBLU5
R183 RN404A
2SC1815Y 10n 50 44 ADUB7 1 8 ADUB77 ADUB66 2 7 VBLU6
100 B/Pb3 VP27
TV_Bout 43 ADUB6 2 7 ADUB66 ADUB77 1 8 VBLU7
TV_Bout VP26
L174 PBout c4120 51 42 ADUB5 3 6 ADUB55 RN401A22X4
R174 B/Pb2 VP25
2.2uH 10n 41 ADUB4 4 5 ADUB44
75 VP24
TV_BBout c415 52 40 ADUB3 1 8 ADUB33 RN410 22X4
B/Pb1 VP23
10n 39 ADUB2 2 7 ADUB22 RN404 ADVR00 4 5 VRED0
R402 VP22 22X4
56 36 ADUB1 3 6 ADUB11 ADVR11 3 6 VRED1
BIAS VP21
R173 C179 C180 R175 R175A 12K 35 ADUB0 4 5 ADUB00 ADVR22 2 7 VRED2
VP20
470 330pF 330pF NC 75 R400 75 c416 62
REF_G/Y RN408A22X4 ADVR33 1 8 VRED3
R400A 10n 32 ADYG7 1 8 ADYG77 ADVR44 4 5 VRED4
VP17
75 c4121 63 31 ADYG6 2 7 ADYG66 ADVR55 3 6 VRED5
G/Y3 VP16
10n TDA8795 28 ADYG5 3 6 ADYG55 ADVR66 2 7 VRED6
VP15
Yout c417 64 27 ADYG4 4 5 ADYG44 ADVR77 1 8 VRED7
D G/Y2 VP14 D
10n 26 ADYG3 1 8 ADYG33 RN410A 22X4
VP13 RN408 X400
Q173 c410 65 25 ADYG2 2 7 ADYG22
R184 G/Y1 VP12 RN400 22X4 13.5MHz
2SC1815Y 10n 24 ADYG1 3 6 ADYG11 22X4
100 VP11 1 2
TV_Gout c418 72 23 ADYG0 4 5 ADYG00 ADYG00 4 5 VGRN0 C401
TV_Gout SOG/Y3 VP10 C400
L175 10n ADYG11 3 6 VGRN1 22pF
R180 RN406A 0.1uF 0.1uF
2.2uH c412 73 18 ADVR7 1 8 ADVR77 ADYG22 2 7 VGRN2
75 SOG/Y2 VP07 22X4 22pF C402 C403
3
TV_GGout 10n 17 ADVR6 2 7 ADVR66 ADYG33 1 8 VGRN3
VP06
R403A C419A74 16 ADVR5 3 6 ADVR55 ADYG44 4 5 VGRN4
SOG/Y1 VP05
75 10n 15 ADVR4 4 5 ADVR44 ADYG55 3 6 VGRN5
VP04 GND + C405 + C406
R179 C182 C183 77 10 ADVR3 1 8 ADVR33 ADYG66 2 7 VGRN6
REF_R/Pr VP03 R401 22uF/6.3V 22uF/6.3V 187R/1%
470 330pF 330pF c4122 c419 9 ADVR2 2 7 ADVR22 ADYG77 1 8 VGRN7
R403 VP02 470K/1% R404
75 10n 78 8 ADVR1 3 6 ADVR11 RN400A 22X4
R/Pr3 VP01 GND
10n 7 ADVR0 4 5 ADVR00
VP00 DACRST#
Yout c413 79 RN411 22X4
R181A R/Pr2 RN406 ADHS 1 8 VHS
)25 7( 673 85326( ,1 &$6( 2) ) /, 21 /<
R181 10n 1 VHS
22R/5%
22R/5%
22R/5%
75 HREF 22X4 ADVS 2 7 VVS C411 0.1uF
NC c414 10n 80 VVS
R/Pr1 3 6 GND RDACOUT
95 168 4 5 ADHS
HE HS ADCLK 4 5 VCLK GDACOUT
102 169 3 6 ADVS VCLK
COAST VS 3.3VS23 GND BDACOUT
103 2 7
R405 1K GAIN
104 1 8 ADCLK
R416
R417
GND CLAMP
uoc_vs 105 2 DAC1.8V
R409
R410
R411
VCC5A L171 VSYNC1 CKP RN402
75R/1%
106 DAC3.3V
R418
R452 VSYNC2 47X4
107 PLL1.8V
75R/1%
47 VSYNC3 C4123
TV_Csync R413 108 94 MA1 MA2MA3 When FLI2300 is not installed,where should SHREF be connected?
75R/1%
C172 C174 TV_Csync HSYNC1 OE NC
NC 109 PP PP PP
10V22uF 0.1uF HSYNC2
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
110 166 GND
Q171 HSYNC3 PL GND 1.8VS23
uoc_hs R451 111 167 U401
2SC1815Y CKEXT DE
R182 22 113
TV_Rout TCLK
AVSS_PLL_SDI
XTAL OUT
DAC_VREFOUT
DAC_GOUT
DAC_ROUT
DAC_BOUT
R456
TEST2
TEST1
TEST0
AVSS_PLL_FE
AVDD_PLL_FE(1.8)
PLL_PVDD(1.8)
VSSio
AVDD_PLL_SDI(1.8)
AVSS_PLL_BE2
AVSS_PLL_BE1
AVDD_PLL_BE2(1.8)
AVDD_PLL_BE1(1.8)
FID_PORT2
VDD9(3.3)
HS_PORT2
VS_PORT2
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
D1_IN_1
VDDcore8(1.8)
D1_IN_0
IN_CLK_PORT2
DAC_RSET
DAC_PVDD(3.3)
DAC_VDD(1.8)
DAC_PVSS
DAC_AVDDG(3.3)
DAC_GR_AVDD(3.3)
DAC_AVSS
DAC_COMP
DAC_AVDDR(3.3)
DAC_AVDDB(3.3)
DAC_VSS
DAC_AVSSG
DAC_GR_AVSS
TV_Rout 170 VHS
XTAL IN
PLL_PVSS
VSScore
DAC_VREFIN
DAC_AVSSR
DAC_AVSSB
DAC_AVDD(3.3)
L172 CS GND
100 171 NC
R172 2.2uH R414 ORR/V
SDA_V 118 172
75 TV_RRout SDA ORB/U
SCL_V R412 100 119 173 3.3Vcore
SCL ORG/Y R415 ADHS VGRN[7..0]
100 114 174 VGRN[7..0]
DIS VAI ADVS
96 175 4.7K
R171 C171 C173 A0 FREF 1 156 2300OE# RN403A22X4
176 HSYNC1_PORT1 OE
470 330pF 330pF VREF ADCLK 2 155 FLIGRN7 5 4 VGRN7
VSYNC1_PORT1 G/Y/Y_OUT_7
3 154 FLIGRN6 6 3 VGRN6
3.3V_out U400B FIELD ID1_PORT1 G/Y/Y_OUT_6
4 153 FLIGRN5 7 2 VGRN5
TDA8759 IN_CLK1_PORT1 G/Y/Y_OUT_5
R176 R176A GND 5 152 FLIGRN4 8 1 VGRN4
HSYNC2_PORT1 G/Y/Y_OUT_4
NC 75 6 151 FLIGRN3 5 4 VGRN3
164 165 VSYNC2_PORT1 G/Y/Y_OUT_3
Vp OGND 7 150 FLIGRN2 6 3 VGRN2
3 4 FIELD ID2_PORT1 G/Y/Y_OUT_2
Vp OGND 8 149 FLIGRN1 7 2 VGRN1
3.3V_out 13 14 VDD1(3.3) G/Y/Y_OUT_1
R454 Vp OGND 9 148 FLIGRN0 8 1 VGRN0 VRED7..0]
21 22 VSSio G/Y/Y_OUT_0 VRED[7..0]
Vp OGND ADUB00 10 147 RN403 22X4
1K R444 29 30 IN_CLK2_PORT1 VSSio
Vp OGND ADUB11 11 146 22X4
1
37 38 B/Cb/D1_0 VDD8(3.3) RN405

4.7K Vp OGND ADUB22 12 145 FLIRED7 5 4 VRED7
45 46 B/Cb/D1_1 R/Y/Pr_OUT_7
Vp OGND ADUB33 13 144 FLIRED6 6 3 VRED6 VBLU[7..0]
11 B/Cb/D1_2 R/Y/Pr_OUT_6 VBLU[7..0]
1.8Vcore Vcore ADUB44 14 143 FLIRED5 7 2 VRED5
MSTR_SDA 3 2 SDA_V 116 12 B/Cb/D1_3 R/Y/Pr_OUT_5
Vcore DGND ADUB55 15 142 FLIRED4 8 1 VRED4
130 TDA8759 117 B/Cb/D1_4 R/Y/Pr_OUT_4
U404 2N7002E 132 127 VDDcore1(1.8) R/Y/Pr_OUT_3
158 131 VSScore R/Y/Pr_OUT_2
3.3V_out Vcore DGND 18 139 FLIRED1 7 2 VRED1
R455 159 B/Cb/D1_5 VSScore
DGND 19 138 FLIRED0 8 1 VRED0
138 133 B/Cb/D1_6 VDDcore7(1.8)
1k R453 3.3Vcore Vcore DGND 20 FLI2310 137 RN405A 22X4
139 142 B/Cb/D1_7 R/Y/Pr_OUT_1
1
Vcore DGND ADVR00 21 136

4.7k 145 148 R/Cr/CbCr_0 R/Y/Pr_OUT_0
Vcore DGND ADVR11 22 135 22X4
C 151 154 R/Cr/CbCr_1 B/U/Pb_OUT_7 RN407 C
Vcore DGND ADVR22 23 134 FLIBLU7 5 4 VBLU7
157 R/Cr/CbCr_2 B/U/Pb_OUT_6
MSTR_SCL 3 2 SCL_V Vcore ADVR33 24 133 FLIBLU6 6 3 VBLU6
48 47 GND R/Cr/CbCr_3 B/U/Pb_OUT_5
3.3Vcca Vcca AGND ADVR44 25 132 7 2 VBLU5
U406 HIGH: 8759PowerDown 54
VccA AGND
53
ADVR55 26
R/Cr/CbCr_4 B/U/Pb_OUT_4
131
FLIBLU5
FLIBLU4 8 1 VBLU4
61 55 R/Cr/CbCr_5 B/U/Pb_OUT_3
2N7002E Vcca AGND ADVR66 27 130 FLIBLU3 5 4 VBLU3
67 57 R/Cr/CbCr_6 B/U/Pb_OUT_2
Vcca AGND ADVR77 28 129 FLIBLU2 6 3 VBLU2
69 58 R/Cr/CbCr_7 VSSio
Vcca AGND ADYG00 29 128 FLIBLU1 7 2 VBLU1
76 60 G/Y/Y_0 VDD7(3.3)
Vcca AGND 30 127 FLIBLU0 8 1 VBLU0
8759PowerDown 82 66 VDD2(3.3) B/U/Pb_OUT_1
Vcca AGND 31 126
59 68 VSSio B/U/Pb_OUT_0
Vbias AGND ADYG11 32 125 FLICLK R432 RN407A 22X4
L402 70 G/Y/Y_1 CLKOUT
AGND ADYG22 33 124 22R/5%
+3.3V_SW 10uH 3.3V_out L404 123 71 G/Y/Y_2 VSScore
3.3Vcore Vi2c AGND ADYG33 34 123 1 TP400 1 TP401
+1.8V_SW 10uH 1.8Vpll 75 G/Y/Y_3 VDDcore6(1.8)
R408 AGND ADYG44 35 122
C427 8759Powerdown 93 81 G/Y/Y_4 CTLOUT4
C430 C433 C436 C438 C440 C443 C445 + C446 PD AGND 36 121
100 85 83 VDDcore2(1.8) CTLOUT3
22u/10V 3.3Vcca Vfro AGND 37 120 FLIHREF
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u VSScore CTLOUT2
+C457 ADYG55 38 119 FLIVS R434
C450 87 G/Y/Y_5 CTLOUT1
22u/10V 1.8Vpll Vpll_1.8v ADYG66 39 118 FLIHS 22R/5%
GND 0.1uF 88 84 G/Y/Y_6 CTLOUT0
3.3Vpll Vpll_3.3v AGND_pll TP402 ADYG77 40 117
86 G/Y/Y_7 TEST OUT1
AGND_pll 1 R437 100R/5% 41 116 1 TP403 1 TP404
L401 GND IN_SEL TEST OUT0
42 115
+3.3V_DEC 10uH 3.3Vcca 120 TEST TEST3
DGNDi2c DEVADDR1 43 114
C454 156 126 DEV_ADDR1 SDRAM CLKIN
C455 NC DGNDi2c DEVADDR0 44 113
L405 0.1uF 155 DEV_ADDR0 VSSio
+ C444 0.1uF NC SCL_V R438 100R/5% 45 112
C423 C425 C428 C431 C434 C437 C439 +3.3V_DEC 10uH 3.3Vpll 153 GND SCLK VDD6(3.3)
0.1u 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22u/10V NC SDA_V R439 100R/5% 46 111 SDCKO 100R/5% R440 2 3 S D C L K
152 SDATA SDRAM CLKOUT 23SDCLK
NC RESET_2310 R442 100R/5% 47 110 23SDDQM
150 RESET_2310 RESET_N SDRAM DQM 23SDDQM
NC 48 109 23SDCS#
GND 149 VDD3(3.3) SDRAM CSN 23SDCS#
+C458 NC 49 108 23SDBA0
C451 147 VSSio SDRAM BA0 23SDBA0
22u/10V NC 23SDD0 50 107 23SDBA1
0.1uF 146
NC TST17
163 Reset SAA7115 on the same time. 23SDD1 51
SDRAM D0 SDRAM BA1
106 23SDCAS#
23SDBA1
144 162 SDRAM D1 SDRAM CASN 23SDCAS#
SDRAM ADDR10
NC TST16 23SDD2 52 105 23SDRAS#
SDRAM ADDR9
SDRAM ADDR8
SDRAM ADDR7
SDRAM ADDR6
SDRAM ADDR5
SDRAM ADDR4
SDRAM ADDR3
SDRAM ADDR2
SDRAM ADDR1
SDRAM ADDR0
GND 143 161 SDRAM D2 SDRAM RASN 23SDRAS#
NC TST15 23SDWE#
VDDcore3(1.8)
VDDcore4(1.8)
VDDcore5(1.8)
L400 141 160 23SDWE#
SDRAM WEN
NC TST14 23SDA[10..0]
SDRAM D10
SDRAM D11
SDRAM D12
SDRAM D13
SDRAM D14
SDRAM D15
SDRAM D16
SDRAM D17
SDRAM D18
SDRAM D19
SDRAM D20
SDRAM D21
SDRAM D22
SDRAM D23
SDRAM D24
SDRAM D25
SDRAM D26
SDRAM D27
SDRAM D28
SDRAM D29
SDRAM D30
SDRAM D31
+3.3V_SW 10uH 3.3Vcore L403 140 125 23SDA[10..0]
SDRAM D3
SDRAM D4
SDRAM D5
SDRAM D6
SDRAM D7
SDRAM D8
SDRAM D9
NC TST13
VDD4(3.3)
VDD5(3.3)
+1.8V_SW 10uH 1.8Vcore 137 124 23SDD[31..0] 23SDD[31..0]
NC TST12
VSScore
VSScore
VSScore
TEST IN
136 122
VSSio
VSSio
NC TST11 R449
135 121
+ C435 NC TST10 22R/5%
C422 C424 C426 C429 C432 + 134 112
22u/10V C442 + C456 NC TST9 GND
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C447 C448 C449 C452 C453 129 101 +3.3V_SW
470u/10V 22u/10V NC TST8 RN409 C4125
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 128 100
NC TST7 22 NC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
GND 115 99
NC TST6 FLICLK 1 8 VCLK
GND 34 98 VCLK
NC TST5 2 7
10K/5%
FLIHREF
33 97
NC TST4 3 6 VHS
10K/5%
10K/5%
FLIHS
R445
R447
20 92 VHS
NC TST3 4 5 VVS
TDA8759 AD Power Supply. 19 91 FLIVS VVS
R446
NC TST2
6 90
NC TST1
23SDA10
23SDA9
23SDA8
23SDA7
23SDA6
23SDA5
23SDA4
23SDA3
23SDA2
23SDA1
23SDA0
5 89
NC TST0
23SDD10
23SDD11
23SDD12
23SDD13
23SDD14
23SDD15
23SDD16
23SDD17
23SDD18
23SDD19
23SDD20
23SDD21
23SDD22
23SDD23
23SDD24
23SDD25
23SDD26
23SDD27
23SDD28
23SDD29
23SDD30
23SDD31
23SDD3
23SDD4
23SDD5
23SDD6
23SDD7
23SDD8
23SDD9
GND GND
GND
23SDA[10..0]
+3.3V_SW 3V3D 2300OE#
23SDD[31..0]
L406 DEVADDR1
DEVADDR0
10uH
NOTE: FLI2300 could be used in place of FLI2310

+3.3V_DEC 3V3A
L407
B 10uH B
R425 100R/5% SCL_V

R426 100R/5% SDA_V
FB411 +1.8V_SW
1 2
+3.3V_SW 3.3VS23
+
L409
98
99
97
23
17
11
25
51
75
33
43
58
68
83
93
72
71
70
69
67
66
65
64
77
78
79
31
32
22
3
2
U402 C480 5.6uH/5%

GND
C459 22uF/6.3V
R420 DAC1.8V
SubchannelTV 47nF 10 54
TDI
VDDA0
VDDA1
VDDA2
SCL
VDDE
VDDE
VDDE
VDDE
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
AOUT
SubchannelTV AI24 IPD7 GND

TMS
TEST3
TEST4
TEST5
TRSN
TDO
TCK
HPD0
HPD1
HPD2
HPD3
HPD4
HPD5
HPD6
HPD7
SDA
VXDD
+
18R 55 C471 C472 C473 C474 C475 C476 C477 C478 C479
IPD6
C460 56 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C486 C487
R419 IPD5
Scart1VideoIN 47nF 12 57 22uF/6.3V 0.1uF
Scart1VideoIN AI23 IPD4
0 59
IPD3 FB412
C461 60
R424 IPD2
Scart2_CIn 47nF 14 61 1 2 L410
Scart2_CIn AI22 IPD1 +1.8V_SW 1.8VS23
0 62 GND 5.6uH/5%
IPD0
+
C462
R422 PLL1.8V
Video1_C_IN 47nF 16 42 C4104
Video1_C_IN AI21 ITRDY
+
0
SAA7115HL 45 22uF/6.3V C4105 C4106
C463 ICLK GND
13 46 C495 C496 C497 C498 C499 C4100 C4101 C4102 C4103 22uF/6.3V 0.1uF
AI2D IDQ
47nF 47 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
ITR1
48 L412
IGP0
C464 49 5.6uH/5%
R423 IGP1
Scart2_VideoIn 47nF 18 52 GND
Scart2_VideoIn AI12 IGPV +3.3V_SW DAC3.3V
0 53
IGPH
+
C465 37 C4118
R421 AMCLK
Video1_Y_IN 47nF 20 39
Video1_Y_IN AI11 ASCLK 22uF/6.3V
0 40
ALRCLK GND
41 C4111 C4112 C4113 C4114 C4115 C4116 C4117
AMXCLK
XTOUT
C466 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

RESON
VSSA0
VSSA1
VSSA2
AGND
XRDY
ALRCLK is used to seleted to 24.576MHZ crystal.

RTCO
TEST0
TEST1
TEST2
XCLK
VXSS
XPD7
XPD6
XPD5
XPD4
XPD3
XPD2
XPD1
XPD0
XTRI
47nF 19 6
VSSE
VSSE
VSSE
VSSE
LLC2
RTS0
RTS1
XRI1
XDQ
XRV
VSSI
VSSI
VSSI
AI1D XTAL
LLC
7
CE
XTAL1
24.576MHz
SAA7115HL
100
C4004
27
24
15
9
21
5
26
38
50
63
76
88
28
29
30
34
35
36
44
73
74
81
82
84
85
86
87
89
90
92
91
96
95
94
80
4
Strapping' Clock
R429 R433 22P
NC R430R431 NC Y400
R435
NC NC TP405 TP406
NC
R428 GND C404 GND
ITRU7
ITRU6
ITRU5
ITRU4
ITRU3
ITRU2
ITRU1
ITRU0
56R GND 22P C4124

R436 NC DECOUPLING FOR FLI2310 +5V_SW +1.8V_SW
100
R450 SVCLK
SVCLK
+5V_SW U405 +3.3V_DEC U403
22 LM1117DTX-3.3 LM1117DTX-1.8
SAA7115_EN High is effective.
SAA7115_EN ITRU[0..7]
ITRU[0..7] 3 4 3 4
VIN TAB VIN TAB
GND
GND
2 2
A 'Strapping' I2C Slave TO-252 TO-252 A

C407 C408
C409 C491 C492 C490
1
1
3V3D 47uF/10V 47uF/6.3V 47uF/10V 47uF/6.3V
R441 0.1uF 0.1uF
3V3A ASSEMBLE RN700 TO RN707.
Open C494A + C4002
+C467 C468 C469 C470 C481 C482 C483 C484 C485 C488 C489 C493 R443 C494 C4003 C4001 WHEN FLI2310 IS PRESENT
100n 10u DO NOT ASSEMBLE RN710, RN711,RN712,RN713
10u 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 4.7K 100n 100n 100n
Leave 1sq inch- exposed copper area attached to Tab of U408 Leave 1sq inch- exposed copper area attached to Tab of U408
GND GND
GND GND
ASSEMBLE RN710, RN711,RN712,RN713
WHEN FLI2310 IS NOT PRESENT
DO NOT ASSEMBLE TO RN700 TO RN707.
Title

B
Drawn By:
1 2 3 4
1 2 3 4 5 6
R519 NC
R521A NC
R521 NC
1
32V-EN
CP7
C501A
1u CP9
0.1uF +5V_MCU
D U501 3 3 1u D
LM2596-5.0 DP3A
L500 TP504 R505 DP3 BAS62-A13
+12V_3A 4 U502
Feedback 1.2/0.5W BAS62-A13
1 33uH Panel_Power LM2596-5.0
Vin D502
ON/OFF
2
output SMB05 L501
12
12
+24V_1A 4
GND
Feedback
C500 C502 R502 + 1 +5V
Vin 33uH
470uF 0.1uF 47K 2
ON/OFF
output CP8
C502A C503
GND
C501 1u
0.1uF C505 100uF/35V C519
3
0.1uF 3 3
470uF
CP10
D500 C504 0.1uF
DP4A 1u
1N5824 470uF DP4
D501
3
BAS62-A13
1N5824 BAS62-A13
C517 +50V
0.1uF
2
GNDL
3
RP4
R501 10K
2.2k/0.5W
1 Q500
PPWR +32V
2SC2712Y
+32V
+5V +5V
CP21
2 50V100uF DP2
UPC574
GND R508 R510
47K 22K
GND
+5V U503 +3.3V R508A
LM1086CS-3.3 NC CP31
R503 R504 GND
Backlight_on_off 0.1uF
0 0
3 4
VIN TAB
3
GND
2 GNDL GND GNDL GND R506 R509
PBIAS 1 1 Q502
TO-263 PBIAS
2SC2712Y
C506 C509 10K Q501 10K
1
47uF/10V 47uF/6.3V 2SC2712Y
2
C C
GND GND
GND U505
+5V LM1117DTX-2.5
TO-252
+1.8V +1.8V_CORE +5V
Leave 1sq inch- exposed copper area attached to Tab of U902
Leave room for heat sink
U504 3 4
VIN TAB
LM1117DTX-1.8
GND
FB500 2
3 4 1 2
VIN TAB
C513
GND
D504 2 C511 C515
1
47uF/10V 0.1uF 47uF/6.3V
SOD4001 C508 TO-252
C510
C507 47uF/6.3V
1
47uF/10V 0.1uF
GND

+5V
GND
R507
+3.3V_ADC
47K
R507A
2
+3.3V_ADC +3.3V_DVI +1.8V +1.8V_DVI +3.3V_ADC +3.3V_PLL +3.3V_ADC +3.3V_I/O_BGA +3.3V_ADC +3.3V_LBADC 0 +2.5V_DDR
GND
D506
BAV99
L505 L504 L507 L510 L512 U507 3
R513 +3.3V
1 8
S1 D1
2 7 +3.3V_SW
B 47K G1 D1 B
2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R R516 3 6
100K S2 D2
Q503 4 5
G2 D2
2SC2712Y
1
GND R511 IRF7314
+1.8V
47K SO-8
GND
+3.3V_ADC +3.3V_LVDSA +1.8V +1.8V_ADC +3.3V_ADC +3.3V_LVDSB+3.3V_ADC +3.3V_LVDS +3.3V_ADC +3.3V_DIG
L506 L503 L508 L509 L511

R514
POWER_OFF
POWER_OFF
47K
2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R 2.2uH/0.5A/<1R R517
100K Q505
2SC2712Y
GND
GND
+5V_4A
Leave 1sq inch- exposed copper area attached to Tab of U907 +5V_ANG
U508
U506
R512 1 8 +5V_SW
+5V LM1117DTX-3.3 +3.3V_ADC S1 D1
47K 2 7
TO-252 G1 D1
3 6
S2 D2
4 5
3 4 G2 D2
VIN TAB
GND
IRF7314
2 SO-8
R515
C512 C514 C516
1
47uF/10V 0.1uF 47uF/6.3V 47K

A R518 A
100K
Q504
2SC2712Y
GND
GND
GND
Title

C
Drawn By:
1 2 3 4 5 6
1 2 3 4
+12V_3A +12V_DC
LA2
+
RA1 33uH
10 CA2 CA3
100uF/16V 0.1u
GND GND CA42 CA24
D 0.47uF 0.1uF D
JP7
DA1 1
NC DA2 QA1
2CK75D 2SA1015Y CA25 2
LA1
+12Vaudio_ctrl 0.1uF
CA38 33uH CON2
RA15 +
RA2 10n
470K 10K RA3 +12V_AUDIO CE1
CA53 150K +12V_AUDIO RE2
1u 10K
47uF/16V
+
CA39 CA33
CA55
0.1u RE1
+24V_4A
DA3
RA50
100K 0.1u 10n
U6 10K
When mode_in is Low,AMP is in class_D.
48
47
46
45
44
43
42
41
40
39
38
37
CA37
W05Z6.8B RA11 220uF/16V TPA3002D2 And the Mode_out is output High.
470K
CE2
BSRP
PVCCR
PVCCR
PVCCR
PVCCR
BSRN
PGNDR
PGNDR
ROUTN
ROUTN
ROUTP
ROUTP
MUTE
Low is mute/shutdown. CA49
1u RE4
10K
MUTE 1u
C C
CA44 1u 1 36 +12V_AUDIO
SD VCLAMPR RE3
MOL 2 35
MOL RINN MODE_OUT 10K
CA46 1u 3 34 Mode_in CA10 10u
RINP MODE
4 33
+
CA45 CA47 1u V2P5 AVCC
1u CA48 1u 5 32 CA34
LINP VAROUTR +5VE
MOR 6 31 0.1u
MOR LINN VAROUTL
7 TPA3002D2 30
AVDDREF AGND CA51 100n
15K 8 29
RA4 VREF AVDD
9 28
VARDIFF COSC CA52 220P
15k RA5 10 27
VARMAX ROSC RE6
11 26 RE5 RA14
VOLUME AGND 10K
10k RA6 12 25 RA54 120K
REFGND VCLAMPL 120K 10K
LOUTN
LOUTN
PGNDL
PGNDL
LOUTP
LOUTP
PVCCL
PVCCL
PVCCL
PVCCL
RA55 4.7k BSLN
BSRP
CA50
RA7 10k CE3 1 8 CE4 Mode_in 4
1u BYP IN1
0.47u 100u
RA8 2 7 SPDIF/L 3
+
15k GND VO1
13
14
15
16
17
18
19
20
21
22
23
24
+5VE
B +12V_AUDIO +12V_AUDIO B
SPDIF_SW 3 6 CE5 2
SD AVDD
100u
CA41 4 5 1
+
IN2 VO2
CA35 CA36 High is shut down the erphone
0.1u JP2
10n 0.1u CON-4
CA40 UE1 CA27
TPA6110A2 0.1uF
10n
LA3
33uH
CA26 JP8
1
CA43 0.1uF
RA0 JUMP LA4 0.47uF 2 RE7 RE8
CA28 1K 1k
33uH 0.1uF CON2
Title
A A

A4
Drawn By:
1 2 3 4
1 2 3 4 5 6
+2.5V_DDR
C602 C603 C604 C605 C606 C607 C608 C609 C610 C611 C612 C613 C614 C615
C600
47uF/6.3V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D D
GND
L600
5.6uH/5%
FSDATA[0..31]
FSDATA[0..31] +3.3V_SW
FSVREF
+2.5V_DDR FSVREF
C616
C617 47uF/6.3V
1
0.1uF
14
22
59
67
73
79
86
95
15
35
65
96
58
U600
2
8
FB600 GND
GND
FB601
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
FSADDR[0..11] 97 FSDATA0 3.3VSDRAM2 3.3VSDRAM1
2
FSADDR[0..11] FSADDR0
DQ0
31 98 FSDATA1
FSADDR1
A0 DQ1
32 100 FSDATA2
FSADDR2
A1 DQ2
33 1 FSDATA3
15
29
43
35
41
49
55
75
81
A2 DQ3
3
9
FSADDR3 34 3 FSDATA4 U601
FSADDR4
A3 DQ4
47 4 FSDATA5
FSADDR5
A4 DQ5 23SDA[10..0]
48 6 FSDATA6
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FSADDR6 49 A5 DQ6 7 FSDATA7
A6 DQ7
FSADDR7 50
A7
FSADDR8 51 23SDA0 25 2 23SDD0
A8/AP A0 DQ0
A9 A1 DQ1
23SDA[10..0]
A10 A2 DQ2
A11 A3 DQ3
60 FSDATA8
DQ8
61 FSDATA9 23SDA4 61 8 23SDD4
DQ9 A4 DQ4
FSBKSEL0 29 63 FSDATA10 23SDA5 62 10 23SDD5
C FSBKSEL0 BA0 DQ10 A5 DQ5 C
FSBKSEL1 30 64 FSDATA11 23SDA6 63 11 23SDD6
FSBKSEL1 BA1 DQ11 A6 DQ6
68 FSDATA12 23SDA7 64 13 23SDD7
DQ12 A7 DQ7
FSCLK- 54 69 FSDATA13
FSCLK- CLK DQ13
FSCLK+ 55 71 FSDATA14 23SDA8 65 74 23SDD8
FSCLK+ CLK DQ14 A8 DQ8
FSCKE 53 72 FSDATA15 23SDA9 66 76 23SDD9
FSCKE CKE DQ15 A9 DQ9
28 23SDA10 24 77 23SDD10
CS A10 DQ10
/FSRAS 27 79 23SDD11
/FSRAS RAS DQ11
/FSCAS 26 14
/FSCAS CAS NC
/FSWE 25 9 FSDATA16 21 80 23SDD12
/FSWE WE DQ16 NC DQ12
FSDQS 94 10 FSDATA17 30 82 23SDD13
DQS DQ17 NC DQ13
12 FSDATA18 57 83 23SDD14
DQ18 NC DQ14
FSDQM[0..3] FSDQM0 23 13 FSDATA19 69 SDRAM-64MBX32 85 23SDD15
FSDQM[0..3] DM0 DQ19 NC DQ15
FSDQM1 56 17 FSDATA20 70
DM1 DQ20 NC
FSDQM2 24 18 FSDATA21 73 31 23SDD16
FSDQM3
DM2 DQ21 NC DQ16
57 20 FSDATA22
86 PIN TSOP 33 23SDD17
DM3 DQ22 DQ17
21 FSDATA23 34 23SDD18
DQ23 DQ18
36 23SDD19
DQ19
38 23SDDQM 16
NC 23SDDQM DQM0
39 37 23SDD20
NC DQ20
40 71 39 23SDD21
41 NC DQM1 DQ21 40 23SDD22
NC DQ22
GND 42 74 FSDATA24 28 42 23SDD23
FSDQS NC DQ24 DQM2 DQ23
43 75 FSDATA25
NC DQ25
44 77 FSDATA26 59 45 23SDD24
NC DQ26 DQM3 DQ24
87 78 FSDATA27 47 23SDD25
NC DQ27 DQ25
88 80 FSDATA28 48 23SDD26
NC DQ28 DQ26
89 81 FSDATA29 23SDBA0 22 50 23SDD27
NC DQ29 23SDBA0 BA0 DQ27
90 83 FSDATA30
NC DQ30
91 84 FSDATA31 23SDBA1 23 51 23SDD28
DNC DQ31 23SDBA1 BA1 DQ28
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
93 53
MCL
23SDD29
NC DQ29
VSS
VSS
VSS
VSS
54 23SDD30
DQ30
23SDWE# 17 56 23SDD31
23SDWE# WE DQ31
MT46V2M32LG-4 23SDCAS# 18
5
11
19
62
70
76
82
92
99
16
46
66
85
52
TQFP-100 23SDCAS# CAS

23SDRAS# 19
23SDRAS# RAS
GND 23SDCS# 20
23SDCS# CS
B B
23SDCLK 68
23SDCLK CLK
1K R601 67
+3.3V_SW CKE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
+2.5V_DDR
MT48LC2M32B2TG-5
86
72
58
44
6
12
32
38
46
52
78
84
GND
R600 FSVREF 23SDD[31..0]
23SDD[31..0]
10K
FSVREF
R602 3.3VSDRAM1
10K
C618 C619 C620 C621 C622 C623 C624 C625
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
GND
GND
3.3VSDRAM2
C626 C627 C628 C629

FSCLK+
0.1uF 0.1uF 0.1uF 0.1uF
R603
150(140)
FSCLK- GND
A A
3ODFH WKLVSDUDOOHO WHUPLQDWLRQ FORVH WRFRUUHVSRQGLQJ PHPRU\ ,& 3LQV
Title

Orcad C
Drawn By:
1 2 3 4 5 6
1 2 3 4
Component Video Inputs
JPY1 1 Pr Pr
RY3
5 82
D +12V_PORT D
2
1 V1 RA10 VIN
RA51 CA31
100 改为 10
6 Pb RA1 10K 0.1uF
82 RA49
5
YPbPr 3 Y Y AVP1
180 QA8
AV-3-1 2 RA11 LIN
4 2SC2712C
RY1 AV_IN CA1 10K
7 RA2 CA2
82 100P 22K QA6 RA8
AV-1-3PKA 6 L1 VOUT
AV_VOUT 2SC1162Y
RA12 AV_VOUT 82
3 R1 RIN RA48
4 CA3 10K 180 16V470uF
RA3
GND Pb 22K
7 100P
RY2
82
1 VOUT
5
AVP2
JPY3 3
AV-3-1 2
2 RY4
YPbPr Left Audio 22K AV-OU
1 RY5 YPbPr_L 6 LOUT
AV-1
10k 3 ROUT
4
7
+12V_dc +12V_PORT
JPY2 3 RA36
Y1 RA4
YPbPr Right Audio 2 RY6 100 改为 10 YIN
100
22K
1 +
5
RY7 YPbPr_R S-VIDE J3 RA5
AV-1 RA7 CIN CA28 CA29
10k 82 RA37
100uF 0.1uF
4 1 C1 100 改为 10 12k RA38
3 2 RA9 12k
CA41000P
J 82 QA1 QA2
C CA24 C
AVOUTL 2SC2712C 2SC2712C
L1 56UH AVOUTL
+
6
10uF
K CA26 CA27
RA40 ROUT
+
RA6 6.8k
0
10uF RA34 10uF

4.7k
6.8k
+5VB RA39 RA35
GND
20 1k
AUDIO 1k
+5V-T1
19
+5V
CA25
LOUT
18 SubchannelTV
VIDEO AVOUTR 10uF
AVOUTR
+
17
AGC
16
SIF
15
NC
14 RT8 UOC_SW1
SW1 UOC_SW1
100
13 RT7 UOC_SW0
SW0 UOC_SW0
100
12
IF
11 +32V
IF
LT2
UT1
10 22uH +5VB
NC CT7
TM14-C22P2RW
9 0.1u
30V
8
AFT CT12
+ CT11 0.1uF+ CT15
7 CT8 CT1 CT9 470uF 470uF
+5V 0.1u 0.1u 0.1u J1B J1A
6 Y 26 1
NC Pb 27 2
5 RT5 UOCIII_SDA Pr 28 3
SDA
100 LIN 29 4
B 4 RT4 UOCIII_SCL RIN 30 5 B
SCL
100 +5V-T1 YPbPr_L 31 VIN 6
ADD 3 YPbPr_R 32 7
AVOUTL 33 8
2 34 9
NC +12V_dc
AVOUTR 35 AV_VOUT 10
1 36 11
AGC
37 12
+32V 38 13
39 14
40 15
41 K 16
42 CIN 17
43 18
0
+5VB
44 YIN 19
SubchannelTV 45 20
11 Tuner_IF
GND
IF Tuner_IF 46 21
+32V UOC_SW0 47 22
10 RT6
NC NC UOC_SW1 48 23
Tuner_IF 49 UOCIII_SDA 24
9
33V CT3 LT1 AGC 50 UOCIII_SCL 25
0.1u +5V-T2 22uH +5VB 50PIN_12
8
NC 50PIN_12
+5V 7 CT6 CT4 + CT2 CT10 + CT16

470u 470u
0.1u 0.1u 0.1u
UT2 6
+5V
TAD5-E2122W RT2
5 UOCIII_SDA
SDA UOCIII_SDA
100
4 RT1 UOCIII_SCL
SCL UOCIII_SCL
100
3
ADD
2
UT
1 AGC
AGC AGC
CT5
0.1u
A A
Title

B MUX / CONNECTORS
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D D
1.61~2.3v:MENU 0.81~1.6v:VOL-- 0~0.8v: STANDBY++

2.3~3.0:source
2.0V 1.2V 0.3V
2.67V
R1 R2 R4
27K 10K 4.7K
KK1 KK2 KK4 KK6

R6
SOURCE 1K
C MENU VOL--- POWER C
JK1
1
GND 2
GND 3
R3 R5 4
10K 4.7K
VOL++ CN-4
KK3 KK5 KK7

R7
1K
CH--
CH+ NO KEY PRESS 3V~3.3v
2.0V 1.2V 0.3V

1.61~2.6v:VOL+ 0.81~1.6v:CH-- 0~0.8v: CH++
B B
A A
Title

B
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D D
+3.3V_DIG
LK1
22UH
JK2
5
IRDATA 4
UK1 CK2 LED2 3
Vs 1 LED1 2
1
+
CK1 +3.3V_DIG
0.1UF
2 CN-5
GND
16V-47U L1
C GREEN RED C
OUT 3 1 2
HS0038A2M3V
LIGHT
3
B B
A A
Title

B
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L3
3.3uH
R5
C1 C2 82 +5VOUT
D 330pF 330pF D
J1
C7 R6
L1 R2 4
10K K
EARPHONE-R 3
3.3uH 82 R
+
Q1 2
L
EARPHONE-L
16V-10U 2SC2712C 1
C3 C4 G
330pF 330pF R1 +5V
W3F4P-D R11
82
R9 10K
10K
R10
+5V 10K
J4
R8 1
+5V 10k 2
C 3 C
PH-SW 4
R7 Q4
R18
10k 2SC2712C CN-4
1K
SVIDEO-C-IN
R16 R17
1K 1K
13 Q2 Q3
K +5VOUT
11 2SC2712C 2SC2712C
Y
10 J2
S 9 1
8 R13 AUDIO-L-IN 2
C
12 10k 3
16V-10U
C8 Q5 AUDIO-R-IN 4
L2 R4
1 2SC2712C 5
3.3uH 6
+
82
7
5 C5 C6 8
R3 R14
330pF 330pF 9
2 82 10k
B B
R21 CON-9
6 330
+5V
3 R12 AUDIO-L-IN
10K +5V +5VOUT
4
7 R19
22K C9 R22
J3 100pF
AVW133RD-1S 47
C13 + C12
0.1uF 16V100U
R15 AUDIO-R-IN
10K
R20
22K C10
100pF
Title
A A

A4
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JP1
CON-10 +12V_3A
10
For GM1601 Board supply. +5V_4A +5V_4A
9
8 +5V_4A For panel supply. LP3
7 +5V_MCU +5VB 22uH VCC5A
+
6 CP13 CP2 CP15
+5V 470uF 0.1uF
D 5 0.1uF D
4 +
3 CP3 + CP5
RP2 CP4
2 470uF 0.1uF
22k 32V-EN 0.1uF
1 StandBy_power
+24V_4A UP6 CP6

+24V_4A LP1 470uF
LM2596-5.0 33uH
JP9 JP10
+24V_1A 4
14 14 Feedback
+24V_1A 1
13 13 Vin
ON/OFF
JP11 2
12 12 output
8
GND
11 11 CP34
7 0.1uF CP37
10 10 DP1
6 0.1uF
9 9 CP35 1N5824
5 CP36
8 8 0.1uF
4 100uF/35V
3
7 7
3 +12V_3A J171
6 6
2 NC
5 5
1 1
4 4 Backlight_on_off
C Backlight_on_off 2 C
3 3
CON-8 3
2 2
4
CON-14 1 1
5
UP2
Low is Normal on mode. CP1 6
JP12 +24V_4A +5VB CON-14 +5VB IRF7314
High is standby mode. 0.1uF 7
6 1 8
S D 8
5 Standby 2 7
S D
4 RP8 3 6
S D
3 RP6 +5VB 10k DVD_On/Off 4 5
QP2 DVD_On/Off G D
2 nc 2SC1815Y IRDATA/SCL
1 RP10 Backlight_on_off IRDATA/SCL
RP5 CP34A NC State/SDA
CN-6 nc 0.1uF R6 State/SDA
Brightness
UP4 0
RP11 V1_8ANA
0 CP32 UP7 Si2311DS 2
4
3
0.1uF CP26 LM1117-1.8V
RP11 RP10
CHIMEI: 0 NC 0.1uF P_CHANNEL UP1
OUT 4
LG 30: NC OK LM1117-3.3V
GND
4
B B
VIN
LG 26: 2.2k 1k
1
AU 26: 1K 3.3k
OUT 4
V1.8CONTROL
+5VB
GND
V1_8V1
VIN
3
1
RA53 UP3 +12V_AUDIO
+12V_3A 0.27/0.5W IRF7134 LP5
1 8 DP6 CP23 +5VB D3.3V 10uH V3_3A
S1 D1 CP22
2 7 0.1uF
1
G1 D1 SOD4001 47uF
3 6 CP18
S2 D2 CP14
+12Vaudio_ctrl 4 5 0.1uF
G2 D2 GND GND GND GND CP11
CP20 0.1uF
10V100uF
CP24 0.1uF
0.1uF
CP16 CP17
GND
0.1uF 10V100uF
GND
Title
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OCMDATA[0..7]
OCMDATA[0..7]
+3.3V_DIG
D U801 D
37
13
14
29LV800BT
OCMADDR[0..19]
OCMADDR[0..19] +3.3V_DIG
WP#
VCC
VPP
OCMADDR19 16 47
17 A18 BYTE#
OCMADDR18
48 A17 45
OCMADDR17 OCMADDR0
1 A16 A-DQ15 43 C800 C801
OCMADDR16
A15 DQ14
OCMADDR15 2 A14 DQ13 41 47uF/6.3V 0.1uF
OCMADDR14 3 A13 DQ12 39
OCMADDR11 6 A10 DQ9 32 GND
OCMADDR9 8 A8 DQ7 44 OCMDATA7
OCMADDR8 18 42 OCMDATA6
19 A7 DQ6 40
OCMADDR7 OCMDATA5
20 A6 DQ5 38
OCMADDR6 OCMDATA4
21 A5 DQ4 35
OCMADDR5 OCMDATA3
22 A4 DQ3 33
/OCM_WE OCMADDR4 OCMDATA2
/OCM_WE 23 A3 DQ2 31
/OCM_RE OCMADDR3 OCMDATA1
/OCM_RE 24 A2 DQ1 29
/ROM_CS OCMADDR2 OCMDATA0
/ROM_CS 25 A1 DQ0
OCMADDR1
+3.3V_DIG A0
C /OCM_RE 28 OE# A20/NC 10 C
/OCM_WE 11 WE# A19/NC 9
R802
4.7K
/RESET3.3V 12 RST# RY/BY# 15
VSS 27
/ROM_CS 26 CE# VSS 46
8
7
6
5
8
7
6
5
RN800 RN800A R803
10k 10KX4 10K
1
2
3
4
1
2
3
B 4 B
Custom1 10: LOW (Use TCLK)

Custom2 R804 0
R805 0 11: LOW (set all display output to '0')
R806 0 12: LOW
RN801 10K R807 NC 13: LOW(disable serial interface debug)
OCMADDR10 1 8 Serial Interface Debug1 14: LOW
OCMADDR11 2 7 15: LOW
OCMADDR9 3 6 Serial Interface Debug2 16: HIGH (use crystal)
OCMADDR8 4 5 Serial Interface Debug3 17: LOW (8bit bus with OCM access external ROM)
OCMADDR13 1 8 18: HIGH
OCMADDR14 2 7 19: LOW
OCMADDR12 3 6 BOOTSTRAP HEADER
OCMADDR15 4 5 OPEN=1
RN801A 10K SHUNTED=0 GND
OCMADDR16 INT_OSC
OCMADDR18 8-BIT_FLASH2
OCMADDR17 R800 10K 8-bit_flash1
OCMADDR19 R801 10K 8-bit_flash3

A A
Title
GND
GND Size Number Revision
Orcad B
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Models:

Numbe Parts Description

.ICs FUNCTION INTRODUCTION IN DETAILS

Main Tuner (TMI4-C22P2RW)

Sub Tuner (TAD5-C2IP1RW):

Pin Name Description

TDA8759 Internal Diagram：

52,51,50 B/Pb1~ B/Pb3 Blue/blue-chrominance channel analog input

13 BSLN Bootstrap I/O left channel

TPA3002D2 Internal Diagram：

SM5301AS Internal Diagram：

6 VXDD Crystal oscillator power supply

UOCⅢ Internal Diagram：

CHAPTER THREE SIGNAL FLOW ANALYSIS AND KEY POINT

2.Accompanying sound flow:

3.、TV power supply system：

Name Type PIN1(V) PIN2(V) PIN3(V) PIN4(V) PIN5(V)

Main Components and Socket Locations and Definitions:

Number Name Connected Object Function Description

Main Components explanation:

Main Point Wave Picture:

the 10th of SAA7115 also like this:

U201,the 11th pin of U5,the 4th pin of parent/sub RF tuner:

The wave in the 10th of SAA7115 also like this:

2th、6th pin of U6 also like this:

45th pin of U6 and pins:

Symptom One：Display card of PC no image in DVI.

Symptom Three：No picture、no sound ,no snowflake in TV mode, but AV is normal.

Assembly Assembly BBreakable

DVD maintenance parts( only for models with DVD module):

CHAPTER SIX FACTORY MODE AND NOTICE

Adjustment methods for factory menu

3. The illuminate of white balance and AutoColor adjustment method

③ White balance, color temperature adjustment

FSDQM[0..3] Ls08-AD convert-01 LS08-Gm1601-03 ls08-Graphics_Components In-04

Size Number Revision

CON-9 RA16 RA17 To UOCIII&Tuner Board. RA37

CA7 CA9 2348 UOC_SW2 UOC_SW2

47K 0.1uF 10V220uF 0.1uF UOCIII_SDA Tuner_IF

Size Number Revision

180 1uH R271

3.3K MM_SDA RT5 100 3 2

22uF/6.3V 5K +5V_MUX +5V_ANG 100K

24LC21 C326 GREEN-

GND ADDA R382 R390 22K

GND R4 F24 FSDATAU29

VSSA33_DDDS GND SOIC8 (150mil BODY) GND

GND +3.3V_LVDSB GND

C792 C793 C794

37 38 B/Cb/D1_0 VDD8(3.3) RN405

Vcore DGND ADVR00 21 136

NOTE: FLI2300 could be used in place of FLI2310

R425 100R/5% SCL_V

U402 C480 5.6uH/5%

SubchannelTV AI24 IPD7 GND

C466 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

ALRCLK is used to seleted to 24.576MHZ crystal.

56R GND 22P C4124

A 'Strapping' I2C Slave TO-252 TO-252 A

Size Number Revision

D504 2 C511 C515

Leave 1sq inch- exposed copper area attached to Tab of U903

+3.3V_ADC +3.3V_LVDSA +1.8V +1.8V_ADC +3.3V_ADC +3.3V_LVDSB+3.3V_ADC +3.3V_LVDS +3.3V_ADC +3.3V_DIG