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Malfunction with the KA-3300D digital circuitry, such as the absence of output, could be due to the digital signal input source. Be sure to check and repair the source equipment as well as the ka-3300D. Refer to Parts List on page 55.
Malfunction with the KA-3300D digital circuitry, such as the absence of output, could be due to the digital signal input source. Be sure to check and repair the source equipment as well as the ka-3300D. Refer to Parts List on page 55.
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Malfunction with the KA-3300D digital circuitry, such as the absence of output, could be due to the digital signal input source. Be sure to check and repair the source equipment as well as the ka-3300D. Refer to Parts List on page 55.
Drepturi de autor:
Attribution Non-Commercial (BY-NC)
Formate disponibile
Descărcați ca PDF, TXT sau citiți online pe Scribd
Malfunction with the KA-3300D digital circuitry, such as the absence of output, could be due to the digital signal input source such as the CD player as well as the KA-3300D.
Therefore, when servicing such trouble, be sure to check and repair the source equipment as well as the KA-3300D.
1. Remove the six screws fixing the metallic cabinet to the chassis (left side: 3, right side: 3) (0).
2. Remove the two screws attached to the metallic cabinet (8)·
3. Remove the metallic cabinet by lifting it in the direction of the arrow (8).
4. Remove the seven screws attached to the front panel
(0)·
5. Remove the seven knobs from the front panel. Also remove the seven nuts taking care not to damage the front panel (0).
6. Loosen the four screws insert into the two couplings (No.19 in the enlarged diagram) (0).
2
7. Remove the front panel in the direction of the arrow (0).
8. When attaching the front panel again, align the grooves the front panel with those of the extension shaft. If this has not been done, the panel cannot be attached correctly ($).
9. Remove the screw from the metal part in the power switch section (0).
10. When attaching the power switch section again, insert the guide pins of the metal part (two on each part) into the slots on the frame (front) ( 4D ).
11. Remove the four screws attaching the connector cover
(.).
12. Remove the connector cover in the direction of the arrow
( f)).
DISASSEMBLY FOR REPAIR
13. Remove the two screws from the Control Unit (Xll-2350-81) (Am (fi).
14. Remove the parallel cable which has been connected to CN7 of the Control Unit (X 11- ) (An) in the direction of the arrow (~).
15. Remove the parallel cables which have been connected to CN3 and CN4 of the Control Unit rx n- ) (Am (e).
16. Crush the heads of two unit holders which attach the Control Unit (Xll-) (A/7) to the frame (front) using radio pliers, and pull them out from the Control Unit (4D).
17. Remove the Control Unit (Xll-) (An) in the direction of the arrow (tI).
7. Insert the AUX connector section into the slot on the bottom panel (0).
8. Insert the PHONES jack section into the slot on the bottom panel ($).
9. Remove the bottom panel from the main chassis in the direction of the arrow (0).
t . «s:
~
(9
CN3.4
2. REMOVING THE BOTTOM PANEL
3. REMOVING THE SIGNAL PROCESSOR UNITS AND REAR PANEL
Refnove the four screws from the connector cover (0).
2. Remove the connector cover in the direction of the arrow (8).
3. Loosen the six screws on the bottom panel (8).
4. Remove the two screws from the rear side of the bottom panel (0).
5. Remove the two screws from the AUX connector section
(0).
6. Remove the two screws from the PHONES jack section (0).
1. Remove the metallic cabinet and bottom panel before performing the following operations.
2. Disconnect the four connectors which have been connected to the frame (rear and front) (0).
3. Remove the 13 screws retaining the shield cover (8).
4. Remove the shield cover in the direction of the arrow
(8)·
DISASSEMBL V FOR REPAIR
5. Remove the screw retaining the thermal switch, then
remove the thermal switch and its metal fixture (8).
6. Lift the shield case upward (0).
7. Separate the connector cord from two unit holders attached to the shield case (3).
8. Disconnect the parallel cable from CN 1 of the Signal ProcessorUnit(X32-1112-71) (C/6) (0).
9. Lift the two Signal Processor Units (X32- ) (A/6, B/6) in the tj;hield case upward.
o
10. Pull outthe coupling from the remote switch shaft (0).
11. Remove the eight screws (four from the upper side, four from the bottom side) from the frame (rear) ( dO ).
12. Remove . .the.fourscrews from the bottom side of the frame (rear) ( 4D ).
13. Remove the 14 screws from the rear panel ( f&).
14. Disengage the claw fixing the rear panel to the chassis (.~).
15. Remove the rear panel in the direction of the arrow by sliding the left-hand side upward ( tJ) ).
4
BLOCK & LEVEL DIAGRAM
16. When attaching the rear panel,follow the procedure and cautions below.
17. Engage the claw of the rear panel onto the notch on the chassis ( 41 ).
18. Insert the claw of the frame (left) correctly into the slot on the right side of the rear panel. At this time, the upper surface of the frame (rear) shall come above the rear panel ( ~ ).
19. Insert the claw of the chassis into the slot on the frame (rear) ( 4D ).
20. Pile the Main Amplifier unit reinforcement metal (No.736 in the enlarged diagram), frame (rear), Main Amplifier Unit (X07-2320-82) and chassis in this order, and fix them together using a screw ( CD ).
21. Attach the rear panel as shown in the diagram ( 41> ).
i!
« o
I o
-, I I I I I
'" ...
::> n. z
>«
o ..J
w n.
L!;i...J
a
~';
'--- 0 ~ __j
o~
w z a J: a,
....
I J:J
.ow<l , Z 0: '" _ .... V) ..J V)
,
L _
o ....
o z o I o,
a o
a z o
'" x
::> «
o >w «
0: ..J
L~j ~
0:
W Z ::> ....
o >w «
0: '" ..J
Lwn.
~_j
....
o >w «
0: '" ..J
Lw o,
n....J «
....
x ::> «
o
:3
L_ ~
«
5
CIRCUIT DESCRIPTION
DESCRIPTION OF COMPONENTS
Main Amplifier Unit (X07-2320-S21
Transistors forming the VIG circuit. 09, 10, 13 and 14 form the constantvoltage circuit, 011, 12,15 and 16 the buffer, and 017 to 20 are grounded-base circuit for cascode grounding.
1 st-stage differen-
051-54
Constant-voltage circuit
051 and 52
055, 56
Protection driver
I circuit inserted in the
amp.
057
Constant-voltage circuit
Used to transmit the operation signal of current limiter 033 and 034 to the protection IC (IC3)'
058
Constant-voltage circuit
Constant-voltage regulated circuit for the muting relay and tact SW driver circuitry.
Constant-voltage regulated circuit for the equalizer amp. 059 and 60 are control transistors, and 061 and 62 form an error amplifier.
059-62
Constant-voltage circuit
Protection IC
Performs muting when power is turned ON/OFF, and output relay control n.case .. of DCleakage to SPpin overload,.etc.
IC3
Preamplifier Unit (XOS-21S0-S21
Component Use/Function Operation/Condition/Compatibility
01-4 EO MC 1 st-stage differential amp
05-8 EO 1 st-stage cascode circuit
09,10,.23,24 EO constant-voltage circuit Provided to improve the SVRR and CMRR of 1st-stage differential amp.
011-14 EO MC output-stage emitter-follower cir-
cuit
015-18 EO MM 1 st-stage differential amp
019-22 EO MM output-stage emitter-follower
circuit
025, 26 A Class 1 st-stage differential amp
027-30 A Class 1 st-stage cascode circuit
031-34 A Class 2nd-stage differential amp
035-38 A Class 3rd-stage differential amp
039-42 A Class cascode circuit
043, 44 A Class current Miller circuit
045-49 Muting control and driver circuit Control and drive of the muting lamp and relays.
IC1,2 EO op amp IC
IC3 Muting circuit IC J-K flip-flop. 6
CIRCUIT DESCRIPTION
Signal Processor Unit (X32-1112-71 I
Use/Function
Operation/Condition/Compatibility
Component
CIRCUIT DESCRIPTION
Component Use/Function Operation/Condition/Compatibility
026 Constant-voltage regulated power supply (FAST OFF).
027-35 For current 0,hapiflg:
037-43 For protection against static electricity.
A1 Optical reception module Converts optical signal into electric signal. Control. Unit (X 11-2350-81 ) \~.
Component Use/Function Operation/Condition/Compatibility
01 LED drive switching circuit
The LED lights continuously while the power indicator and set are
02, 3 Blinking circuit operating normally. It blinks during the period between power ON and
amplifier stabilization (for approx. 5 sec.) or when the protection circuit is
activated due to a malfunction in the power amplifier.
04 Constant-voltage circuit for lamp Controls the voltage applied to the lamp to 27 V.
IC1 Tone control circuit Ie 8
CIRCUIT DESCRIPTION
1. NEW VIG OLD CIRCUIT
1-1. Features
The KA-3300D is not only an upgraded unit of KA-ll 000, but a variable superb integrated amplifier incorporated with digital technology.
KA-3300D incorporates new technology appropriate for an up-market integrated amplifier, such as:
1. A new VIG OLD (Dynamic Linear Drive) circuit
2. A dual phono equalizer
3. A dual REC OUT switch
1-2. A New VIG OLD Circuit
Refer to the KA-990V new-product data for an explanation of the principle on which VIG operates.
The configuration of the VIG circuit incorporated in the current KA-990V is depicted in Fig. 1.
In addition to preventing the influx of ,\?!.nde~rable power source components (such as ripples) into the .. 01 driver transistor, the VIG circuit also applies a bootstrap to the output as shown in Fig. 1 ® . The output from the VIG then follows the output'frorn the amplifier in a constant voltage shift pattern. The input signal is no longer absorbed by the power source {j,ccorQ.jng to the potential which exists between the input and the power, and high-frequency characteristics and distortion 'fates ate improved.
Power source
02 final transistor
Fig. 1 Configuration of a Conventional VIG Circuit
As a result, the voltage across the output of 01 (the emitter) and the power source (the collector) is held constant whether or not there is a signal (see Fig. 2).
This insertion of a VIG circuit in the initial stage of a Darlington connection circuit means that undesirable power source components do not undergo current amplification at 02, the final transistor. In other words, large-capacity power sources free of ripples become the norm.
Power source
/~-'rVIG output
/ \ Amplifier
I output
/
Ripple-free power at constant voltage
Fig. 2 VIG Output and Amplifier Output
Constant
____ / VIG output »: ...- -- <,
/ I -, <,
\ "
Voltage shifts according to 01
/
I
02 base emitter
Intervallic voltage (shifts)
Fig. 3 VB-E and VIG Output
CIRCUIT DESCRIPTION
Upon further investigation, however, doubts arose. concerning operation of the 02 driver transistor at the abovementioned constant voltage. That is, the voltage across the transistor base and emitter could be thought of as normally about 0.6 volts, but the final transistor voltage shifted between 0.6 to about 2.0 volts in keeping with the output current (see Fig. 3). In the conventional configuration depicted in Fig. 1, this shift caused the voltage applied to the driver transistor 01 to shift as~vyell. It became clear that with the conventional configuration undesirable power source components were suppressed, but this in turn produced new voltage shift components.
The new VIG circuit applies a bootstrap to the 02 final transistor base as shown in Fig. 4. In addition, a buffer has been inserted so that any undesirable power source components which may leak through the bootstrap do not undergo current amplification at 02.
Fig .. 4 Configuration of the New VIG Circuit
With this configuration, the new VIG circuit permits capacities to be utilized to the fullest extent.
Undesirable power source components can be suppressed, as can the shift component produced by operation of the circuit itself, for effectiveness 25 times greater than that of conventional circuit configurations. This permits 01 to operate at an ideal constant voltage and allows only very pure signals to be input to the final transistor, making possible "cleaner" overall amplification.
1-3. Effects of the New VIG Circuit
1. Effects on the amplifier of ripples and signal components caused by the power source, as well as the cross modulation distortion to which they give rise, are drastically reduced for clear, sharp audio.
2. Power can be boosted accordingly (over 10 times conventional levels) for brilliant audio.
3. Improves raw effects at the pre-negative feedback voltage amplification stage for broad band. low-distortion sound.
4. Reduces dynamic crosstalk and other power sourceinduced interference.
10
1-4. Dual REC OUT
REC 1, 2, 3 output the signals indicated in the chart at right. REC 1 f~D.ctions as the source selector, while REC functions as the'REC selector.
During tape dubbing, the source signal is output at the playback TAPE REC-OUT.
POSITION RECl REC2 REC3
OFF OFF OFF OFF
DIGITAL -2,3 SOURCE DIGITAL DIGITAL
CD -2,3 SOURCE CD CD
TUNER -2,3 SOURCE TUNER TUNER
TAPE 1 -2,3 SOURCE PLAY 1 PLAY 1
TAPE 2 -1,3 PLAY2 SOURCE PLAY 2 Note: Signal selected by the SOURCE INPUT SEL.
DIGITAL
CIRCUIT DESCRIPTION
2. DIGITAL AUDIO INTERFACE
MONITOR sw
MAIN
This is a self-synchronization, serial interface designed for connection of digital signals between digital audio equipment (CD player, OAT, etc.l.
Block diagram
Optical receiving module
4fs (Ouadrupie) oversampling digital filter
LOUD NESS
rI I I I I I I I I I I I I I I
L 1
-------------,
I I I I I I rn=H====~h---@ REC 2 I
I I I
INPUT 2
13
DIGITAL j TAPE2, 3 r
OFF \ I ,00
Q (INPUT SEL. SOUROE~TAPEI
.. TUNER ~ TAPE I)
-TAPEI~2 3J
' DUBBING
.. TAPE2-*1 3 --------+SOUROE-~TAPE2
25615
38415
I REC 0 OAT
. L PLAY
3. DIGITAL SIGNAL FORMATS
The sub-frame is the minimum unit of transmitted
bits of data obtained one
3-1.
3-2.
A sub-frame consists of the SYNC part which is a called preamble, the audio data part, and the control part which includes emphasis data, etc. (Fig. 2)
. audio-signal sampling operation. With the CD format ,the sampling frequency of which is 44.1 kHz, ~44, 1 00 data per second are sampled with each of
the Land R channels, so that a total of 88,200 data are obtained every second. Each of data obtained in this way corresponds to one sub-frame. (Fig. 1)
3-3.
The data is transferred after biphase-mark modulation. With this modulation, bits "1" are inverted twice while bits "0" are inverted once. (Fig. 3)
Time (t) ->
I: Frame
Sub· frame "'
Fig. 3
---=fLJ1_J
Fig. 1
R
R
L
L
L
R
L
Fig. 2
SYNC AUDIO DATA
preamble
biphase-rnark
11
CIRCUIT DESCRIPTION
CIRCUIT DESCRIPTION
4. THREE SAMPLING FREQUENCIES AND
TRANSMITTED SIGNAL
The digital signal is output at 0.5 Vp-p. The Land R signals are time-division multiplexed so that stereo digital audio data is transmitted via one single cable (optical cable or 75-ohm coaxial cable).
The information required for sound reproduction by the receiving equipment (bit, clock and emphasis data) is also transferlfied together with the audio data.
Sampling Transmission Frequency Source Equipment of fs
Frequency (fs) 32 x fs with "0" 2 x 32 xfs with "1"
32 kHz 1.024 MHz 2.048 MHz DBS, OAT (option)
44.1 kHz 1.4112 MHz 2.8224 MHz CD, OAT (PCM processor signal)
48 kHz 1.536 MHz 3.072 MHz OAT (record/play type). DBS 5. INPUT SWITCHING CIRCUIT
Three input systems are switched by purely electronic method.
The X32 (0/6) input switching circuit hasthe basic configuration as shown below. The contents of its operation is shown in the timing chart below.
INPUT@
/15 "l
INPUT I INPUT 2
DAT- ON , OAT-OFF
6. DIGITAL 110 CIRCUIT
The signal is input to received data demodulation IC pin 15. At this stage, the signal contains the clock required for data reproduction in addition to the digital audio data. The clock must first be reproduced because it is used as the basis for demodulating the biphase-modulated signal into ordinary digital data and for converting it into analog signal using the OIA converter. All processing after this stage until the OIA conversion is performed based on the clock.
12
I
I
I
I
I
1!"F-""--~~-11
The sigQ.aLis transmitted at 32 times the sampling frequency, and"6its "1" are transmitted at twice the abovementioned transmission frequency. To enable direct connection of the digital signals from the equipment described in 1 (CO player, OAT, 8S), the three types of sampling frequencies are prepared defined by the standard.
X32 (D/6)
Pin No. of Pin No. of
INPUT 1/2 DAT ON/OFF
®
~
0 55
o
Lr1_f- fS
0 IC23(3) IC23@ U
Z
0
® IC24(2) IC22@ i=
<t ....I
----wuu U ....I
@ IC23@ IC22@ u:: e,
i= z
I Z 0
CD ILfTlJlJ1l1J IC23@ IC22(3) w i=
c <t
I ....I
INPUT I I INPUT 2 (i) ::;)
OAT ON I OAT OFF ~ C
I > 0 u;1
u ::2E
z w <,
w c ~I
::;) ~
0 o ~I
w 0 0
Ilrd'if a:: ....I ~I
LL. o
" c §L ____
z w
::i >
ll.. iii
::2E u
<t w
en a: ~I
<I:
~I
~I 71
N r<')
x
13
CIRCUIT DESCRIPTION
6-1. Operation of sampling frequency (fs) identification circuit
1 I
1
___)
1 U
1
1 I
1 I
1
1 ,
1
1
2.65 msec 103801 103802
1038 03 103804
1036 CD 1035 1040
1033 (j) 1036@
036@
01 and 02 in the circuit diagram are used to switch the window for detection of the SYNC signal. The state at IC33 pins 6
The signal output at IC36 pin 1 depends on the fs as well as on the time constant across IC35 pins 15 and 14. If the pulse duration is set to 2.65 the "L". This is
and 7 varies in three modes
on the output of each
CIRCUIT DESCRIPTION
Assuming that the PLL is locked in mode (IT) with fs = 44.1 kHz, IC33 pin 7 is "L" in this mode and IC40 pin 2 goes from "H" to "L" in a certain period of time (approx. 1.35 rns).
At this time, IC36 pin 10 outputs "H" for an instant, and the 3-mode switoh of IC33 changes the mode to "HH". The PLL is unlocked at this time as shown in the top of the timing chart. However, the OISCHG signal is input from IC42 to IC33, the mode is changed, and the PLL is locked finally in mode (III).
If the PLL is locked in mode (III) with fs = 44.1 kHz, IC33 pin 7 is "H", and IC36 pin 10 does not generate pulse even when IC40 pin 2 goes """"t_" , so the PLL lock state is maintained.
The "JL." pulse extracted from IC36 pin 1 is used to ensure stable locking even when fs drops around 40 kHz due to the variable-pitch circuit. Under such condition, the """"t_" (negative-going) edge of the above-mentioned ;;,65 ms pulse is generated on the above-mentioned pulse. Eeen when the mode is (II) at this time, IC36 pin 10 does not output pulse so the lockinq is stabilized in mode (IT).
In short, the additional circuit which incorporates a counter, etc. functions so that the PLL is locked in the following condition: ".j
IC33
pin 6 pin 7
fs=32 kHz: Mode (l) (H H)
fs=44.1 kHz: Mode (III) (L H)
fs=40 kHz: Mode (II) (H U(Variable-pitch)
or (III) (L H) In the actual circuit, 012 is eliminated, and shownenclosed in broken lines (---) in the circuit diagram, is not operating. Then the models with Serial No. 73KOOOOO and after, the parts boxed with" ---" are eliminated. Therefore, the PLL of the IC33 in modes (6) and (7) locks with (I) and (III).
(1)
(III)
Mode
--------------l_ 1033@
1033(j) -----, .-
L -'
fs=32kHz
44.1 kHz or 48kHz
chart, with IC36 pin 1 output during transition of IC35 pin 13 output from "H" to "L". This diagram shows the case in which fs = 44.1 kHz, but the output is also "L", with the "~" point at the position of 0' when fs = 32 kHz and at the position of "0" when fs = 48 kHz.
Mode
(II) (III)
(I)
1033@
IC33(j)~
Is 32kHz
--- 44. 1 kHz, 48kHz
Mode variation
When fs = 32 kHz is input, the PLL is locked in mode (l). It is locked in mode (III) when fs = 48 kHz.
The mode of IC33 varies via 036 and 012. However, when fs = 32 kHz or 48 kHz, the mode will not be varied by the signal passing through 012. This is because, when fs=32 kHz or 48 khz, the PLL is locked first only in mode (l) or (III). Next, when fs = 44. 1 kHz is input, the locked mode can either be mode (IT) or (III) because it is close to fs = 48 kHz. When the PLL is locked in mode (III), the inputs to IC39 pin 12 and IC36 pin 5 go "L" and the output at IC36 pin 1 is output directly at IC36 pin 13. When it is locked in mode (II), the output at IC36 pin 1 is inverted and output at IC36 pin 13.
Is=32kHz Is=44.1kHz
1 1
: n::
IC36CD -----L-T-I -...... '-+I--+-I L-----
IlL I
1 1 1
1040(2) ------1-1 ---- __ 1'--+1---"
1 I L.._
I I
1 1 1
I ----J_I,::=48kHZ
1035@------iC--C-l ... _
1 I I
0' 0 0"
14
6-2. Ihe ol!.Jput from VCO IC28 pin 6 becomes 384-fs, a part of the sig~al is divided into 1/192 by IC31 and IC30 to generate a Signal which is input to phase-comparator IC27 pin 3. The 2 f of the input signal is also input to IC27 via pin 1, and the PLL is locked when the signals at pins 1 and 3 become identical.
At this PLL, two types of clocks are generated simultaneously; the 384-fs clock required for the processing from the VCO to digital filter; and the 256-fs clock required for data demodulation which is obtained by dividing the 384-fs clock into 2/3.
Sampling frequency 256fs 384fs Major source unit
32 kHz 8.192 MHz 12.288 MHz DBS
44.1 kHz 11.2896 MHz 16.9344 MHz CD
48 kHz 12.288 MHz 18.432 MHz OAT, DBS 15
digital audio data that can be D/A modulated and, at the same time, extracts the information from the subcode, such as the emphasis data.
CIRCUIT DESCRIPTION
6-3. Received data demodulator IC42
Using the reproduced 256-fs clock, demodulator IC42 demodulates the biphase-modulated audio data to obtain the
IC42: CXD1076P Received Data Demodulator
Pin Configuration
COpy CBIT VBIT
100 101 EMPH UBIT
2
XRCH TEST TXCP
CS SLAV RX
(TOP VIEW)
BCK LRCK OISCHG Vss RXCP
DATA WCK VAR REF APTL
Block Diagram
UN-LOCK
BLK-IO oLSBF
Biphase demodulator
Timing generator
LSBF
DATA
16
CIRCUIT DESCRIPTION
Explanation of Pins
3
LRCK
Outputs the audio data LlR channel-identification pulse. The polarity can be switched by XRCH pin. The R CH is "High" when XRCH = "L".
o
4
o
WCK
Outputs a pulse having twice the frequency of LRCK. The pulse indicate the end of each word. Each word lasts until the fall of this pulse.
When the external PLL for clock extraction is unlocked, this pin outputs the Low-Active pulse which is used as the trigger for locking it.
DISCHG
5
o
17
CIRCUIT DESCRIPTION
• Timing chart
(XRCH: "L") BLK-IO
LRCK
R ch of previous block \
APTL
Timing chart
L ch of the start of block
The timing chart above shows the relations between BLK-ID, LRCK, APTL and APTR.
BLK-ID: "H" indicates the beginning of a block. However, since the DATA output is still the RCH data of the end of the
• Channel status data
BLK-IO
previous block, LRCKgoes "High". (XRCH: "L")
The firstdataof.the block will be output next time LRCK goes "Low". APTLandAPTR are output at the timing above from the respective channel.
WCK
LRCK J (XRCH- Low)
J J
=J ____:._
I
100
~
I I I I
I I I
I I
I I
~- __ ---+-
10 I
j.___-----:-
COpy
EMPH
Among the channel-status data, 100, 101, COPY-Inhibit information and Emphasis information are output from the 100, 101, COpy and EMPH pins at the timing shown above.
18
I
~
CIRCUIT DESCRIPTION
• User definable data, validity flag
,\----- Word 1 -------001--- Word 2 -- - --
RX
WCK
---; J-- 2 clocks with RXCP
-------------------------------__,I :
I
VBIT
I
---------~Ir_------------------------
__________ -JX~w~0~m_1~V_-_bi_t_da_t_a __
UBIT
_________ ~X~w __ o_m_1_U_-_bi_t_da_t_a __
CBIT
X Word 1 C-bit data
---------'
The digital 1/0 data, user-definable data and validity flag that are input to the RX pin in the digital interface format are out-
'"-:1
put with a slight delay after the fall of WCK. The C-bit data is similarly output at the CBIT pin.
The signal timings are designed in consideration of facilitating connection to the D/A converter (CX20017, etc.). LRCK, DATA, BCK and WCK signals are output with the timing shown in the diagram above. The digital audio data (DATA output) is shifted by the negative edge of BCK before being output. The data output is MSB-first when the LSBF pin is "Low", and LSB-first when it is "High". The polarity of LRCK
can be switched by the input at the XRCH pin. When XRCH is "Low", "Low" of LRCK indicates the L CH and the L CH data is output. Therefore, direct connection to CX20017 is possible by setting XRCH to "High".
For this operation, it is necessary to input a clock with a frequency below 500 Hz to the CS pin in order to generate
---
DISCHG output required for the external PLL.
19
20
CIRCUIT DESCRIPTION
Word 1
RX
U1.JWL....R.f
r---+---=--=~--=-=--::--;-,------iv U C p!------l
Preamble (M)
Audio data
RXCP TXCP
Preamble (B)
JIIIUlIL
JlI1IlJU1IIIIII ..JLJL../LJL.JL
REF
VAR
III I
WCK
LRCK (XR\"l- Low) APTL
APTR
BCK
BLK-ID
DATA
VBIT
J, Word 1 V-bit JlJiord 1 V-bit ]. Word 1 C-bit
~V ~V. ~C
UBIT
CBIT
6-4. IC41 :SM5804B
Block Diagram
r---
I
I I
-jl
~~~~~~~~~~ __ ~~ I I I I I I
CIRCUIT DESCRIPTION
IV:
I~
I~
I~ I~
I~
" v
tn
o '"
Input interface circuit
Coefficient ROM
16
'" o
v
!£ x
I
x
o o >
XT
Shift resistor (I)
XT
CKO@ E (A) (B)
1:
CKSL 0
0
Cl 16
C
'{:? 4SSL 'E
i= TEST 1
VSS
J J
0-
J
I I
.... _--
36
I I
___ ..J
o " v
(Il
21
Shift resistor (II)
Output latch/output timing circuit (16 bits)
I~ I~ I~ I~
o v
!\I o u
'" o
u
" " o
CD o o
Note: In the above diagram, the pin used for two functions are treated as two separate terminals.
CIRCUIT DESCRIPTION
CIRCUIT DESCRIPTION
Explanation of Pins PISL=H PISL=L
With this LSI, the switching between the serial and parallel in- of the functions of pins X1 to X16 and Y1 to Y16 may be r Pin No. Function
Pin Name 110 Pin Name I/O
puts/outputs is performed by the PISL and POSL pins. Some changecj)2Y this switching. SODB 0 B CH serial data output.
~y,., ""
/i 28
-_ ') Y2 0 Parallel output (inverted, Bit 2),
All the terminals of this unit function with PISL = H. Note: ip designates an input jack with a pull-up resistor. i[\
29 (NC) .> -> Internally short-circuited to VOO. Not to be connected externally.
Pin No. " PISL=H PISL=L ;i BCKO 0 Serial output bit clock output.
Function 30
Pin Name 110 Pin Name I/O .. Y3 0 Parallel output (inverted, Bit 3).
1~;;'" SIMD ip Serial input mode switching. COl 0 Serial output control clock 1.
31
X5 ip Parallel data input (Bit 5). 1 ••••• Y4 0 Parallel output (inverted, Bit 4).
2 SIEB ip B CH serial input enable. ! i CO2 0 Serial output control clock 2.
X4 ip Parallel data input (Bit 4). < 32
~ Y5 0 Parallel output (inverted, Bit 5).
3 SIEA ip A CH serial input enable. C03 0 Serial output control clock 3.
. i
X3 ip Parallel datainput (Bit 3), 33
Y6 0 Parallel output (inverted, Bit 6),
BCKI ip Serial input bit clock input. 'ye
4 Serial output control clock 4.
C04 0 /!c.
X2 ip Parallel data input(8it 2). 34
i Y7 0 Parallel output (inverted, Bit 7).
5 SID ip Serial input data.
(NC) Hz (NC)
Xl ip Parallel data input (LSB). 35
.'
Y8 0 Parallel output (inverted, Bit 8).
6 44CI ip ip 44.1 kHz sync clock input.
ABSL= H-44 CI clock, H/L = A CH/B CH. (NC) Hz (NC)
7 ABSL ip ip 36
ABSL= L-44 CI clock, H/L = B CH/A CH. 1:!: . .,.. Y9 0 Parallel output (inverted, Bit 9).
8 TEST 1 ip ip Test input 1 (Normally Open). (NC) Hz (NC)
" .' 37'
9 TEST 2 ip ip Test input 2 (Normally Open). Yl0 0 Parallel output (inverted, Bit 10).
10 4SSL ip ip Normally 4SSL= H or Open. 4SSL= L when input is 16.9344 (NC) Hz (NC)
MHz or 17.2872 MHz. 38
CKSL= Yll 0 Parallel output (inverted, Bit 11).
IA
'---~~ ,,_- ---"TT- ~-"--'--"-- -TKSr rp rp ,to
CKSL= L--+X'tal oscillation. (NC) Hz (NC)
39
12 Vss -> / GND power supply pin (0 V). I~ ft Y12 0 Parallel output (inverted, Bit 12).
~
CKSL = H - Clock input. (NC) Hz (NC)
13 XT I ... I CKSL= L-X'tal oscillation input. 40
Y13 0 Parallel output (inverted, Bit 13).
Y14 0 Parallel output (inverted, Bit 14).
15 CKO 0 ... 0 Clock output.
System clock 96 fs- SCSL = H. (NC) Hz (NC)
42
16 SCSL ip .. ip System clock 98 fs-SCSL=L. Y15 0 Parallel output (inverted, Bit 15),
17 2FS ip ip Open. .~ (NC) Hz (NC)
43
18 POMD ip .. ip POMD = H - Normal parallel output mode. Y16 0 Parallel output (inverted, MSB)'
POMD = L-In-phase parallel output mode" .~ POSL= H-Serial output system.
POSL ip ip
19 SOMD ip ip SOMD = L with serial output. 44 POSL= L-Parallel output system.
20 LSBO ip ... ip LSBO = H - MSB-first serial output. "1C5ti3= H-2's complement display output.
LSBO=L-LSB-first serial output. 45 YOFB ip ip YOFB = L - Offset binary display output.
21 (NC) / ... -> (NC) L_ -> +ve power supply pin (5 V).
46 Voo
/ /
22 (NC) .. (NC) XOFB= H-2's complement display input.
/ / (NC) 47 XOFB ip ip XOFB = L - Offset binary display input.
23 (NC) ...
24 (NC) .> .. / (NC) .f PiSI= H-Serial input system.
~ 48 PISL ip ip PISL = L - Parallel input system.
25 DGA 0 .. 0 A CH deglitch control output. .>
49 (NC) / (NC)
26 DGB 0 ... 0 B CH deglitch control output.
27 SODA 0 A CH serial data output.
Yl 0 Parallel output (inverted, LSBl. I 22
Serial Output Timing (SOMD = L, SCSL = H, system clock = 4.2336 MHz)
24
( I 76.4kHz)
CIRCUIT DESCRIPTION
6-5. D/A converter IC IC1, IC2: PCM56P-K
1. Block Diagram and Pin Connection
-Vee ]1 tVee
~ ~
eo .I: ...
DIG. GND c. ~ :J
0 S
... :J
:§c: '" 0
:1::
~ 0 .0 "'0
<Il,_ ~i
so ~ <0
:B~ ~> ADJ
:Jc
Uo
<00 .1: 0
~U .o<t:
N/C <0-
~a
I CK
"0
c_
eo 0
LEC ~:.
LSI ,_ c
.I: 0
'" o
Qiu
DATA ~~
-VL
ANALOG OUT
* r:!:3.0V) Note: The MSB error and differential linearity error with bipolar zero can be zeroadjusted by the external circuit shown below.
Pin No. Pin name Function Pin No. Pin Name Function
1 -Vcc Analog negative power supply 9 VOUT Voltage output
2 DIG GND Digital grounding 10 RF Feedback resistance
3 +VL Logic positive power supply 11 S,J Summing junction (op amp input)
4 NC No connection 12 ANA GND Analog grounding
5 CK Clock input 13 lOUT Current output
6 LEC Latch enable control input 14 MSB ADJ MSB adjustment pin
7 DATA Data input 15 VPOT Potentiometer pin
8 -VL Logic negative power supply 16 +Vcc Analog positive power supply 25
CIRCUIT DESCRIPTION
Timing Diagram
DATA INPUT
DATA CLOCK
~(,
LATCH ENABLE CONTROL
L
• The data format is 2's complement, MSB-first.
• Data is latched in the shift register at the rise of data clock.
• Latch enable control is performed by the frequency twice the LlR clock, and theLSB corresponds to its rise.
It shall be synchronized with the fall of data clock.
7. WAVEFORMS AT MAJOR DIGITAL CIRCUIT PINS (When CD digital signal is connected)
Pin
signal "0" (32 fl
IC25@ (TC74HC386P)
The actual waveform is superimposed with the waveform of "1".
IC25@
Input signal "0" (64 f)
l 73nS j- z8ons___' 73n5 t-ZBOnS------i
The actual waveform is superimposed with the waveform of "1".
IC27CD IC27@ (MC4044P)
T~\ n·
1---------1 I. 3p s---------!
When a CD player is not connected, the output is present at IC27 pin 3 only (in free-run condition, however).
IC28@ (SN74LS624N)
DC 2.0V
3* IC28@
• Shall be no jitter.
26
: Defective.
3*
IC32@ (TC74HC86P)
Pin
CIRCUIT DESCRIPTION
: Defective.
are present even
i--35.,S----j
T
5.0V
1
1.41MHz
-+-+--95,S---I
25n5
• Shall be no jitter.
IC42@ (CXDl076P)
i------- 706'5----i
T
44. 1kHz
4fs
IC42CD
IC41@ (SM5804B) (W8 @CV)
IC41@ C\V8@)
IC41@ (W8 @)
1.41MHz
32fs
32fs
16fs
fs
The output is present only during CD player playing.
96fs
"* Note: Even when the input cable is apart from the CD player' s DIGITAL OUT, the output from IC2a pin a and IC32 pin a are output from the free-run (time-free) VCO.
1-- 1412n5 _
70S.2kHz
T
27
1
1-------11.3)15----------
H .. --'v--[~[
r--236nS --!--236n5----i
T
s.ov
1
4.23MHz
--j II., S I-
1-- 236'S---j
T
176.4kHz
5,OV
1
ADJUSTMENT/REGLAGES/ABGlEICH
ADJUSTMENT/REGLAGES/ABGLEICH /"
ADJUSTMENT
POWER AMP UNIT (X07-2320-82)
REGLAGE DE NIVEAU DE SORTIE
jacks de sortie/ entree numerique et verrouiller I
circuit de verrouillage de phase (PLL) du KA-3300D.
Connecter une charge de 10k.Q au jack "DIRECT OUT" N/A et connecter un
vo lt ae t re CA
a travers la charge.
Fai re iouer Ie signal
de 1kHz, 0 dB . du CD d' essai.
VRI (G) VR2 (D)
Regier pour que
la tension de sortie soit de 2 V.
(b)
DC voltmeter
CD player
INPUT OUTPUT AMPLIFIER ALIGNMENT
No. ITEM SETTI NGS SETTINGS S Er:r'INGS' POINTS ALIGN FOR FIG.
Connect a DC
IDLE voltmeter across VRI (L)
I CURRENT - CP3 (L) VOLUME: 0 VR2 (R) 9mV (a)
, CP4 (R) o
CD DIGITAL OUT
SIGNA6r'PROCESSORUNIT (X32-1112-71)
Cord with mini plug
INPUT OUTPUT AMPLIFIER ALIGNMENT
No. ITEM SETTINGS SETTINGS SETTI NGS POINTS ALIGN FOR FIG.
Connect the digi Connect a load of
tal output/input 10 k.Q to the D/A Play the 1kHz,
I OUTPUT LEVEL jacks and lock DIRECT OUT jack and o dB signal VRI (L) Adjust so that (b)
ADJUSTMENT the PLL connect an AC volt- of the test CD. VR2 (R) the output voltage is 2 V.
of the KA-3300D. meter across the load. Optical fiber cable
KA-3300D
REGLAGES
UNITE D'AMPLIFICATEUR PRINCIPAL (X07-2320-82)
(a)
REGLAGE DE REGLAGE DE REGLAGE DE POINS
N' ITEM L' ENTREE LA SORTIE L' AMPLIFICATEU L' ALIGNEMENT ALl GNER POUR FIG.
Connecter un
COURANT DE voltmetre de CC sur VRI (G)
I POLARISATION - CP3 (G) VOLUME: 0 VR2 (D) 9mV (a)
CP4 (D) AC voltmeter
N'
REGLAGE DE L' ENTREE
FIG.
UNITE DE DISPOSITIF DE TRAITEMENT DE SIGNAUX (X32-1112-71)
ITEM
REGLAGE DE LA SORTIE
Resistor 1 0 kO
ABGLEICH
HAUPTVERST ARKER (X07 -2320-82)
E I NGANGS- AUSGANGS- VERSTilRKER ABGLE I CH-
HR. GEGENSTAND EINSTELLUNG EINSTELLUNG EINSTELLUNG PUNKTE ABGLEICHEN FUR ABB.
Einen
Gleichspannungs-
messer tiber VRI (L)
I LEERLAUFSTROM - CP3 (L) VOLUME: 0 VR2 (R) 9rnV (a)
CP4 (R)
anschlieBen. SIGNALPROZESSOR (X32-1112-71)
EINGANGS AUSGANGS- VERSTiI RK ER ABGLEI CH-
NR, GEGENSTAND EINSTELLUNG EINSTELLUNGS EINSTELLUNG PUNKTE ABGLEICHEN FUR ABB.
Die Digital- Eine Last von 10k.Q
Eingang/Ausgang- an die D/A DIRECT
Buchsen OUT-Buchse Das 1kHz, So einstellen,
I AUSGANGSPEGEL- anschl ieBen ansch 1 i eBen und o dB Signal VRI (L) daB die Ausgangsspannung (b)
EINSTELLUNG und den PLL ein Wechselstrom- der Tes t -CD VR2 (R) 2 V bet ragt.
des KA -3300D Voltmeter tiber spiel en.
verriegeln. die Last anschlieBen. 28
~ - ~~~~~;~ ~~~A:~~.:~ 1 J I 111 S7 .----------- __ --<3h i :' ~ I
~)~I~,,~:D~I~I~t~TU~N~E~R: ~1:J::::~~D~~~,,2:~:O:-:-:::::0:~:!=IP=H=O=N=0=1 ~~*:;:,--"i~~;~;l~~~ l ~:6)-:-~-:~ Q::;~~I'==~=~===;ll"·,';~f ',;;~,' " T [ . , T ~~U:"'~-Sll-l +- __ ~ __ -ihl---'.J~~r-~-,-~-----<"h t "'1:'~ro_;:~:~.:~:V:'V==I:M:UT:I:N:G:R:E:L:AY:I====+-. I
p-J - -~'~~,;-~l-- -{~-I~ - ff-b c "" .. I cas o.aa ,____, ::Jf'i-r-- '-.s;;-,;:.:_ 'rtN =L-:::::_'l~_-)___:_::'~~mgLJE~.=..JJ ~~ I ~CNI3 J, fr---;:~t=R' .=t--?62K~K;:aJ i!!~ I
1- tlilb- t1 tlr1tP ~-u:i:r R2 4.," I C240.22 7 ~ r4-- T y.; 0 ON ~df~ , >- t 'I"'~ ~ en i
r- - ~ _ ~~ PF~" 'f I ~w_~ '!F'-F~-:-+-r-)"" :i I ON l .--t---=:---+r---c-_-QJ __ ~ 1 1"1"' .r2~ '~~:.:! L..:,3'"'6 ·E_2:-Ic:;»--/(3;:I-~__' ~ ; my.[Y-!---+-..::9:;r-_~- 1~:J I
----"= _n ~ ---- L-~~_" MONO [E~~--~~ oJi ~ n ! 0 :-r T I f ;,~ ~i 4 4 R6 62K 1 '. I
DC voltages are as measured with a high impedance voltmeter with no signal input. Values may vary slightly due to variations between individual instruments orland units.
Les tensions c.c, doivent etr e rnesu rees avec un voltmetre a haute impedance sans signal d'entree, Les valeurs peuvent differer leqerement du fait des variations inherentes aux appareils et aux instruments de mesure individuels.
Die angegebenen G leichspannungswerte wurden mit einern hochohmigen Spannungsmesser ohne Eingangssignal gemessen. Dabei schwanden die MeBwerte aufgrund von Unterschieden zwischen einzelnen Instrumenten oder Geraten u.U, geringfOgig.
CAUTION: For continued safety, replace safety critical cornponents only with manufacturer's recommended parts (refer to parts list}. ~ Indicates safety critical components. To reduce the risk of electric shock, leakage-current or resistance measurements shall be carried out (exposed parts are acceptably insulated from the supply circuit) before the appliance is returned to the customer.
fu !!-- ~~ RI9 s '~_ \.'::~" R53 'C94 ~,Ol 048: 2SA733IA)(O,PJ
'\;\ f. 2.:~M ~~ ~ 220 or 2SA999 (E,F)
~ Q3 ~( ~~. ~~~
t--w,--t-2--l2CO~P lOOp 10 ~f.~ ! ,oi~~6,3
R3I 620 . 09 7 R3~. 560 +
'"
~ i
~ ~ ~
~ '=' 013 ~
~ <'- l~ ~
,~~ '" ~: u
.' I I~
>-- ---« 0 12
~----~~----~~~
~'OO'W~
1 X08112121
I I I
I I __ J
2SC2167 2S01266
NJM2041 0·0 NJM55320-0
'~.
1
c.
NO
NO
: uQ
0
0
0
.
~ POWER AMPLIFIER PRE DRIVER PART
-_.-f< )(~< I PI-------
2SK371
pP04027BC
'~
,
,,5
(~
J '0'14 @(X07-2320-82HA/2) CNI2
CN14
42
43
DC voltages are as measured with a high impedance voltmeter with no signal input. Values may vary slightly due to variations between individual instruments or/and units.
Les tensions c.c, doivent etr e rnesurees avec un voltmetre a haute impedance sans signal d'entree. Les valeurs peuvent differer legerement du fait des variations inherentes aux appareils et aux instruments de mesure individuels.
Die angegebenen Gleichspannungswerte wurden mit einem hochohm igen Spannungsmesser ohne Eingangssignal gem essen. Dabei schwanden die MeBwerte aufgru nd von Untersch ieden zwischen einzelnen Instrumenten oder Geriiten u.U, geringfOgig.
CAUTION: For continued safety, replace safety critical components only with manufacturer's recommended parts (refer
to parts list).
it. Indicates safety critical components. To
reduce the risk of electric shock, leakage-current or resistance measurements shall be carried out (exposed parts are accepta-
KA-3300D
bly insulated from the supply circuit) before the appliance is returned to the customer.
DC voltages are as measured a h'fuh impedance voltmeter with no signal input. Values may vary slightly due to variations between individual instruments or/and units.
R41 90.9K
C29 56P 125V
Les tensions c.c, doivent etre rnesurees avec un voltmime a haute impedance sans signal oentree. Les valeurs peuvent diff'erer legerement duvfait des variations inherentes aux appareils et aux instruments de mesure individuels,
~
R39 1M
R43 909
crac
F!-
Die angegebenen Gleichspannungswerte wurden mit einem hochohm iqen. Spannungsmesser ohne Eingangssignal qernessen, babei schwanden die MeBwerte aufgrund '. von Unterschieden zwischen einzelnen lnstrurnenten oder Geriiten u.U, geringfugig.
1 CAUTION: For continued safety, replace safety critical com-
ponents only with manufacturer's recommended parts (refer to parts list). if} Indicates safety critical components. To reduce the risk of electric shock, leakage-current or resistance measurements shall be carried out (exposed parts are acceptsbly insulated from the supply circuit) before the appliance is returned to the customer.
TC74HCl12P TC74HC~73P
"~
1
CXD1076P
15
AN7805F
~ 'OUTPUT
~ND
INPUT (Casel
AN7905F
OUTPUT (Casel INPUT
GND
~PC78L05
OUTPUT
TC74HCOOF TC74HC04F
~PC1237HA
KA-3300D
KENWOOD
(X32-1112-71) (D/6)
-1----
7r1
fl J
([NPUT 5'1 )
-, I I I I I I
'16
f- __ V':"" __ -1 1 eNS ,- __ v:;- _ _JI eN6
'IS
1-_..;1\-,- __ ] eN' ,- _ _cl\r-_-"I eN3
-- 4<~N-_+ _ _;;W.;;J_,/
'''9 r~l--f
180 1;;1 J
___:ttw
11,2
2SA733IAHO,P) or 2SA999IE,F) 2SC945IAHO,PI or 2SC23201E,FI 2SC20031 L ,K)
In the actual circuit, 012 is eliminated, and shown enclosed in broken lines (---I in the circuit diagram. is not operating. Then the models with Serial No. 73KOOOOO and after, the parts boxed with "---" are eliminated.
47
(RECE1VED DATA DEMODU~
r----;;;;ALOG LPF ~UTTERWORTH)
RZI 3.16K
(OUTPUT AMP
IC9
R3I !.62K
~[
e 8
7
~~
>----t--;
90,
CZ9 56P 125v
~
R39 1M
ca R43 47{ 909 10!
DIGITAL INPUT I 10PTrCALl
I
I
I
l!::_
IC 1,2 PCM56P - K
IC3 ~Io NE5532P 03,4
IC 21 TC74HCU04F 05,6
IC22,23 TC74HCOOF 07
IC24 TC74HC04F 08
IC25 TC74HC386P
IC26,35 TC74HCI23P D! ....... 3
IC 27 MC4044P 04 ~13,
IC 28 SN74LS624N 15~23
IC29 TC74HC74P 36~40
IC3o,38 TC74HC393P 014
IC 31,33 TC74HCI12P 024
IC32 TC74HC86P 025,26
IC34,43 TC74HC04P 027-35
IC36 TC74HC02P 041
IC 37 NJM5550
IC39 TC74HCOOP AI
IC40,44 TC74HCU04P
IC41 SM58048-T or SM58040-T
IC42 CXoI076P
IC45 ~PC78LOS
IC46 NJM79L05A
IC47 AN780SF'
IC48 AN7905F
IC49 MS220P w3
or 2SA9991 E, F I or 25C23201E,FI
25C20031 L ,KI 250126610, PI 25894110, P I
830-0431-05 155133 or 155176
1$$237111 E-272
RoS,IJ51821 or Hl55.151821 o5MIAI
MAI56
W02-0726-05
(INPUT SW )
-,
I I I I
I I
(X32-1112-71) (i
,-
I
I
I
I
I I I I I
I I I
_ _j
(X32-1112-71) (C/6)
I
I I
_j
~URE
(X07-2320- 82){A/2J WIO
------------------,
I I I I I I
5V
-I I I I I
I
051-54
(AVR CIRCUIT
025,20 : ,IIPA68H I K, Ll
027-30: 25C9451AlIO,PI or 25C23201E,FI Q31-34: 2SA733IA){Q,P) or 2SA9991E,Fl 035-42: 25C263210 ,R ,51
Q43.44 : _2SA1124ta ,R,S)
011,12 : 1$5133 or 1$5176 013,14: MA270lAI
Ql-4 (PRE DRIVER)
r-- -- -- --- ---
I I I
__j
IX07-2320-821
07 I 11-22 08
D9, 10 ,62 ....... 64 Dll ,12 023-26
: 1$5133 or I : E - 202
: E- 152
: MA27Q(A) : RU4Z
: ISS 131 or I~
lC 1,2 IC3
: TA2030
: pPCI237HA
027,28 : OATI018P5 *5
029,30 : 25C32B4 *5
Q31 ,32 : 2SA 1303 *5
051,58,59: 250126610,PI
052,60 : 25B94110,PI
053 : 2SCI845tF,El
Q54,57 : 2SA992{F,El
055 : 25A111010,RI
e 0
I I
022 B
e =
023
06 07 08 09 010 011 012 013 =
0 0 0 a a a a a 0170 a DI8
IL____ [§ [§ [§ 152-0 I 52-b 152-< 152-d 152-0 I ~o ~J DI40 0'015 =
SI-< SI-b SI-o
05 e S90bU-O e 56-0 S6-b e 57 e DI D2 03
0 0 0 D DS5 = = =
0 = = =
51-0 SI-b SI-c
J L\' ~ ~ )1 L
I I~ /1 1 01,2 :2SC945IAIt0,PI
DC voltages are as measured with a high impedance voltmeter with no signal input. Values may vary slightly due to variations between individual instruments or/and units.
Les tensions c.c. doivent etr e masurees avec un voltmetre a haute impedance sans signal derrtree. Les valeurs peuvent differer legerement du fait des variations inherentes aux appareils et aux instruments de mesure individuels.
Die angegebenen Gleichspannungswerte wurden mit einem hochohmigen Spannungsmesser ohne Einqanqssignal gemessen. Dabei schwanden die MeBwerte aufgrund von Unterschieden zwischen einzelnen Instrumenten oder Gersten u.U. geringfugig.
CAUTION: For continued safety, replace safety critical components only with manufacturer's recommended parts (refer
to parts list).
& Indicates safety critical components. To
reduce the risk of electric shock, laakage-current or resistance measurements shall be carried out (exposed parts are acceptably insulated from the supply circuit) before the appliance is returned to the customer.
(
I
PARTS LIST
* New Parts Parts without Parts No. are not supplied.
Les articles non mentlonnes dans Ie Parts No. ne sont pas fournls. Telle orme Parts No. werden nlcht gellefert.
* New Parts
PARTS LIST
Parts without Parts No. are not supplied.
Les articles non mentlonnes dans Ie Parts No. ne sont pas fournls. Telle orme Parts No. werden nlcht gellefert.
BINDING PISlST (GND)
AUDIISl CISlRD
AC PISlWER CISIRD E
AC PISlWER CISIRD M
AC PISlWER CISIRD KP
AC F'ISIWER C!9RD T
FUSE (SEMKISl) (250V T4A) TE
FUSE WU (250V 8A) I<P
FUSE (250V 4A) M TE KPM
AUX (Terminated vyith 47 kohms+ 250 pF) Phono Input Capacity'(DIN)
(MM)
(MC) ;
Phono Maximum Input level (MM)
(MC)
Output Level/Impedance TA.~EREC;,,;
PRE OUT .
Phono Frequency Response Tone-Control ~ ',
BASS (at 50 Hz)
(at 100 Hz) TREBLE (at 10 kHz)
(at 20 kHz)
Loudness Control (at - 30 dB Volume Level) Subsonic Filter (at - 3 dB)
Digital Inputs Dlgltaf,0utput Ie
Signar>to Noisekatio Total Harmonic Distortion Channel Separation
GENERAL
Power Consumption
AC Outlet
Dimensions
Weight (Net) UHF'66)
220 W 160W
160 W+160 W
1 78 W per channel at 8 ohms 320 W per channel at 4 ohms 460 W per channel at 2 ohms
0.004% at 150 W into 8 ohms 0.003% at 75 W into 8 ohms
0.005% at 150 W with VOLUME -20 dB 0.003% at 150 W into 8 ohms
150 Hz into 8 ohmsl
to 50 kHz at 0.04% T.H.D. to 150 kHz/+O -3 dB
2.i5pmVI 47 kohms O. r mV/100 ohms 150 mVI 47 kohms
87 dB 12.5 mVI 76 dB 1250 pVI 110 dB
60 dB
61MB
63'dB
67 dB
58 dB
250 pF 1,650 pF
210 mV, IRMSI T.H.D. 0.003% at 1 kHz 8 mV, IRMSI T.H.D. 0.003% at 1 kHz
150 mV/220 ohms
2 V/600 ohms
RIAA standardcurve ±0.2 dB 120 Hz to 20 kHzl
±10 dB ±1O dB ±10 dB ±10 dB
0-8 dB at 100 Hz 6 dBIOct. at 18 Hz
Optical xl: -15 - - 28 dBrn Coaxial x 2: 0.5 Vp-pl75 ohms Coaxial xl: 0.5 Vp-pl75 ohms More than 105 dB at 1 kHz Less than 0.003% at 1 kHz_ More than 115 dB att kHz
7.1 A IU.S.A. and Canadal 280 W IOtherl
Switched x2 1100 W)
Unswitched x 1 (400 W) (Except European and U.K. Models)
W 440 mm 117-5/16"1 H 170 mm 16-11/16"1 o 420 mm 116-9/16") 19.1 kg 1421b)
KENWOOD CORPORATION
Shionogi Shibuya Building, 17-5, 2-chome Shibuya, Shibuya-ku, Tokyo 150, Japan
Rembrucker-Str. 15, 6056 Heusenstamm, West Germany
TRIO-KENWOOD FRANCE SA Hi-Fi·VIDEO·CAR Hi-Fi
13, Boulevard Ney, 75018 Paris, France
TRIO-KENWOOD UK LTD.
17 Bristol Road, The Metropolitan Centre, Greenford, Middx. UB6 8UP England
KENWOOD ELECTRONICS AUSTRALIA PTY. LTD.
4E Woodcock Place, Lane Cove, N.S.W. 2066, Australia
KENWOOD & LEE ELECTRONICS, LTD.
Wang Kee Building, 5th Floor, 34-37, Connaught Road, Central, Hong Kong
Kenwood follows a policy of continuous advancements in development. For this reason specificatlons may be
changed without notice. .
Kenwood poursuit une politique de proqres constants en ce qu i doncerne Ie developpernent, Pour cette raison, les specifications sont sujettes a modifications sans preavis.
Kenwood strebt standiqe, Verbesserungen in der Entwick lung an. Daher bleiben Anderunqen der technischen Daten jederzeit vorbehalten.