VETRIVINAYAHA COLLEGE OF ENGINEERING AND

TECHNOLOGY, THOTTIAM-621215 VETRIVINAYAHA COLLEGE OF ENGINEERING AND

DEPARTMENT OF ELECTRONICS AND COMMUNICATION TECHNOLOGY, THOTTIAM-621215
ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION
UNIT TEST-II ENGINEERING
EC1256-ELECTRONICS AND MICROPROCESSORS UNIT TEST-II
DATE: 15.02.11 MAX MARKS: 50 EC1256-ELECTRONICS AND MICROPROCESSORS
YEAR/SEM: II/IV TIME: 1.30 HRS DATE: 15.02.11 MAX MARKS: 50
NOTE: ANSWER ALL THE QUESTIONS YEAR/SEM: II/IV TIME: 1.30 HRS
NOTE: ANSWER ALL THE QUESTIONS
PART-A (5*2=40 MARKS)
1. Subtract (1001)2 from (1110)2 PART-A (5*2=40 MARKS)
2. Multiply (1110)2 and (1111)2 1. Subtract (1001)2 from (1110)2
3. write down all the basic rules of Boolean algebra 2. Multiply (1110)2 and (1111)2
4. show how to implement an AND gate using OR gate and NOT gate 3. write down all the basic rules of Boolean algebra
5. Simplify the following 4. show how to implement an AND gate using OR gate and NOT gate
i) ABC(BD+CDE)+AC 5. Simplify the following
ii) (A+B)C+ABC) i) ABC(BD+CDE)+AC
PART-B (40 MARKS) ii) (A+B)C+ABC)
6. Explain briefly about all the logic gates. Verify XOR gate using PART-B (40 MARKS)
A B + A B. (16) 6. Explain briefly about all the logic gates. Verify XOR gate using
A B + A B. (16)
7. Write short notes on SOP, POS and their gate level realization. (6)
8. Explain the following 7. Write short notes on SOP, POS and their gate level realization. (6)
i) Half Adder.(3) 8. Explain the following
ii) Full Adder.(3) i) Half Adder.(3)
9. With necessary logic diagrams and truth table explain RS and JK flip ii) Full Adder.(3)
flop. (8) 9. With necessary logic diagrams and truth table explain RS and JK flip
10. State the following flop. (8)
i) Sequential and combinational logic circuits. (2) 10. State the following
ii) Two forms of DeMorgan’s laws. (2) i) Sequential and combinational logic circuits. (2)
ii) Two forms of DeMorgan’s laws. (2)