Digital Electronics FAQ at Virtual VLSI

2/25/2010 Digital Electronics FAQ @ Virtual VLSI
Digital Electronics
Design a divide-by-3 sequential circuit with 50% duty circle?
What are the different Adder circuits you studied?
Give a circuit to divide frequency of clock cycle by two ?
What are set up time & hold time constraints What do they signify Which one is critical for estimating
maximum clock frequency of a circuit?
Explain about setup time and hold time, what will happen if there is setup time and hold tine violation,
how to overcome this? What is skew, what are problems associated with it and how to minimize it?
What is the function of a D flip-flop, whose inverted output is connected to its input ?
Design a circuit to divide input frequency by 2.
Design a divide-by-3 sequential circuit with 50% duty cycle.
What are the different types of adder implementations ?
Draw a Transmission Gate-based D-Latch.
Give the truth table for a Half Adder. Give a gate level implementation of it.
Design an OR gate from 2:1 MUX.
Design an XOR gate from 2:1 MUX and a NOT gate
What is the difference between a LATC H and a FLIP-FLOP ?
Design a D Flip-Flop from two latches.
What are the two types of delays in any digital system ?
Design a Transparent Latch using a 2:1 Mux.
Design a 4:1 Mux using 2:1 Muxes and some combo logic.
What is metastable state ? How does it occur ?
http://www.virtualvlsi.com/digital.asp 1/11
Design a 3:8 decoder
Design a FSM to detect sequence "101" in input sequence.
C onvert NAND gate into Inverter, in two different ways.
Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the mux.
Design a divide by two counter using D-Latch.
Design D Latch from SR flip-flop.
Define C lock Skew , Negative C lock Skew, Positive C lock Skew.
What is Race C ondition ?
Design a 4 bit Gray C ounter.
Design 4-bit Synchronous counter, Asynchronous counter
Design a 16 byte Asynchronous FIFO
What is the difference between an EEPROM and a FLASH ?
What is the difference between a NAND-based Flash and a NOR-based Flash ?
Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.
How can you generate random sequences in digital circuits?
Give two ways of converting a two input NAND gate to an inverter
Given a circuit, draw its exact timing response. (I was given a Pseudo RandomSignal Generator; you
can expect any sequential ckt)
What are set up time & hold time constraints? What do they signify? Which one is critical for estimating
maximum clock frequency of a circuit?
Give a circuit to divide frequency of clock cycle by two Design a divide-by-3 sequential circuit with
50% duty circle. (Hint: Double the C lock)
Suppose you have a combinational circuit between two registers driven by a clock. What will you do if
the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational
circuit transistors)
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Give the truth table for a Half Adder. Give a gate level implementation of the same.
Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the
output)
How do you detect if two 8-bit signals are same?
How do you detect a sequence of "1101" arriving serially from a signal line?
What is glitch? What causes it (explain with waveform)? How to overcome it?
Given only two xor gates one must function as buffer and another as inverter?
What is difference between latch and flipflop?
Build a 4:1 mux using only 2:1 mux?
Difference between mealy and moore state machine? Advantages and disadvantages
Difference between onehot and binary encoding?
What are different ways to synchronize between two clock domains?
Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows up (the leading 0s
cannot be used in more than one sequence)?
How to achieve 180 degree exact phase shift?(don’t use inverter)
What is significance of ras and cas in SDRAM?
Tell some of applications of buffer?
Implement an AND gate using mux?
What will happen if contents of register are shifter left, right?
Design a four-input NAND gate using only two-input NAND gates.
Difference between Synchronous and Asynchronous reset.?
Give two ways of converting a two input NAND gate to an inverter?
What is a multiplexer?
How can you convert an SR Flip-flop to a JK Flip-flop?
How can you convert the JK Flip-flop to a D Flip-flop?
What is Race-around problem?How can you rectify it?
7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
Design all the basic gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer?
Design a circuit that calculates the square of a number?
How will you implement a Full subtractor from a Full adder?
In a 3-bit Johnson's counter what are the unused states?
What is an LFSR .List a few of its industry applications.?
what is false path?how it determine in ckt? what the effect of false path in ckt?
What are multi-cycle paths?
what is difference between RAM and FIFO?
The circle can rotate clockwise and back. Use minimum hardware to build a Is it possible to reduce
clock skew to zero?
Design a FSM (Finite State Machine) to detect a sequence 10110?
C onvert D-FF into divide by 2. (not latch)?
Give the circuit to extend the falling edge of the input by 2 clock pulses?
Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch ?
How to implement a Master Slave flip flop using a 2 to 1 mux?
How many 2 input xor's are needed to inplement 16 input parity generator ?
Design a circuit for finding the 9's compliment of a BC D number using 4-bit binary adder and some
external logic gates?
what is local-skew, global-skew,useful-skew mean?
What are the various timing-paths which i should take care in my STA runs?
What are the various components of Leakage-power?
What are the various yield-losses in the design?
what is meant by virtual clock definition and why do i need it?
What are the various Variations which impacts timing of the design?
What are the various Design constraints used while performing Synthesis for a design?
what are the various capacitances with an MOSFET?
Vds-Ids curve for an MOSFET, with increasing Vgs.
Basic Operation of an MOSFET.

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What is C hannel length Modulation?
what is body effect?
What is latchup in C MOS design and ways to prevent it?
Why is NAND gate preferred over NOR gate for fabrication?
What is Noise Margin? Explain the procedure to determine Noise Margin Explain sizing of the inverter?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
What is Noise Margin? Explain the procedure to determine Noise Margin?
What happens to delay if you increase load capacitance?
What happens to delay if we include a resistance at the output of a C MOS circuit?
What are the limitations in increasing the power supply to reduce delay?
How does Resistance of the metal lines vary with increasing thickness and increasing length?
For C MOS logic, give the various techniques you know to minimize power consumption?
What is C harge Sharing? Explain the C harge Sharing problem while sampling data from a Bus?
Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit
to one large inverter?
Give the expression for C MOS switching power dissipation?
What is Body Effect?
Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
What is the fundamental difference between a MOSFET and BJT ?
Which transistor has higher gain. BJT or MOS and why?
Why do we gradually increase the size of inverters in buffer design when trying to drive a high
capacitive load?
In C MOS technology, in digital design, why do we design the size of pmos to be higher than the
nmos.What determines the size of pmos wrt nmos. Though this is a simple question try to list all the
reasons possible?
Why PMOS and NMOS are sized equally in a Transmission Gates?
What happens when the PMOS and NMOS are interchanged with one another in an inverter?
What is the fundamental difference between a MOSFET and BJT ?
What is the basic difference between Analog and Digital Design?
What is Design For Test and why it is done.
What is clock gating? How and why it is done.
What is pipelining, how may it affect the performance of a design
What is the difference between transport delays and inertial delays in VHDL
What determines the max frequency a digital design may work on. Why hold time is not included in the
calculation for the above.
What will happen if output of an inverter is shorted to its input What is noise margin.
Why are p-mos larger than n-mos in C MOS design
Draw DC curve of inverter and Re-Draw it if pmos and nmos are equal
What is Latch-up ?
How can an Inverter work as an amplifier
Design a state machine which divides the input frequency of a clock by 3. Given that the phase change
in the output due to propogation delay in of the flip flop is acceptable up to a delay offered by a single flip
flop only.
Why does a pass gate requires two transistors(1 N and 1 P type) C an we use a single transistor N or P
type in a pass gate? If not why? and if yes then in what conditions?
Why C MOS why not N-MOS or P-MOS logic, when we know that the number of gates required in C MOS
are grater than in n-mos or p-mos logic.
How much is the max fan out of a typical C MOS gate.
What are dynamic logic gates? What are their advantages over conventional logic gates
Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles
What is the relation between binary encoding and or gray encoding.
Make a T Flip Flop using a D Flip Flop
How you will make a Nand Gate function like an inverter.
Design a state machine to detect a '1101' pattern in a stream. detect both, overlapping and non
overlapping patterns.
What are MISRs, example usage?
What is D-FF?
What is the basic difference between Latches and Flip flops?

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What is a multiplexer?
How can you convert an SR Flip-flop to a JK Flip-flop?
How can you convert an JK Flip-flop to a D Flip-flop?
What is Race-around problem? How can you rectify it?
Which semiconductor device is used as a voltage regulator and why?
Explain an ideal voltage source?
Explain zener breakdown and avalanche breakdown?
What are the different types of filters?
What is the need of filtering ideal response of filters and actual response of filters?
What is sampling theorem?
What is impulse response?
Explain the advantages and disadvantages of FIR filters compared to IIR counterparts.
What is C MRR?
Explain half-duplex and full-duplex communication?
Which range of signals is used for terrestrial transmission?
Why is there need for modulation?
Which type of modulation is used in TV transmission?
Why we use vestigial side band (VSB-C 3F) transmission for picture?
When transmitting digital signals is it necessary to transmit some harmonics in addition to fundamental
frequency?
For asynchronous transmission, is it necessary to supply some synchronizing pulses additionally or to

supply or to supply start and stop bit?
BPFSK is more efficient than BFSK in presence of noise. Why?
What is meant by pre-emphasis and de-emphasis?
Explain 3 dB cutoff frequency? Why is it 3 dB, not 1 dB?
Explain ASC II, EBC DIC ?
Give two ways of converting a two input NAND gate to an inverter
Give a circuit to divide frequency of clock cycle by two
Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the C lock)
Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the
output)
How do you detect a sequence of "1101" arriving serially from a signal line?
Design any FSM in VHDL or Verilog.
Explain RC circuit.s charging and discharging.
Explain the working of a binary counter.

Describe how you would reverse a singly linked list.
Implement D- latch from - RS flip flop; - multiplexer.
How to convert D-latch into JK-latch and JK-latch into D-latch?
You have two counters to 16, built from negedge D- FF . First circuit is synchronous and second is
"ripple" (cascading). Which circuit has less propagation delay?
Top
What is the difference between flip-flop and latch?
Write an HDL code for their behavioral models.
How to design a divide-by-3 counter with equal duty cycle ?
C onvert D-latch into divider by 2.
Design a 1-bit fulladder using a decoder and 2 "or" gates?
If inverted output of D flip-flop is connected to its input how the flip-flop behaves?
Design a circuit to divide input frequency by 2?
Design a divide by two counter using D-Latch.
What are the different types of adder implementation?
Draw a Transmission Gate-based D-Latch?
Design an OR gate from 2:1 MUX.
What is the difference between a LATC H and a FLIP-FLOP?
Design a D Flip-Flop from two latches.
Design a 2 bit counter using D Flip-Flop.
What are the two types of delays in any digital system
Design a Transparent Latch using a 2:1 Mux.
Design a 4:1 Mux using 2:1 Mux's.
What is metastable state? How does it occur?
Design a 3:8 decoder
Design a FSM to detect sequence "101" in input sequence
C onvert NAND gate into Inverter in two different ways.
Design a D and T flip flop using 2:1 mux only.
Design D Latch from SR flip-flop.
Define C lock Skew, Negative C lock Skew, Positive C lock Skew?
What is race condition? How it occurs? How to avoid it?
Design a 4 bit Gray C ounter?
Design 4-bit synchronous counter, asynchronous counter?
Design a 16 byte asynchronous FIFO?
What is the difference between a EEPROM and FLASH?
What is the difference between a NAND-based Flash and NOR-based Flash?
Which one is good: asynchronous reset or synchronous reset? Why?
Design a simple circuit based on combinational logic to double the output frequency.
Implement comparator using combinational logic, that compares two 2-bit numbers A and B. The
comparator should have 3 outputs: A > B, A < a =" B.">
Give two ways of converting a two input NAND gate to an inverter?
What is the difference between mealy and moore state-machines?
7 bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?
Design all the basic gates NOT, AND, OR, NAND, NOR, XOR, XNOR using 2:1 Multiplexer.
How will you implement a full subtractor from a full adder?
In a 3-bit Johnson's counter what are the unused states?
What is difference between RAM and FIFO?
What is an LFSR? List a few of its industry applications.
Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
How to implement a Master Slave flip flop using a 2 to 1 mux?
How many 2 input xor's are needed to inplement 16 input parity generator?
C onvert xor gate to buffer and inverter.
Difference between onehot and binary encoding?
What are different ways to synchronize between two clock domains?
How to calculate maximum operating frequency?
How to find out longest path?
How to achieve 180 degree exact phase shift?
What is significance of ras and cas in SDRAM?

Top
Tell some of applications of buffer?
Implement an AND gate using mux?
What will happen if contents of register are shifter left, right?
What is the basic difference between analog and digital design?
What advantages do synchronous counters have over asynchronous counters?
What types of flip-flops can be used to implement the memory elements of a counter?
What are the advantages of using a microprocessor to implement a counter rather than the
conventional method (flip-flop and logic gates)?
What is the principal advantage of Gray C ode over straight (conventional) binary?
What does Pipelining do?
Design divide by 2, divide by 3 circuit with equal duty cycle.
How many 4:1 mux and 2:1 mux do you need to design a 8:1 mux?
Define Moore, Mealy state machines. Which one is good for timing?
Design a FSM to detect 10110. What is the minimum number of flops required?
Design a simple circuit based on combinational logic to double the output frequency.
Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)
Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
Minimize: S= A' + AB
What is the function of a D-flipflop, whose inverted outputs are connected to its input?
How to synchronize control signals and data between two different clock domains?
Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in
heads.
In what cases do you need to double clock a signal before presenting it to a synchronous state
machine?
How many bit combinations are there in a byte?
C onvert 65(Hex) to Binary
C onvert a number to its two's compliment and back.
What is the 1's and 2's complement of the decimal number 25.
If A?B=C and C ?A=B then what is the boolean operator ?
What is the difference between FPGA and ASIC ?
Implement F= not (AB+C D) using C MOS gates?
What is charge sharing?
Explain the working of 4-bit Up/down C ounter?
Id vs. Vds C haracteristics of NMOS and PMOS transistors?
Differences between DRAM and SRAM?
Given a circuit and asked to tell the output voltages of that circuit?
How can you construct both PMOS and NMOS on a single substrate?
What happens when the gate oxide is very thin?
What is pipelining and how can we increase throughput using pipelining?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
What is SPIC E?
What is FPGA?
Implement F = AB+C using C MOS gates?
What is hot electron effect?
Define threshold voltage?
Factors affecting Power C onsumption on a chip?
Explain C lock Skew?
Why do we use a C lock tree?
Explain the various C apacitances associated with a transistor and which one of them is the most
prominent?
Explain the Various steps in Synthesis?
Explain ASIC Design Flow?
Which gate is normally preferred while implementing circuits using C MOS logic, NAND or NOR? Why?
4-1 demultiplexer is to be implemented using a memory chip. how many address lines and word length
required Ans. 4, 1
Implement the following using 4X1 MUX. A'BC + AB'C +ABC '
How will you convert an S-R FF into J-K FF ?
A logic gate is an electronic circuit which a. Makes logic decisions b. Allows electron flow in only
direction c. Works on binary algebra d. Alternates between 0 and 1
The process of converting analog signal into digital signals so they can be processed by a receiving
computer is referred to as
a. Modulation b. Demodulation c. Synchronizing d. Desynchronizing
EBC DIC ca code up to how many different characters?

a. 8 b. 16 c. 32 d. 64 e. 256
An integrated circuit is a. A complicated circuit b. An integrating device

c. Much costlier than single transistor d. Fabricated in a single silicon chip
Draw a diode. Explain the operation. What is threshold voltage. Typical values.
Why the current rises rapidly. Direction of current. Which one is anode - cathode.
What is a PN junction doide. Draw npn transistor ? Expalain what r the terminals ? Why so called.Utility
of it. Give example. What is a JK-FF? Utility of JK.
What are universal gates & why ? Draw or with NOR.
Which has least propagation delay?

a)EC L b)TTL c)RTL d)C MOS
For mod 9 counter how many min flips flops are required
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2/25/2010 Digital Electronics FAQ @ Virtual VLSI

Design a divide-by-3 sequential circuit with 50% duty circle?

What are the different Adder circuits you studied?

Give a circuit to divide frequency of clock cycle by two ?

Design a circuit to divide input frequency by 2.

Design a divide-by-3 sequential circuit with 50% duty cycle.

Design a divide-by-5 sequential circuit with 50% duty cycle.

What are the different types of adder implementations ?

Draw a Transmission Gate-based D-Latch.

Design an OR gate from 2:1 MUX.

Design an XOR gate from 2:1 MUX and a NOT gate

What is the difference between a LATC H and a FLIP-FLOP ?

Design a D Flip-Flop from two latches.

What are the two types of delays in any digital system ?

Design a Transparent Latch using a 2:1 Mux.

What is metastable state ? How does it occur ?

Design a FSM to detect sequence "101" in input sequence.

C onvert NAND gate into Inverter, in two different ways.

Design a divide by two counter using D-Latch.

Design D Latch from SR flip-flop.

Define C lock Skew , Negative C lock Skew, Positive C lock Skew.

What is Race C ondition ?

Design a 4 bit Gray C ounter.

Design 4-bit Synchronous counter, Asynchronous counter

Design a 16 byte Asynchronous FIFO

What is the difference between an EEPROM and a FLASH ?

What is the difference between a NAND-based Flash and a NOR-based Flash ?

Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.

How can you generate random sequences in digital circuits?

Give two ways of converting a two input NAND gate to an inverter

Draw a Transmission Gate-based D-Latch.

How do you detect if two 8-bit signals are same?

What is difference between latch and flipflop?

Build a 4:1 mux using only 2:1 mux?

What are different ways to synchronize between two clock domains?

How to achieve 180 degree exact phase shift?(don’t use inverter)

What is significance of ras and cas in SDRAM?

Tell some of applications of buffer?

Implement an AND gate using mux?

What will happen if contents of register are shifter left, right?

Design a four-input NAND gate using only two-input NAND gates.

Difference between Synchronous and Asynchronous reset.?

Give two ways of converting a two input NAND gate to an inverter?

How can you convert an SR Flip-flop to a JK Flip-flop?

How can you convert the JK Flip-flop to a D Flip-flop?

What is Race-around problem?How can you rectify it?

How do you detect if two 8-bit signals are same?

Design all the basic gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer?

Design a circuit that calculates the square of a number?

How will you implement a Full subtractor from a Full adder?

In a 3-bit Johnson's counter what are the unused states?

What is an LFSR .List a few of its industry applications.?

What are multi-cycle paths?

what is difference between RAM and FIFO?

Design a FSM (Finite State Machine) to detect a sequence 10110?

C onvert D-FF into divide by 2. (not latch)?

How to implement a Master Slave flip flop using a 2 to 1 mux?

what is local-skew, global-skew,useful-skew mean?

What are the various components of Leakage-power?

What are the various yield-losses in the design?

what is meant by virtual clock definition and why do i need it?

what are the various capacitances with an MOSFET?