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  • CMOS Transmission Gate Fundamentals

    Încărcat de

    Avinash Vikram
    116 vizualizări4 pagini
    A transmission gate (TG) is a complementary CMOS switch composed of a parallel PMOS and NMOS transistor controlled by complementary signals. TGs can efficiently implement multiplexers, XOR, XNOR, latches, and flip-flops using fewer transistors than regular CMOS. For example, a 2-input XOR can be implemented using 8 transistors with TGs versus 12 for regular CMOS. However, TGs become inefficient for regular logic functions involving more than 3 levels and require buffers if more than 3 levels are needed.

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    15NOv- CMOS Transmission Gates

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    A transmission gate (TG) is a complementary CMOS switch composed of a parallel PMOS and NMOS transistor controlled by complementary signals. TGs can efficiently implement multiplexers, XOR, XNOR, latches, and flip-flops using fewer transistors than regular CMOS. For example, a 2-input XOR can be implemented using 8 transistors with TGs versus 12 for regular CMOS. However, TGs become inefficient for regular logic functions involving more than 3 levels and require buffers if more than 3 levels are needed.

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    Descărcați ca DOC, PDF, TXT sau citiți online pe Scribd
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    116 vizualizări4 pagini

    CMOS Transmission Gate Fundamentals

    Încărcat de

    Avinash Vikram
    A transmission gate (TG) is a complementary CMOS switch composed of a parallel PMOS and NMOS transistor controlled by complementary signals. TGs can efficiently implement multiplexers, XOR, XNOR, latches, and flip-flops using fewer transistors than regular CMOS. For example, a 2-input XOR can be implemented using 8 transistors with TGs versus 12 for regular CMOS. However, TGs become inefficient for regular logic functions involving more than 3 levels and require buffers if more than 3 levels are needed.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOC, PDF, TXT sau citiți online pe Scribd
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    din 4

    CMOS Transmission Gates:

     A Transmission Gate (TG) is a complementary CMOS switch.

    PMOS and NMOS are in parallel and are


    controlled by complementary signals

    - Both transistors are ON or OFF simultaneously.


    - The NMOS switch passes a good zero but a poor 1.
    - The PMOS switch passes a good one but a poor 0.

    VDD

    - Combining them we get a good 0 and a good 1 passed in both directions


    -
    - 0 0
    - Circuit Symbols for TGs: 1 1

    C’

    - TGs are efficient in implementing some functions such as multiplexers, XORs, XNORs,
    latches, and Flip-Flops.

     2 I./P XOR using TGs:


    F = A.B’ + A’.B , we need this: if A=1  F = B’ (pass B' to F)
    if A=0  F = B (pass B to F)
    using TGs: A’

    B’

    A
    8 Ts (2 inverters for A and B and two TGs) F=A+B
    Versus 12 Ts for regular CMOS
    B
    A'
     2 I/P XNOR
    F = A.B + A’B’ if A=1  pass B to F
    if A=0  pass B’ to F
    A

    B’

    A’

     General Logic using TGs: AOI 22:

    F = (AB + CD)’ if A=1 F = (B+CD)’


    B’ Then if C=1  F= (B+D)’ … and so on….

    0 C’
    B
    B A’
    C 24 Ts versus 8 T for regular
    D’ C CMOS  TGs are very
    B’ A inefficient for regular
    B' A functions
    C’

    C’ A’

    D’
    C
    C

    1
    C’

     2-1 mux using TGs S’


    F = S’.D0 + S.D1
    D1
    S Y
    0 D0 D0 S
    Y S Y
    1 D1
    D1
    D0
    S S’
     4-1 Mux in TGs:

    Y = S1’.S0’.D0 + S1’.S0.D1 + S1.S0’.D2 + S1.S0.D3

    S0 S1
    D0
    D0 D1 Y
    D2
    S0’ S1’
    S0’ S1 D3
    S0 S1

    D1 S1 S0 Y
    S0 S'1
    S0 S'1 Y 0 0 D0
    0 1 D1
    1 0 D2
    D2 1 1 D3
    S0’ S
    S'0 S'11
    20 Ts

    D3 S0 S1

     Another way is to use 3 of 2-1 Muxs:

    S0
    D0
    D0
    D1
    S0'
    S0’ S1
    S0 Y
    D1 D2
    S S1' S1
    S00 S1’ D3

    D2 S0

    S0' S1
    S0’
    We can use the same concept to
    make 3,4 or more I/Ps XORs
    D3
    S0
     4 I/P XOR:

    A'

    A
    A

    B'
    A' F=A+B+C+D
    C'
    D

    C
    C
    D'

    C'
    F = A.B’.C’.D’ + A’.B.C’.D’ + A’.B’.C.D’ + A.B.C.D’ + A.B.C.D’ + A.B.C’.D + A.B’.C.D

    In regular CMOS: 4 inverters + 64T = 72 T

    Warning: TGs can not be connected in series for more than 3 levels 

    If you need more than that, use CMOS inverters in between as buffers:

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