Slides4 Combinational Logic

COMBINATIONAL
LOGIC
Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS

Combinational vs. Sequential Logic
In Out
Logic Logic
In Out
Circuit Circuit
State
(a) Combinational (b) Sequential
Output = f(In) Output = f(In, Previous In)

Static CMOS Circuit
At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

Static CMOS
VDD
In1
In2 PUN PMOS Only
In3
F=G
In1
In2 PDN NMOS Only
In3
VSS
PUN and PDN are Dual Networks

NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0

Complementary CMOS Logic Style Construction (cont.)

Example Gate: NAND

Example Gate: NOR

Example Gate: COMPLEX CMOS GATE
VDD
B
A
C
D
OUT = D + A•(B+C)
A
D
B C

4-input NAND Gate
Vdd
VDD
In1 In2 In3 In4

Out
In1
In2
Out In3
In4
GND
In1 In2 In3 In4

Standard Cell Layout Methodology
metal1 VDD
Well
VSS
Routing Channel
signals
polysilicon

Two Versions of (a+b).c
VDD VDD
x
x
GND GND
a c b a b c
(a) Input order {a c b} (b) Input order {a b c}

Logic Graph
VDD
x
b PUN
j c c
a x i VDD
x
b j a
c
i PDN
GND
a b

Consistent Euler Path
x i
VDD
b a
j
GND
{ a b c}
Example: x = ab+cd
x x
b c b c
x V DD x V DD
a d a d
GND GND
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
V DD
GND
a b c d
(c) stick diagram for ordering {a b c d}

Properties of Complementary CMOS Gates
High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)

Properties of Complementary CMOS
Gates
High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)

Transistor Sizing
•for symmetrical response (dc, ac)
•for performance
V DD
B 12
A 6
Input Dependent
C 12
Focus on worst-case
D 6
F
A 2
D 1
B 2 C 2

Propagation Delay Analysis - The Switch
Model
RON
=
VDD VDD
V DD
Rp Rp Rp
Rp
A B B
A F
Rn Rp
F CL
B A
Rn
CL F
Rn Rn Rn
A CL
A B
A
(a) Inverter (b) 2-input NAND (c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)

What is the Value of Ron?

Numerical Examples of Resistances for 1.2µm
CMOS

Analysis of Propagation Delay
VDD 1. Assume Rn =Rp = resistance of minimum
Rp Rp sized NMOS inverter
A B
2. Determine “Worst Case Input” transition
F (Delay depends on input values)
Rn
CL 3. Example: tpLH for 2input NAND
B - Worst case when only ONE PMOS Pulls
up the output node
Rn
- For 2 PMOS devices in parallel, the
A
resistance is lower
t pLH = 0.69Rp CL
2-input NAND 4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
t pHL = 0.69(2R n)CL

Design for Worst Case
V DD
V DD
1 1 B 4
A A 2
B
F C 4
2 CL
B D 2
F
2 A 2
D 1
A
B 2C 2
Here it is assumed that Rp = Rn

Influence of Fan-In and Fan-Out
on Delay
VDD
A B C D Fan-Out: Number of Gates Connected

2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
D 2. Capacitance Increasing
(tpHL )
tp = a1 FI + a2 FI 2 + a3 FO

tp as a function of Fan-In
4.0
tpHL
3.0
tp (nsec)
2.0 quadratic tp
1.0
tpLH
linear
0.0
1 3 5 7 9
fan-in
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Fast Complex Gate - Design
Techniques
•Transistor Sizing:
As long as Fan-out Capacitance dominates
•Progressive Sizing:
Out
InN MN CL
M1 > M2 > M3 > MN
In3 C3
M3
Distributed RC-line
In2 M2 C2
In1 M1 C1
Can Reduce Delay with more than 30%!

Fast Complex Gate - Design Techniques
(2)
•Transistor Ordering
critical path critical path
CL CL
In3 M3 In1 M1
In2 M2 C2 C2
In2 M2
In1 M1 C1 C3
In3 M3
(a) (b)
(3)
•Improved Logic Design

(4)
• Buffering: Isolate Fan-in from Fan-out
CL CL

Example: Full Adder
V DD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A
Co B
Co = AB + Ci(A+B)
28 transistors
A Revised Adder Circuit
V DD
VDD V DD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate
Generate
A B B A B Ci A
24 transistors

Ratioed Logic
VDD VDD VDD
Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3
VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS

Ratioed Logic
VDD
• N transistors + Load
Resistive
Load • VOH = V DD
RL
• VOL = RPN
F RPN + RL
In1 • Assymetrical response

In2 PDN
In3 • Static power consumption
•tpL = 0.69 RL CL
VSS

Active Loads
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
depletion load NMOS pseudo-NMOS

Load Lines of Ratioed Gates
1
Current source
0.75
IL(Normalized)
Pseudo-NMOS
0.5
Depletion load
0.25
Resistive load
0
0.0 1.0 2.0 3.0 4.0 5.0
Vout (V)

Pseudo-NMOS
VDD
F
CL
A B C D
VOH = VDD (similar to complementary CMOS)
2
 VOL  kp 2
k n ( VDD – VTn )VOL – -------------  = ------ ( V DD – VTp )
 2  2
kp
V = (V – V ) 1 – 1 – ------ (assuming that V = V = V )
OL DD T k T Tn Tp
n
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Pseudo-NMOS NAND Gate
VDD
GND

Improved Loads
V DD
M1 M1 >> M2
Enable M2
CL
A B C D
Adaptive Load

Improved Loads (2)
VDD VDD
M1 M2
Out Out
A
A PDN1 PDN2
B
B
VSS VSS
Dual Cascode Voltage Switch Logic (DCVSL)

Example
Out
Out
B B B B
A A
XOR-NXOR gate

Pass-Transistor Logic
Switch Out A
Out
Inputs
Network B
B
•N transistors
• No static consumption

NMOS-only switch
C=5V C=5V
M2
A=5V A=5V B
Mn
B
CL M1
VB does not pull up to 5V, but 5V - VTN
Threshold voltage loss causes

static power consumption

Solution 1: Transmission Gate
C
C
A B A B
C
C
C=5V
A=5V
B
CL
C=0V

Resistance of Transmission Gate
30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
20000.0
R (Ohm)
Rp
10000.0
Req
0.0
0.0 1.0 2.0 3.0 4.0 5.0
Vout

Pass-Transistor Based Multiplexer
S S
VDD
V DD
S
A
M2
S F
M1
GND
In1 S S In2

Transmission Gate XOR
B
M2
A A
F
M1 M3/M4
B

Delay in Transmission Gate Networks
5 5 5 5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In
C C C C C
0 0 0 0
(a)
Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In
C C C C C
(b)
m
Req Req Req Req Req Req

In
C CC C C CC C
(c)
Elmore Delay (Chapter 8)
Vin R1 1 R2 2 Ri-1 i-1 Ri i RN N
C1 C2 Ci-1 Ci CN
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
N N N i
τN = ∑ Ri ∑ Cj = ∑ C i ∑ R j
i=1 j=i i=1 j=1

Delay Optimization

Transmission Gate Full Adder
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

(2) NMOS Only Logic: Level Restoring
Transistor
VDD
Level Restorer VDD
Mr
B
M2
X
A Mn Out
M1
• Advantage: Full Swing

• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Level Restoring Transistor
5.0 with
5.0
without
Vout (V)
3.0 3.0 without

with
VX
VB
1.0 1.0
-1.00 2 4 6 -1.00 2 4 6
t (nsec) t (nsec)
(a) Output node (b) Intermediate node X

Solution 3: Single Transistor Pass Gate with
VT=0
VDD
VDD
0V 5V
VDD 0V Out
5V
WATCH OUT FOR LEAKAGE CURRENTS

Complimentary Pass Transistor Logic
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network
B B B B B B
A A A
B F=AB B F=A+B A F=A ⊕ ΒÝ
A A A
(b)
B F=AB B F=A+B A F=A⊕ ΒÝ
AND/NAND OR/NOR EXOR/NEXOR

4 Input NAND in CPL

Dynamic Logic
V DD V DD
φ Mp φ Me
Out
In1
CL
In1 In2 PUN
In2 PDN In3
In3 Out
CL
φ Me φ Mp
φn network φp network
•Precharge
2 phase operation:
•Evaluation
Example
V DD
φ Mp
•N + 1 Transistors
Out
•Ratioless
•No Static Power Consumption

A •Noise Margins small (NML )
C
•Requires Clock
B
φ Me

Transient Response
6.0
φ Vout
4.0
EVALUATION PRECHARGE
Vout (Volt)
2.0
0.0
0.00e+00 2.00e-09 4.00e-09 6.00e-09
t (nsec)

Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
φ GND

Reliability Problems —
Charge Leakage
VDD
φ
φ Mp
Out
(1) CL
A t
Vout precharge evaluate
(2)
φ Me
t
(a) Leakage sources (b) Effect on waveforms
Minimum Clock Frequency: > 1 MHz

Charge Sharing (redistribution)
VDD case 1) if ∆V out < VTn
φ Mp
L out ( )
C V = C V t + C (V – V ( V ))
L DD a DD Tn X
Out
or
CL Ca
A Ma ∆V out = Vout ( t ) – V DD = –-------- ( V DD – V Tn ( V X ))
CL
X
Ca
B=0 Mb case 2) if ∆V out > VTn
C
 a 
Cb ∆Vout = –V DD ---------------------- 
φ Me Ca + CL 

Charge Redistribution - Solutions
VDD VDD
Mbl φ Mp Mbl φ
φ Mp
Out
Out
A Ma A Ma
B Mb B Mb
φ Me φ Me
(a) Static bleeder (b) Precharge of internal nodes

Clock Feedthrough
VDD
could potentially forward

φ Mp
bias the diode
Out
CL 5V
A Ma φ
X
Ca
B Mb overshoot
Cb out
φ Me

Clock Feedthrough and Charge Sharing
output without redistribution (Ma off)

feedthrough
out
4
φ
V (Volt)
internal node in PDN
0
0 1 2 3
t (nsec)

Cascading Dynamic Gates
VDD VDD V
φ
φ Mp φ Mp
In
Out1 Out2
Out1
In VTn
Out2 ∆V
φ Me φ Me t
(a) (b)
Only 0→ 1 Transitions allowed at inputs!

Domino Logic
VDD VDD
VDD
φ Mp φ Mp
Mr
Out1
Out2
In1 Static Inverter
In2 PDN In4 PDN with Level Restorer
In3
φ Me φ Me

Domino Logic - Characteristics
•Only non-inverting logic
•Very fast - Only 1->0 transitions at input of inverter

move VM upwards by increasing PMOS
• Adding level restorer reduces leakage and

charge redistribution problems
• Optimize inverter for fan-out

np-CMOS
VDD VDD
φ Mp φ Me
Out1
In1 PUN
In2 PDN In4
In3 Out2
φ Me
φ Mp
Only 1→ 0 transitions allowed at inputs of PUN

np CMOS Adder
V DD V DD
VDD V DD
φ φ S1
φ φ
C i1
A1 B1 B1 A1
B1 Ci1 A1
A1
B1
φ
φ φ Ci2
φ
VDD
VDD
V DD φ
φ
φ B0
A0 Ci1
A0 B0 C i0 A0
A0 B0 B0 C i0
S0
φ φ φ
C i0
Carry Path
Manchester Carry Chain Adder
V DD
Total Area:
225 µm × 48.6 µm
φ 0.5
P0 P1 P2 P3 P4
M0 M1 M2 M3 M4
3 2.5 2 1.5 1
C i,0 1.5 1 C o,4
3.5 3 2.5 2
G0 G1 G2 G3 G4
4 3.5 3 2.5 2
φ 1.5

CMOS Circuit Styles - Summary

Slides4 Combinational Logic

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COMBINATIONAL

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Combinational (b) Sequential

Output = f(In) Output = f(In, Previous In)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

At every point in time (except during the switching

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

PUN and PDN are Dual Networks

Transistors can be thought as a switch controlled by its gate signal

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS switch closes when switch control input is low

PMOS Transistors pass a “strong” 1 but a “weak” 0

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

In1 In2 In3 In4

In1 In2 In3 In4

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Input order {a c b} (b) Input order {a b c}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

High noise margins:

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

High noise margins:

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

(a) Inverter (b) 2-input NAND (c) 2-input NOR

(assuming that CL dominates!)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Here it is assumed that Rp = Rn

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

A B C D Fan-Out: Number of Gates Connected

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

critical path critical path

•Improved Logic Design

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

• Buffering: Isolate Fan-in from Fan-out

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

VDD VDD VDD

Resistive Depletion PMOS

VSS VSS VSS

Goal: to reduce the number of devices over complementary CMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

In1 • Assymetrical response

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

depletion load NMOS pseudo-NMOS

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

VOH = VDD (similar to complementary CMOS)

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995

Digital Integrated Circuits Combinational Logic © Prentice Hall 1995