Intel 815e Schematics

A B C D E
Intel® Pentium® III and FC-PGA Celeron™ Processor/815E Chipset

Universal Socket 370 Platform
4
Customer Reference Board Schematics 4
Revision 1.05 - Fab C

TITLE PAGE
COVER SHEET 1 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or
BLOCK DIAGRAM 2 otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
PGA370 PART 1 & 2 3,4
to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,
AGTL TERMINATION 5 or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
CLOCK GENERATOR 6 life saving, or life sustaining applications.
GMCH PART 1 & 2 7,8
Intel may make changes to specifications and product descriptions at any time, without notice.
DIMM 1 & 2 9 Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined."
DIMM 3 10 Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising
3 3
AGP 11 from future changes to them.
ICH PART 1 & 2 12,13
The Intel® 815E chipset may contain design defects or errors known as errata which may cause the product to deviate from
PCI 1 & 2 14 published specifications. Current characterized errata are available on request.
PCI 3 15
VIDEO BUS & CONNECTOR 16 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product
17 order.
FWH & UDMA100 IDE 1-2
USB 0-3 18 I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was
AC97 CODEC 19 developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips
AUDIO I/O 20 Electronics N.V. and North American Philips Corporation.
LPC I/O CONTROLLER & FDCL 21
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
WOR, WOL & 2S1P 22
KB, MS, GAME & IR 23 Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
2 2
FRONT PANEL & CNR 24 obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
ATX POWER & H/W MONITOR 25
VREGS: VDDQ, VCC1_8, AND VTT 26 Intel®, Pentium®, Pentium® III, Celeron™, are trademarks or registered trademarks of Intel Corporation or its subsidiaries in
VREGS: VCCVID, V1_8SB 27 the United States and other countries.
VREGS: DUALS, 3.3SB, 2.5, VCMOS 28
*Other brands and names may be claimed as the property of others.
SYSTEM CONFIGURATION 29
PU/PDR & UNUSED GATES 30 Copyright© 2001, Intel Corporation
DECOUPLING CAPACITORS 31
INTERNAL DEBUG HEADERS 32
**PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
THERMTRIP 33
1
Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1
Page Name: Title Page

Last Revised: Page: Thursday, November 29, 2001
Doc: Thursday, November 29, 2001
Revision:
Platform Applications Engineering
1.05
1900 Prairie City Road
Page No:
Folsom, CA 95630
1 of 33
A B C D E
A B C D E
BLOCK DIAGRAM
VRM 370-PIN SOCKET PROCESSOR CLOCK

4 4
ADDR
CTRL
DATA
GTL BUS
ADDR
CTRL
DATA
AGP
Connector
3 DIMM
GMCH Modules
Digital Video
3 3
Out Connector
PCI CONN 1
PCI CONN 2
PCI CONN3
IDE Primary PCI CNTRL
UDMA/100
IDE Secondary
PCI ADDR/DATA
ICH2
USB PORT 1-4 USB
Note: PCI3
Connector is
not populated
2 on the board 2
FirmWare Hub
CNR
AC’97 LINK
Connector
SIO Audio
Codec
1
Page Name: Block Diagram

Keyboard Revision:
Floppy Game Port Serial 1 Serial 2 Parallel Platform Applications Engineering
1.05
Mouse 1900 Prairie City Road
Page No:
Folsom, CA 95630
2 of 33
A B C D E
5 4 3 2 1
VTT VCCVID
HA#[3..31]
HA#[3..31] 7
HD#[0..63]
HD#[0..63] 7
AM12
AM16
AM20
AM24
AM28
AM32
AH32
AH36
AD32
AH24
AK34
AB34
AA37
AF34
AJ13
AJ17
AJ21
AJ25
AJ29
AM4
AM8
M32
AK2
AB2
AE5
AA5
AF2
D20
D24
D28
R32
H32
R36
H36
D36
D32
B26
B10
E13
B14
E17
B18
B30
V32
X34
P34
K34
B34
B22
V36
K32
Y35
AJ9
AJ5
F22
F26
F30
Z32
T34
F34
F14
W5
C3
N5
D6
P2
K2
E5
S5
B6
E9
U3A
T2
F4
F2
J5
D HD#0 HA#3 D
W1 AK8
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
VCCVID
HD#1 HD#0 HA#3 HA#4
T4 HD#1 HA#4 AH12
HD#2 N1 AH8 HA#5
HD#3 HD#2 HA#5 HA#6
M6 HD#3 HA#6 AN9
HD#4 U1 AL15 HA#7
HD#5 HD#4 HA#7 HA#8
S3 HD#5 HA#8 AH10
HD#6 T6 AL9 HA#9
HD#7 HD#6 HA#9 HA#10
J1 HD#7 HA#10 AH6
HD#8 S1 AK10 HA#11
HD#9 HD#8 HA#11 HA#12
P6 HD#9 HA#12 AN5
HD#10 Q3 AL7 HA#13
HD#11 HD#10 HA#13 HA#14
M4 HD#11 HA#14 AK14
HD#12 Q1 AL5 HA#15
HD#13 HD#12 HA#15 HA#16
L1 HD#13 HA#16 AN7
HD#14 N3 AE1 HA#17 VCC3_3
HD#15 HD#14 HA#17 HA#18
U3 HD#15 HA#18 Z6
HD#16 H4 AG3 HA#19
HD#17 HD#16 HA#19 HA#20
R4 HD#17 HA#20 AC3
HD#18 P4 AJ1 HA#21
HD#18 HA#21
2
4
6
8
HD#19 H6 AE3 HA#22
HD#20 HD#19 HA#22 HA#23 RP3
L3 HD#20 HA#23 AB6
HD#21 G1 AB4 HA#24 R371
HD#22 HD#21 HA#24 HA#25 10K/8P4R
F8 HD#22 HA#25 AF6
C
HD#23 G3 Y3 HA#26 10K C
HD#24 HD#23 HA#26 HA#27
K6 HD#24 HA#27 AA1
HD#25 E3 AK6 HA#28
HD#26 HD#25 HA#28 HA#29
1
3
5
7
E1 HD#26 HA#29 Z4
HD#27 F12 AA3 HA#30
HD#28 HD#27 HA#30 HA#31
A5 HD#28 HA#31 AD4
HD#29 A3 X6
HD#30 HD#29 HA#32 R372 1k
J3 HD#30 HA#33 AC1
HD#31 C5 W3
HD#32 HD#31 HA#34
F6 AF4
HD#33
HD#34
C1
C7
HD#32
HD#33 370 - Pin Socket Part 1 HA#35
AL35 CPU_VID0
RP4
HD#34 VID0 JPR_VID0 29,32
HD#35 B2 AM36CPU_VID1 1 2 JPR_VID1 29,32
HD#36 HD#35 VID1
C9 HD#36 VID2 AL37 CPU_VID2 3 4 JPR_VID2 29,32
HD#37 A9 AJ37 CPU_VID3 5 6 JPR_VID3 29,32
HD#38 HD#37 VID3
D8 HD#38 GND/VID4 AK36CPU_VID4 7 8 JPR_VID4 29,32
HD#39 D10 AK18
HD#39 REQ#0 HREQ#0 7
HD#40 C15 AH16 1K/8P4R
HD#41 D14 AH18
HD#42 D12 AL19
HD#43 A7 AL17
HD#44 A11 C33
HD#45 HD#44 DEP0#
C11 HD#45 DEP1# C31
HD#46 A21 A33
HD#47 HD#46 DEP2#
B A15 HD#47 DEP3# A31 B
HD#48 A17 E31
HD#49 HD#48 DEP4#
C13 HD#49 DEP5# C29
HD#50 C25 E29 VTT
HD#51 HD#50 DEP6#
A13 HD#51 DEP7# A29
HD#52 D16
HD#53 HD#52
A23 HD#53 VTT1_5 AH20
HD#54 C21 AK16
HD#55 HD#54 VTT1_5
C19 HD#55 VTT1_5 AL21
HD#56 C27 AN11
HD#57 HD#56 VTT1_5
A19 HD#57 VTT1_5 AN15
HD#58 C23 G35
HD#59 HD#58 VTT1_5
C17 HD#59 VTT1_5 AL13
HD#60 A25 U37
HD#61 HD#60 VTT1_5
A27 HD#61 VTT1_5 U35
HD#62 E25 S37
HD#63 HD#62 VTT1_5
F16 HD#63 VTT1_5 S33
VTT1_5 E23
7 RS#0 AH26 RS#0 VTT1_5 AN21
AH22 AA35
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
7 RS#1 RS#1 VTT1_5
7 RS#2 AK28 RS#2 VTT1_5 AA33
AM34
AM10
AM14
AM18
AM22
AM26
AM30
AH34
AD34
AC33
AB32
AF32
AJ11
AJ15
AJ19
AJ23
AJ27
AM6
AG5
AH2
AD2
AC5
M34
D18
D22
D26
D30
R34
H34
D34
AL3
E11
B12
E15
B16
E19
B20
B24
B28
X32
P32
B32
V34
X36
P36
K36
A37
Y37
AJ7
F20
F24
F28
T32
F32
Z34
T36
F36
M2
Q5
G5
H2
D2
U5
D4
V2
Y5
B4
E7
B8
Z2
L5
Socket 370_9 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
A A
Page Name: 370-pin Socket Part 1

Revision:
1.05
Page No:
Folsom, CA 95630
3 of 33
5 4 3 2 1
5 4 3 2 1
BSEL#1 BSEL#0 FSB

0 0 66M
No-stuff R199 - see p.33. 0 1 100M
1 0 rsvd
Stuff either R5 or R415. See p33. 1 1 133M
VTT VCC2_5 VCMOS
Place near AB36 R338 CMOSREF generation circuit

D R314 330 R373 R199 R15 R14 R13 R6 R5 R7 R8 V3SB V3SB D
R9 BC1 75 1%
CMOSREF
1K 1.8k 150 150 330 39 39 150 330 VTT R2 R1 R3 R4 R339 BC228
680 0.1UF GTLREFA
ITP_VTT 150 150 1K 1K 150 1% 0.1uF
J2 CMOSREF
AD36
AB36
AK12
AK22
2 1
AD6
E33
Z36
F18
2 1
R6
K4
V6
R315 0 ITP_DBRESET 4 3
25 DBRESET# 4 3 U3B
6 6 5 5
8 7 AN35 AH14
V1_5
V2_5
VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7
V_CMOS
8 7 TDI BNR# BNR# 7
10 10 9 9 AN37 TDO BPRI# AN17 BPRI# 7
12 12 11 11 AN33 TRST# TRDY# AN25 HTRDY# 7
14 13 R316 0 AL33 AN19
14 13 TCK DEFER# DEFER# 7
16 15 R317 0 AK32 AK20
16 15 TMS LOCK# HLOCK# 7
18 18 17 17 DRDY# AN27 DRDY# 7
20 20 19 19 J37 PREQ# HITM# AL23 HITM# 7
22 21 R318 243,1% A35 AL25
22 21 PRDY# HIT# HIT# 7
24 24 23 23 DBSY# AL27 DBSY# 7
26 25 VTT G33 AN31
26 25 BP2# ADS# HADS# 7
28 28 27 27 E37 BP3# FLUSH# AE37FLUSH#
30 29 R374 C35
6 ITPCLK 30 29 BPM0#
E35 AJ33
C
XHEADER_15X2 14 N33
BPM1#
370 - Pin Socket BSEL0#
BSEL1# AJ31
AK30
BSEL#0
BSEL#1
29,32
29,32
C
RSRVD6 RSRVD12/JBSEL1#
N35 RSRVD7
NCHCTRLP N37 AN29
33 N6395403
Q33
Q35
RSRVD8
RSRVD9 Part2 BR0#
THRMDP AL31
AL29
BR0#
VTIN2
5
21,25
RSRVD10 THRMDN THRMDN 21,25
5 ITPRDY# Q37 RSRVD11 THERMTRIP# AH28
THERMTRIP# 33
AM2 RSRVD13 A20M# AE33 A20M# 12
ITP_CPURESET F10 AG35
RSRVD15 STPCLK# STPCLK# 12
VTT VTT W35 AH30 Tua
RSRVD16 SLP# CPUSLP# 12
Y1 RSRVD17 SMI# AJ35 SMI# 12
R2 RSRVD18 LINT0/INTR M36 INTR 12
R319 R33 G37 L37
RSRVD19 LINT1/NMI NMI 12
L33 AG33 VCC5
RSRVD20 INIT# INIT# 12,17
AL1 RSRVD21 FERR# AC35 FERR# 12
R340 AG37
IGNNE# IGNNE# 12
243,1% 90.9,1% X2 AE35 R341
1k RESVD21(BR1#) IERR# VCCVID 2.2k
R342 1k DYN_OE AN3 W33 PLL1 33uF (C size) L2
26 VTTPWRGD DYN_OE PLL1 PLL2
AK4 VTTPWRGD PLL2 U33 TUAL5 6,7
C6 VCC5
+
12 APICD0 J35 PICD0
L35 AC37 4.7UH/SMD-0805 Q25
12 APICD1 PICD1 RSP# 2N7002
B 6 APICCLK_CPU J33 PICCLK AP0# AL11 B
W37 AN13 VTT R343
6 CPUHCLK BCLK AP1# 2.2k
Y33 CLKREF RP# AN23
AK26 R344
12,33 CPU_PWGD PWRGOOD
7,33 CPURST# AH4 RESET# BINIT# B36 TUAL5#
RESET2# X4 AK24 Debug only!
R345 1k RESET2# AERR# R375 0 1k Q26
AJ3 RSVD - NC BERR# V4
AG1_VTT/NC AG1 AF36 TUALDET 2N3904
R406 VTT VCC2_5 EDGCTRL/VRSEL TUALDET SLEWCNTR
SLEWCNTR E27
C37 S35 RTTCNTR
1k CPUPRES# RTTCNTR
VCOREDET E21
PR4
Rds_on approx. 100 Socket 370_9
Stuff resistor mOhm @5Vgs 150,1% R275 Do Not stuff C Debug only! Do NOT place
only on non-UMB Place Site w/in 0.5" PR1 PR5 JP6 jumper before removing
Q27 of clock pin (W37) Debug sites only. GTLREF Generation Circuit
platforms. R375
FDN335N PR6 MC7 BC7 C3
22 FB30BEAD VTT Use 0603 Packages and distribute 56,%1 110,%1 JUMPER
4.7UF 0.1UF X18PF 1 2 GTLREF Inputs ( 1 cap for every 2 inputs )
6,7,26 TUAL5 150,1% C12 within 500 mils of processor
C163
R346 10PF PR7
0.1uF GTLREFA 32
1k
A 75,1%
Document: Intel(R) 815E Chipset Universal Socket 370 CRB A
GTLREFA Page Name: 370-pin Socket Part 2
GTLREF 7,32
R330 X0
PR8 Do not stuff R330 Last Revised: Page: Thursday, November 29, 2001
BC18 BC17 BC16 BC12 GTLREFA to CPU. Doc: Thursday, November 29, 2001
GTLREF to GMCH. Revision:
150,1% 0.1UF 0.1UF 0.1UF 0.1UF Platform Applications Engineering
1.05
Page No:
Folsom, CA 95630
4 of 33
5 4 3 2 1
5 4 3 2 1
D D
VTT
R23 56
BR0# 4
R12 150
ITPRDY# 4
C C
VTT
MC23 MC22 BC34 BC35 BC36 BC37 BC38 BC24 BC23 BC5 BC14 BC22 BC9 BC15 BC2 BC13 BC3
4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
VTT Do not populate in assembly - debug sites only.

Debug cap sites - place near processor
C164
B 820uF B
VTT Decoupling
A
Page Name: VTT Decoupling

Revision:
1.05
Page No:
Folsom, CA 95630
5 of 33
5 4 3 2 1
A B C D E
PFB4 PFB2
VCC_CLOCK 1 2 AV3 USBV3 1 2
VCC_CLOCK
BEAD BC56 BC55 BC32 BC31 MC18 BEAD
0.1UF 0.01UF R249 8.2K 0.01UF 0.1UF 4.7UF
PFB5 PFB1
VCC_CLOCK 1 2 PCIV3 MEMV3 1 2
VCC_CLOCK
4 MC28 MC29 BC62 BC61 BC57 BC58 BC59 BC60 BC226 BC227 BC28 BC27 BC29 BC30 BC33 BC21 BC63 BC64 MC20 MC19 4
BEAD BEAD
4.7UF 4.7UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 0.01UF 0.1UF 4.7UF 4.7UF R347
0
PFB11 APICCLK_CPU 4
1 2 L_VCC2_5
VCC2_5
R348
TUAL5 4,7,26
BEAD MC21 BC25 BC26 Q28
130
56
14
20
25
31
35
40
44
49
2
5
9
4.7UF 0.1UF 0.01UF C35 U6
18PF
VDDL
VDDL
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDA
2N7002
Y3 R320 33
ITPCLK 4
6 54 R46 33
X1 CPUCLK_0 CPUHCLK 4
29 FMOD1 14.318MHZ 53 R45 33
CPUCLK_1 GMCHHCLK 7
C33 7 1 R57 33
R60 10 18PF X2 IOAPIC R58 33
4 REF0 APICCLK_ICH 12
13 ICH_CLK14 51 8 7 MEMCLK0
13 ICH_3V66 R64 33 SDRAM0 MEMCLK1
10 3V66-0 SDRAM1 50 6 5
8 GMCH_3V66 R65 33 11 47 4 3 MEMCLK2
11 AGPCLK_CONN R66 33 3V66-1 SDRAM2 MEMCLK3
12 3V66-2 SDRAM3 46 2 1
RN19 22/8P4R
3
12 PCLK_0/ICH R67 33 15 45 8 7 MEMCLK4 3
R290 33 PCICLK0 SDRAM4 MEMCLK5
16 PCICLK1 SDRAM5 42 6 5
41 4 3 MEMCLK6
29 FMOD0 SDRAM6 MEMCLK7
18 FS0 SDRAM7 38 2 1
28 RN20 22/8P4R
FS1 R50 22 MEMCLK8
SDRAM8 37
13,21,28 SLP_S3# R72 10 21 36 R51 22 MEMCLK9
32 R_SMBCLK PD# SDRAM9 R62 22 MEMCLK10
22 SCLK SDRAM10 33
32 R_SMBDATA 23 32 R63 22 MEMCLK11
SDATA SDRAM11
29 R44 22
SDRAM12 DCLK_WR 7
C29 C39 C40 C41 C42
X10PF X10PF X10PF X10PF X10PF 26 R48 33

48MHZ_0 USBCLK 13
27 R49 33
48MHZ_1 DOTCLK 8
GNDL
GNDL
ICS9250-28 R47 33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SIO_CLK24 21
VCC3_3
MEMCLK[0..7]
MEMCLK[0..7] 9
55
13
17
19
24
30
34
39
43
48
52
Q29 C19 C21 C20 C133 C25 C24 C28 C30
8
FDN359AN MEMCLK[8..11]
26 VTTPWRGD12 X10PF X10PF X10PF X10PF X10PF X10PF X10PF X10PF MEMCLK[8..11] 10
2 VCC_CLOCK 2
PFB12
Clock power gate VCC3_3 1 2
MC66 BC221 BC222 U29

BEAD
Rds_on = 100 mOhm. R302 R303 4
4.7UF 0.1UF 0.01UF VDD RN34
13 VDD
10K 10K 2 7 8
CLKA1 PCLK_1 14
CLKA2 3 5 6 PCLK_2 14
9 FS1 CLKA3 14 3 4 PCLK_3 15
8 FS2 CLKA4 15 1 2 PCLK_7 21
PCLK_REF 1 6
REF CLKB1 33/8P4R
CLKB2 7
MEMCLK0 MEMCLK4 MEMCLK8 10
MEMCLK1 MEMCLK5 MEMCLK9 CLKB3 R277 33
CLKB4 11 PCLK_8 17
MEMCLK2 MEMCLK6 MEMCLK10
MEMCLK3 MEMCLK7 MEMCLK11 16 R312 X33
CLKOUT
5 GND
12 GND
2
4
6
8
CN6
2
4
6
8
2
4
6
8
2
4
6
8
ICS9112B-17 C120 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
1 CN4 CN5 X10P/8P4C 1
2
4
6
8
2
4
6
8
C34 C31 C23 C22 X10PF

Ensure that the buffer used will disable Page Name: Clock Generator
1
3
5
7
X10P/8P4C X10P/8P4C
X10PF X10PF X10PF X10PF its PLL and tristate outputs when no Page: Thursday, November 29, 2001
Last Revised:
1
3
5
7
1
3
5
7
refclk is present; otherwise, must gate C132 Doc: Thursday, November 29, 2001
1
3
5
7
power here, too. X18PF
Revision:
1
3
5
7
1
3
5
7

1.05
Page No:
Folsom, CA 95630
6 of 33
A B C D E
5 4 3 2 1
VTT Debug sites only. SM_MAC#[4..7]

10 SM_MAC#[4..7]
1 2 VTT
SM_MAB#[4..7] SM_MD[0..63] VCC3SBY
9 SM_MAB#[4..7] SM_MD[0..63] 9,10
FB31BEAD C168 PR42
R61 U7A HD#[0..63] SM_MAA[0..12]
HD#[0..63] 3 9,10 SM_MAA[0..12] U7B
0.1uF 63.4 1%
Place close AA1 HD#0 SM_MAA0 D13 D23 SM_MD0 BC188 BC190 BC191 BC189
HD#0 HD#1 SM_MAA1 SMAA0 SMD0 SM_MD1
to GMCH
HD#1 AB2 B16 SMAA1 SMD1 C23
90.9,1% AF2 HD#2 SM_MAA2 F12 D22 SM_MD2 X0.1UF X0.1UF X0.1UF X0.1UF
32 GTLREF HD#2 HD#3 SM_MAA3 RN37 SMAA2 SMD2 SM_MD3
HD#3 AD4 A16 SMAA3 SMD3 F21
PR43 AB1 HD#4 SM_MAA4 1 2 B12 E21 SM_MD4
D BC72 BC73 HD#4 HD#5 SM_MAA5 SMAA4 SMD4 SM_MD5 D
U6 GTLREFA HD#5 AB3 3 4 A12 SMAA5 SMD5 G20
AA10 AA3 HD#6 SM_MAA6 5 6 C11 F20 SM_MD6
GTLREFB HD#6 SMAA6 SMD6
150,1% 0.1UF 0.1UF
HD#7 AC4 HD#7 SM_MAA7 7 8 A11 SMAA7 SMD7 D20 SM_MD7 Backside decouping , should be
AC1 HD#8 SM_MAA8 D12 F19 SM_MD8
HD#8 HD#9 SM_MAA9 SMAA8 SMD8 SM_MD9
placed under chipset memory signal
6 GMCHHCLK AA7 HCLK HD#9 AF3 C13 SMAA9 SMD9 E19
H3 AD1 HD#10 SM_MAA10 10/8P4R E11 D19 SM_MD10 field
16,17,21,30 PCIRST# RESET# HD#10 SMAA10 SMD10
AA5 AE3 HD#11 SM_MAA11 A13 E18 SM_MD11
4,33 CPURST# CPURST# HD#11 SMAA11 SMD11
L4 AD2 HD#12 SM_MAA12 B7 B18 SM_MD12
4 HLOCK# HLOCK# HD#12 SMAA12 SMD12
M3 AD3 HD#13 RN38 10/8P4R F18 SM_MD13
4 DEFER# DEFER# HD#13 SMD13
G1 AF1 HD#14 SM_MAB#4 1 2 B15 G18 SM_MD14
HADS# ADS# HD#14 SMAB#4 SMD14
N4 AA4 HD#15 SM_MAB#5 3 4 A15 D17 SM_MD15
4 BNR# BNR# HD#15 SMAB#5 SMD15
M5 AD6 HD#16 SM_MAB#6 5 6 C14 A3 SM_MD16
4 BPRI# BPRI# HD#16 SMAB#6 SMD16
J3 AC3 HD#17 SM_MAB#7 7 8 A14 A1 SM_MD17
4 DBSY# DBSY# HD#17 SMAB#7 SMD17
R407 J1 AE1 HD#18 C1 SM_MD18
Place 4 DRDY# DRDY# HD#18 SMD18
K1 AB6 HD#19 SM_MAC#4 1 2 B10 F2 SM_MD19 VDDQ
56 near GMCH 4 HIT# HIT# HD#19 SMAC4 SMD19
L3 AF4 HD#20 SM_MAC#5 3 4 A10 G3 SM_MD20
4 HITM# HITM# HD#20 SMAC5 SMD20
K3 AE5 HD#21 SM_MAC#6 5 6 C10 D6 SM_MD21
4 HTRDY# HTRDY# HD#21 SMAC6 SMD21
VTT AC8 HD#22 SM_MAC#7 7 8 A9 C5 SM_MD22
HA#[3..31] HA#3 HD#22 HD#23 RN36 10/8P4R SMAC7 SMD22 SM_MD23 BC192 BC193 BC194 BC195
3 HA#[3..31] R4 HA#3 HD#23 AB5 SMD23 B4
HA#4 P1 AF5 HD#24 B13 D4 SM_MD24
HA#4 HD#24 9,10 SM_BS0 SBS0 SMD24
HA#5 T2 AC6 HD#25 D11 C2 SM_MD25 X0.1UF X0.1UF X0.1UF X0.1UF
HA#5 HD#25 9,10 SM_BS1 SBS1 SMD25
HA#6 R3 AF6 HD#26 D3 SM_MD26
HA#7 HA#6 HD#26 HD#27 SM_CSA#0 SMD26 SM_MD27
N5 HA#7 HD#27 AD11 D15 SCSA#0 SMD27 E4
C
HA#8 P5 AF8 HD#28 SM_CSA#1 A17 F5 SM_MD28 C
HA#9 HA#8 HD#28 HD#29 SM_CSA#2 SCSA#1 SMD28 SM_MD29
R1 HA#9 HD#29 AD8 D14 SCSA#2 SMD29 G4
HA#10 U1 HA#10 HD#30 AD5 HD#30 SM_CSA#3 E14 SCSA#3 SMD30 J6 SM_MD30 Backside decouping , should be
HA#11 P2 AB7 HD#31 SM_CSA#4 E13 K5 SM_MD31
HA#12 HA#11 HD#31 HD#32 SM_CSA#5 SCSA#4 SMD31 SM_MD32
placed under chipset AGP signal
T1 HA#12 HD#32 AF7 B17 SCSA#5 SMD32 A26
HA#13 T3 AD7 HD#33 A25 SM_MD33 field
HA#14 HA#13 HD#33 HD#34 SM_CSB#0 SMD33 SM_MD34
P3 HA#14 HD#34 AB8 F9 SCSB#0 SMD34 B24
HA#15 T5 AE7 HD#35 SM_CSB#1 F8 A24 SM_MD35
HA#16 HA#15 HD#35 HD#36 SM_CSB#2 SCSB#1 SMD35 SM_MD36
R5 HA#16 HD#36 AE9 D10 SCSB#2 SMD36 B23
HA#17 V5 AB9 HD#37 SM_CSB#3 D9 A23 SM_MD37
HA#18 HA#17 HD#37 HD#38 SM_CSB#4 SCSB#3 SMD37 SM_MD38 SM_MAA12
Y2 HA#18 HD#38 AF9 B9 SCSB#4 SMD38 C22
HA#19 V3 AD10 HD#39 SM_CSB#5 A8 A22 SM_MD39
HA#20 HA#19 HD#39 HD#40 SCSB#5 SMD39 SM_MD40 R349
W1 HA#20 HD#40 AF12 SMD40 D21
HA#21 U4 AB11 HD#41 C16 B21 SM_MD41 10k
HA#21 HD#41 9,10 SM_RAS# SRAS# SMD41
HA#22 V2 AB10 HD#42 D18 A21 SM_MD42
HA#22 HD#42 9,10 SM_CAS# SCAS# SMD42
HA#23 W3 AD9 HD#43 E16 C20 SM_MD43
HA#23 HD#43 9,10 SM_WE# SWE# SMD43
HA#24 W4 AC10 HD#44 B20 SM_MD44
HA#25 HA#24 HD#44 HD#45 SM_CKE0 SMD44 SM_MD45 Q30
U5 HA#25 HD#45 AF10 D8 SCKE0 SMD45 A20
HA#26 Y5 AD14 HD#46 SM_CKE1 E8 C19 SM_MD46 2N7002
HA#26 HD#46 SCKE1 SMD46 4,6,26 TUAL5
HA#27 Y3 AD12 HD#47 SM_CKE2 E9 A19 SM_MD47
HA#28 HA#27 HD#47 HD#48 SM_CKE3 SCKE2 SMD47 SM_MD48
U3 HA#28 HD#48 AB12 D7 SCKE3 SMD48 A4
HA#29 Y1 AE11 HD#49 SM_CKE4 C8 A2 SM_MD49 SM_WE# R90 8.2K
HA#29 HD#49 SCKE4 SMD49 R_BSEL#0 29
HA#30 W5 AE15 HD#50 SM_CKE5 C7 B1 SM_MD50
HA#31 HA#30 HD#50 HD#51 SCKE5 SMD50 SM_MD51 SM_CAS# R89 8.2K
V1 HA#31 HD#51 AF11 SMD51 E1 R_REFCLK 29
B AF13 HD#52 F7 G2 SM_MD52 B
HD#52 6 DCLK_WR SCLK SMD52
HREQ#0 M1 AB14 HD#53 G10 E6 SM_MD53 SM_MAA9 R88 10K
3 HREQ#0 HREQ#1 HREQ#0 HD#53 HD#54 SM_DQM[0..7] RESVD SMD53 SM_MD54
3 HREQ#1 N1 HREQ#1 HD#54 AF14 9,10 SM_DQM[0..7] SMD54 D5
HREQ#2 M2 AB13 HD#55 SM_DQM0 D16 C4 SM_MD55 R68 X10K SM_MAA10
3 HREQ#2 HREQ#3 HREQ#2 HD#55 HD#56 SM_DQM1 SDQM0 SMD55 SM_MD56
3 HREQ#3 L5 HREQ#3 HD#56 AB15 F15 SDQM1 SMD56 B3
HREQ#4 N3 AE13 HD#57 SM_DQM2 A7 D2 SM_MD57
3 HREQ#4 HREQ#4 HD#57 HD#58 SM_DQM3 SDQM2 SMD57 SM_MD58 R77 X10K SM_RAS#
HD#58 AC14 A6 SDQM3 SMD58 E3
RS#0 K2 AD13 HD#59 SM_DQM4 A18 F4 SM_MD59
3 RS#0 RS#1 RS#0 HD#59 HD#60 SM_DQM5 SDQM4 SMD59 SM_MD60
L1 RS#1 HD#60 AD15 C17 SDQM5 SMD60 F6
3 RS#1 RS#2 HD#61 SM_DQM6 SM_MD61
3 RS#2 H1 RS#2 HD#61 AF16 B6 SDQM6 SMD61 G5
HD#62 AF15 HD#62 SM_DQM7 A5 SDQM7 SMD62 H4 SM_MD62 SM_WE# Host Freq : HI=100 LO=66
HD#63 AC12 HD#63
SMD63 J4 SM_MD63 SM_MAA9 FSB P-MOS Kicker : HI=NON-Cu LO=Cu
VCC3SBY PR9 40.2,1% G7 SM_CAS# Host Freq : HI=133 LO=100/66
Do Not Stuff C SRCOMP
SBA7 LM FREQ : HI=133 LO=100
Place Site w/in C38 82815 GMCH SM_BS0
0.5" of clock X18PF Host Interface C36 SM_BS1 SM/LM muxing strap , active low
ball(v6)
SYSTEM MEMORY SM_MAA10 ALLZ : LO=ALLZ HI=Normal
22PF SM_MAA11 IOQ depth : HI=4 LO=1
SM_MAA12 LO = Future 0.13u Socket 370 processors
HI = Pentium(R) III Processor or Intel(R)
Celeron(tm) Processor w/CPUID = 068Xh
SM_RAS# XOR chain : LO=XOR HI=Normal
SM_CKE[0..3]
9 SM_CKE[0..3]
A SM_CKE[4..5]
10 SM_CKE[4..5]
SM_CSA#[0..3]
Page Name: GMCH Part 1
9 SM_CSA#[0..3]
SM_CSA#[4..5] Doc: Thursday, November 29, 2001
10 SM_CSA#[4..5]
SM_CSB#[0..3]
Revision:
9 SM_CSB#[0..3] Platform Applications Engineering
SM_CSB#[4..5]
1.05
10 SM_CSB#[4..5] 1900 Prairie City Road
Page No:
Folsom, CA 95630
7 of 33
5 4 3 2 1
5 4 3 2 1
SBA[0..7]
SBA[0..7] 11
HL[0..10]
HL[0..10] 12
VDDQ VCC3SBY VCC1_8
FTD[0..11]
FTD[0..11] 16
GAD[0..31]
11 GAD[0..31] U7C U7D U7E
D GAD0 FTD0 D
K26 GAD0/LDQM0 LTVDATA0 AD16 W6 VCC_1.8 GND AB4 P11 GND GND N2
GAD1 J22 AF17 FTD1 Y9 E7 P12 N6
GAD2 GAD1/LMD4 LTVDATA1 FTD2 VCC1_8 VCC_1.8 GND GND GND
K25 GAD2/LMD7 LTVDATA2 AE17 Y18 VCC_1.8 GND AC2 P13 GND GND N11
GAD3 J21 AD17 FTD3 AA6 AC5 P14 N12
GAD4 GAD3/LMD3 LTVDATA3 FTD4 L6 22nH VCC_1.8 GND GND GND
L24 GAD4/LMD6 LTVDATA4 AF18 AA8 VCC_1.8 GND AC7 P15 GND GND N13
GAD5 J20 AD18 FTD5 AA11 AC9 P16 N14
GAD6 GAD5/LMD2 LTVDATA5 FTD6 VCC_1.8 GND GND GND
L26 GAD6/LMD5 LTVDATA6 AF20 AA13 VCC_1.8 GND AC11 R2 GND GND N15
GAD7 K23 AD20 FTD7 C169 C170 C171 AA15 AC13 R6 N16
GAD8 GAD7/LMD1 LTVDATA7 FTD8 VCC_1.8 GND GND GND
K22 GAD8/LMD0 LTVDATA8 AC20 AA17 VCC_1.8 GND AC15 R11 GND GND N23
GAD9 M25 AF21 FTD9 33uF 0.1uF 0.01uF AA19 AC17 R12 AA23
GAD10 GAD9/LMA4 LTVDATA9 FTD10 VCC_1.8 GND GND GND
M24 GAD10/LDQM1 LTVDATA10 AE21 AB16 VCC_1.8 GND AC19 R13 GND GND F16
GAD11 M26 AD21 FTD11 AB20 AC21 R14 F25
GAD12 GAD11/LMA2 LTVDATA11 VCC_1.8 GND GND GND
M21 GAD12/LMD8 BLANK# AB19 FTBLNK# 16 AC22 VCC_1.8 GND AC25 R15 GND GND G9
GAD13 N24 AC18 AD19 AE2 R16 G17
GAD13/LMA5 TVCLKIN/SL_STALL SL_STALL 16 VCC_1.8 GND GND GND
GAD14 N22 AE19 C25 AE4 R23 G21
GAD14/LMD9 CLKOUT0 FTCLK0 16 VCC_1.8 GND GND GND
GAD15 N26 AF19 E24 AE6 R25 G23
GAD15/LMA1 CLKOUT1 FTCLK1 16 VCC_1.8 GND GND GND
GAD16 T26 AC16 F23 AE8 T4 P24
GAD/16/LMA8 TVVSYNC FTVSYNC 16 VCC_1.8 GND GND GND
GAD17 T22 AB17 G22 AE10 T11 H6
GAD17/LMD14 TVHSYNC FTHSYNC 16 VCC_1.8 GND GND GND
GAD18 U24 J7 AE12 T12 H22
GAD19 GAD18/LMA11 VCC_1.8 GND GND GND
T23 GAD19/LMD15 LTVCK AB21 3VFTSCL 16 K6 VCC_1.8 GND AE14 T13 GND GND J2
GAD20 U26 AA20 M6 AE16 T14 J5
GAD20/LMA9 LTVDA 3VFTSDA 16 VCC_1.8 GND GND GND
GAD21 T24 P6 AE18 T15 J23
GAD22 GAD21/LMD16 VCC_1.8 GND GND GND
V24 GAD22/LCS# T6 VCC_1.8 GND AE20 T16 GND GND J25
C
GAD23 U21 V7 B26 L15 K4 C
GAD24 GAD23/LMD17 VCC_1.8 GND GND GND
V25 GAD24/LCKE DDDA AA18 3VDDCDA 16 G26 VCC_1.8 GND C3 L16 GND GND K7
GAD25 V21 AB18 C6 L22 K21
GAD25/LMD18 DDCK 3VDDCCL 16 GND GND GND
GAD26 V26 AA21 C9 M4 L2
GAD27 GAD26/LCAS# R251 22 VCC1_8 GND GND GND
W21 GAD27/LMD19 DCLKREF AE24 DOTCLK 6 Y7 VCC1_8 GND C12 M11 GND GND L6
GAD28 W24 Y20 C58 E23 C15 M12 L11
GAD29 GAD28/LTCLK1 IWASTE VCC1_8 GND GND GND
W22 GAD29/LMD20 IREF AD23 AF26 VCC1_8 GND C18 M13 GND GND L12
GAD30 W26 10PF AF25 C21 M14 L13
GAD31 GAD30/LTCLK0 VCC1_8 GND GND GND
Y21 GAD31/LMD21 VSYNC AF22 CRT_VSYNC 16 GND C24 M15 GND GND L14
HSYNC AF23 CRT_HSYNC 16 B2 VCC3SBY GND D1 M16 GND GND AA25
H23 AD22 Do Not Stuff C B5 E5 L25 P4
11 GCBE#0 GCBE#0/LMA3 RED VID_RED 16 Place Site w/in 0.5" VCC3SBY GND GND GND
11 GCBE#1 N21 GCBE#1/LMD10 GREEN AE22 VID_GREEN 16 B8 VCC3SBY GND E10
T25 AE23 of clock ball(AA21) B11 E12
11 GCBE#2 GCBE#2/LMD13 BLUE VID_BLUE 16 VCC3SBY GND Solano
11 GCBE#3 Y26 GCBE#3/LRDS# B14 VCC3SBY GND E15
HCLK F22 GMCH_3V66 6 B19 VCC3SBY GND E17
R26 H24 HL0 B22 E20
11 GFRAME# GFRAME#/LMA10 HL0 VCC3SBY GND
P26 H26 HL1 VCC1_8 B25 E22
11 GDEVSEL# GDEVSEL#/LMD11 HL1 VCC3SBY GND
P23 H25 HL2 E2 F1
11 GIRDY# GIRDY#/LMD12 HL2 VCC3SBY GND
P21 G24 HL3 F10 F3
11 GTRDY# GTRDY#/LMA7 HL3 Place R as VCC3SBY GND
P25 F24 HL4 PR18 F14 F11
11 GSTOP# GSTOP#/LMA0 HL4 VCC3SBY GND
R24 E26 HL5 Close as F17 F13
11 GPAR GPAR/LMA6 HL5 VCC3SBY GND
AE26 E25 HL6 possible to G6 T21 VDDQ
11 GREQ# GREQ#/LMD27 HL6 VCC3SBY GND
AD25 D26 HL7 G8 U2 C69
11 GGNT# GGNT# HL7 GMCH VCC3SBY GND
AC26 D25 HL8 40.2,1% G19 U7
11 PIPE# PIPE#/LMD24 HL8 VCC3SBY GND
B D24 HL9 H2 K24 B
HL9 HL10 VCC3SBY GND 560PF
11 ADSTB0 M22 ADSTB0 HL10 C26 H5 VCC3SBY GND V4
L23 H21 HUBREF_GMCH H7 V6 PR21 PR23
11 ADSTB0# ADSTB0# HUBREF VCC3SBY GND
11 ADSTB1 U22 ADSTB1 HLSTB G25 HLSTB 12 GND V20
V23 F26 K20 V22 82,1% 1K,1%
11 ADSTB1# ADSTB1# HLSTB# HLSTB# 12 VDDQ GND
Y23 H20 HCOMP Y24 W2
11 SBSTB SBSTB HCOMP VDDQ GND
AA24 VCC1_8 L21 W7
11 SBSTB# SBSTB# VDDQ GND GMCH_AGPREF 11
SBA0/LMD31 AB22 SBA0 11 M23 VDDQ GND W23
11 ST0 AD24 ST0/LMD28 SBA1/LMD25 AB25 SBA1 11 U25 VDDQ GND W25
AC24 AB23 N25 Y4 PR24 PR22
11 ST1 ST1/LDQM3 SBA2/LDQM2 SBA2 11 VDDQ GND
11 ST2 AC23 ST2/LMD29 SBA3/LMD26 AB26 SBA3 11 R21 VDDQ GND Y6
AA22 PR16 U20 Y8 82,1% 1K,1%
SBA4/LMD23 SBA4 11 VDDQ GND
AD26 AA26 U23 Y10 C72
11 RBF# RBF#/LMD30 SBA5/LWE# SBA5 11 VDDQ GND
AB24 Y22 301,1% W20 Y17
11 WBF# WBF# SBA6/LMD22 SBA6 11 VDDQ GND
11,32 CONN_AGPREF J24 AGPREF SBA7/LGM_FREQ_SEL Y25 SBA7 11 GND Y19
GRCOMP J26 AA2 560PF
PR14 15.1% OCLK R22 GRCOMP GND
OCLOCK AF24 GND GND AA9
RCLK P22 AE25 AA12
PR15 RCLOCK PR13 BC90 PR17 GND GND
GND AA14
BC89 C61 82815 GMCH AA16
40.2,1% 174,1% 0.1UF 301,1% GND
0.1UF 15PF/5%,MPO 82815 GMCH
Display Cache, Video, and
HUB Interface Power and Ground Document: Intel(R) 815E Chipset Universal Socket 370 CRB
A A
NOTE : OCLK = 0.5" Place as close as Place as close as
RCLK = 1.5"
Page Name: GMCH Part 2
Possible to GMCH Possible to GMCH
and via straight and via straight Last Revised: Page: Thursday, November 29, 2001
to VSS plane to VSS plane
Revision:
1.05
Page No:
Folsom, CA 95630
8 of 33
5 4 3 2 1
A B C D E
VCC3SBY VCC3SBY VCC3SBY VCC3SBY
DIMM1 DIMM2
1 VSS VSS 85 1 VSS VSS 85
SM_MD0 2 86 SM_MD32 SM_MD0 2 86 SM_MD32 SM_MAA[0..12] SM_MAA[0..12] 7,10
SM_MD1 DQ0 DQ32 SM_MD33 SM_MD1 DQ0 DQ32 SM_MD33
3 DQ1 DQ33 87 3 DQ1 DQ33 87
SM_MD2 4 88 SM_MD34 SM_MD2 4 88 SM_MD34 SM_MD[0..63] SM_MD[0..63] 7,10
5 DQ3 DQ35 89 5 DQ3 DQ35 89
6 90 6 90 SM_MAB#[4..7] SM_MAB#[4..7] 7
SM_MD4 VDD VDD SM_MD36 SM_MD4 VDD VDD SM_MD36
7 DQ4 DQ36 91 7 DQ4 DQ36 91
SM_MD5 8 92 SM_MD37 SM_MD5 8 92 SM_MD37 SM_DQM[0..7] SM_DQM[0..7] 7,10
4 SM_MD6 DQ5 DQ37 SM_MD38 SM_MD6 DQ5 DQ37 SM_MD38 4
9 DQ6 DQ38 93 9 DQ6 DQ38 93
SM_MD7 10 94 SM_MD39 SM_MD7 10 94 SM_MD39 MEMCLK[0..7] MEMCLK[0..7] 6
11 DQ8 DQ40 95 11 DQ8 DQ40 95
12 96 12 96 SM_CKE[0..3] SM_CKE[0..3] 7
SM_MD9 VSS VSS SM_MD41 SM_MD9 VSS VSS SM_MD41
13 DQ9 DQ41 97 13 DQ9 DQ41 97
SM_MD10 14 98 SM_MD42 SM_MD10 14 98 SM_MD42 SM_CSA#[0..3] SM_CSA#[0..3] 7
15 DQ11 DQ43 99 15 DQ11 DQ43 99
SM_MD12 16 100 SM_MD44 SM_MD12 16 100 SM_MD44 SM_CSB#[0..3] SM_CSB#[0..3] 7
17 DQ13 DQ45 101 17 DQ13 DQ45 101
18 102 18 102 SM_WE# SM_WE# 7,10
SM_MD14 VDD VDD SM_MD46 SM_MD14 VDD VDD SM_MD46
19 DQ14 DQ46 103 19 DQ14 DQ46 103
SM_MD15 20 104 SM_MD47 SM_MD15 20 104 SM_MD47 SM_RAS# SM_RAS# 7,10
DQ15 DQ47 DQ15 DQ47
21 CB0 CB4 105 21 CB0 CB4 105
22 106 22 106 SM_CAS# SM_CAS# 7,10
CB1 CB5 CB1 CB5
24 108 24 108 SM_BS0 SM_BS0 7,10
CB8 CB12 CB8 CB12
25 CB9 CB13 109 25 CB9 CB13 109
26 110 26 110 SM_BS1 SM_BS1 7,10
SM_WE# VDD VDD SM_CAS# SM_WE# VDD VDD SM_CAS#
27 WE#/WE0# CAS#/DU 111 27 WE#/WE0# CAS#/DU 111
SM_DQM0 28 112 SM_DQM4 SM_DQM0 28 112 SM_DQM4
SM_DQM1 DQM0 DQM4 SM_DQM5 SM_DQM1 DQM0 DQM4 SM_DQM5
29 DQM1 DQM5 113 29 DQM1 DQM5 113
SM_CSA#0 30 114 SM_CSA#1 SM_CSA#2 30 114 SM_CSA#3 SMBDATA SMBDATA 10,13,21,24,30,32
CS0# CS1# SM_RAS# CS0# CS1# SM_RAS# SMBCLK
31 DU/OE0# RAS#/DU 115 31 DU/OE0# RAS#/DU 115 SMBCLK 10,13,21,24,30,32
3 32 VSS VSS 116 32 VSS VSS 116 3
SM_MAA0 33 117 SM_MAA1 SM_MAA0 33 117 SM_MAA1
SM_MAA2 A0 A1 SM_MAA3 SM_MAA2 A0 A1 SM_MAA3
34 A2 A3 118 34 A2 A3 118
SM_MAA4 35 119 SM_MAA5 SM_MAB#4 35 119 SM_MAB#5
SM_MAA6 A4 A5 SM_MAA7 SM_MAB#6 A4 A5 SM_MAB#7
36 A6 A7 120 36 A6 A7 120
SM_MAA8 37 121 SM_MAA9 SM_MAA8 37 121 SM_MAA9
SM_MAA10 A8 A9 SM_BS0 SM_MAA10 A8 A9 SM_BS0
38 A10/AP BA0/A11 122 38 A10/AP BA0/A11 122
SM_BS1 39 123 SM_MAA11 SM_BS1 39 123 SM_MAA11
BA1/A12 A11/A13 BA1/A12 A11/A13
40 VDD VDD 124 40 VDD VDD 124
41 125 MEMCLK1 41 125 MEMCLK5
MEMCLK0 VDD CLK1/DU SM_MAA12 MEMCLK4 VDD CLK1/DU SM_MAA12
42 CLK0/DU A12/DU 126 42 CLK0/DU A12/DU 126
44 128 SM_CKE0 44 128 SM_CKE2
SM_CSB#0 DU/OE2# CKE0/DU SM_CSB#1 SM_CSB#2 DU/OE2# CKE0/DU SM_CSB#3
45 CS2# CS3# 129 45 CS2# CS3# 129
SM_DQM2 46 130 SM_DQM6 SM_DQM2 46 130 SM_DQM6
SM_DQM3 DQM2 DQM6 SM_DQM7 SM_DQM3 DQM2 DQM6 SM_DQM7
47 DQM3 DQM7 131 47 DQM3 DQM7 131
48 DU/WE2# A13/DU 132 48 DU/WE2# A13/DU 132
50 134 50 134 VCC3SBY
CB10 CB14 CB10 CB14
51 CB11 CB15 135 51 CB11 CB15 135
52 CB2 CB6 136 52 CB2 CB6 136
53 137 53 137 R28
CB3 CB7 CB3 CB7 2.2K
SM_MD16 55 139 SM_MD48 SM_MD16 55 139 SM_MD48
2 56 DQ17 DQ49 140 56 DQ17 DQ49 140 2
DQ18 DQ50 DQ18 DQ50 DM_SA_PU 10
DQ19 DQ51 DQ19 DQ51
DQ20 DQ52 DQ20 DQ52
61 NC NC 145 61 NC NC 145
62 VREF/DU VREF/DU 146 62 VREF/DU VREF/DU 146
SM_CKE1 63 147 SM_CKE3 63 147
CKE1 REGE CKE1 REGE
66 DQ22 DQ54 150 66 DQ22 DQ54 150
DQ23 DQ55 DQ23 DQ55
70 DQ25 DQ57 154 70 DQ25 DQ57 154
72 DQ27 DQ59 156 72 DQ27 DQ59 156
75 DQ29 DQ61 159 75 DQ29 DQ61 159
77 DQ31 DQ63 161 77 DQ31 DQ63 161
MEMCLK2 79 163 MEMCLK3 MEMCLK6 79 163 MEMCLK7 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
1 CLK2/NC CLK3/NC CLK2/NC CLK3/NC 1
80 NC NC 164 80 NC NC 164
SMBDATA
81 WP SA0 165
SMBDATA
81 WP SA0 165 Page Name: DIMMs 1 and 2
82 SDA SA1 166 82 SDA SA1 166
SMBCLK 83 167 SMBCLK 83 167 Last Revised: Page: Thursday, November 29, 2001
SCL SA2 SCL SA2 Doc: Thursday, November 29, 2001
Revision:
DIMM168 DIMM168 Platform Applications Engineering
1.05
Page No:
Folsom, CA 95630
9 of 33
A B C D E
CH6-12
A B C D E
VCC3SBY VCC3SBY
DIMM3
1 VSS VSS 85
SM_MAA[0..12] SM_MD0 2 86 SM_MD32
7,9 SM_MAA[0..12] SM_MD1 DQ0 DQ32 SM_MD33
3 DQ1 DQ33 87
SM_MD[0..63] SM_MD2 4 88 SM_MD34
7,9 SM_MD[0..63] DQ2 DQ34
SM_MD3 5 89 SM_MD35
SM_MAC#[4..7] DQ3 DQ35
7 SM_MAC#[4..7] 6 VDD VDD 90
SM_MD4 7 91 SM_MD36
SM_DQM[0..7] SM_MD5 DQ4 DQ36 SM_MD37
7,9 SM_DQM[0..7] 8 DQ5 DQ37 92
4 SM_MD6 SM_MD38 4
9 DQ6 DQ38 93
MEMCLK[8..11] SM_MD7 10 94 SM_MD39
6 MEMCLK[8..11] SM_MD8 DQ7 DQ39 SM_MD40
11 DQ8 DQ40 95
SM_CKE[4..5] 12 VSS VSS 96
7 SM_CKE[4..5] SM_MD9 13 97 SM_MD41
SM_MD10 DQ9 DQ41 SM_MD42
SM_CSA#[4..5] 14 DQ10 DQ42 98
7 SM_CSA#[4..5] SM_MD11 15 99 SM_MD43
16 DQ12 DQ44 100
SM_CSB#[4..5] SM_MD13 17 101 SM_MD45
7 SM_CSB#[4..5] DQ13 DQ45
18 VDD VDD 102
SM_WE# SM_MD14 19 103 SM_MD46
7,9 SM_WE# SM_MD15 DQ14 DQ46 SM_MD47
20 DQ15 DQ47 104
SM_RAS# 21 105
7,9 SM_RAS# CB0 CB4
22 CB1 CB5 106
SM_CAS# 23 107
7,9 SM_CAS# VSS VSS
24 CB8 CB12 108
7,9 SM_BS0 SM_BS0 25 109
CB9 CB13
26 VDD VDD 110
SM_BS1 SM_WE# 27 111 SM_CAS#
7,9 SM_BS1 SM_DQM0 WE#/WE0# CAS#/DU SM_DQM4
28 DQM0 DQM4 112
SM_DQM1 29 113 SM_DQM5
SMBDATA SM_CSA#4 DQM1 DQM5 SM_CSA#5
9,13,21,24,30,32 SMBDATA 30 CS0# CS1# 114
SMBCLK 31 115 SM_RAS#
9,13,21,24,30,32 SMBCLK DU/OE0# RAS#/DU
3 32 VSS VSS 116 3
SM_MAA0 33 117 SM_MAA1
SM_MAA2 A0 A1 SM_MAA3
34 A2 A3 118
SM_MAC#4 35 119 SM_MAC#5
SM_MAC#6 A4 A5 SM_MAC#7
36 A6 A7 120
SM_MAA8 37 121 SM_MAA9
SM_MAA10 A8 A9 SM_BS0
38 A10/AP BA0/A11 122
SM_BS1 39 123 SM_MAA11
BA1/A12 A11/A13
40 VDD VDD 124
41 125 MEMCLK9
MEMCLK8 VDD CLK1/DU SM_MAA12
42 CLK0/DU A12/DU 126
43 VSS VSS 127
44 128 SM_CKE4
SM_CSB#4 DU/OE2# CKE0/DU SM_CSB#5
45 CS2# CS3# 129
SM_DQM2 46 130 SM_DQM6
SM_DQM3 DQM2 DQM6 SM_DQM7
47 DQM3 DQM7 131
48 DU/WE2# A13/DU 132
49 VDD VDD 133
50 CB10 CB14 134
51 CB11 CB15 135
52 CB2 CB6 136
53 CB3 CB7 137
54 VSS VSS 138
SM_MD16 55 139 SM_MD48
2 56 DQ17 DQ49 140 2
SM_MD18 57 141 SM_MD50
58 DQ19 DQ51 142
59 VDD VDD 143
SM_MD20 60 144 SM_MD52
DQ20 DQ52
61 NC NC 145
62 VREF/DU VREF/DU 146
SM_CKE5 63 147
CKE1 REGE
64 VSS VSS 148
SM_MD21 65 149 SM_MD53
66 DQ22 DQ54 150
SM_MD23 67 151 SM_MD55
DQ23 DQ55
68 VSS VSS 152
SM_MD24 69 153 SM_MD56
70 DQ25 DQ57 154
SM_MD26 71 155 SM_MD58
72 DQ27 DQ59 156
73 VDD VDD 157
SM_MD28 74 158 SM_MD60
75 DQ29 DQ61 159
SM_MD30 76 160 SM_MD62
77 DQ31 DQ63 161
78 VSS VSS 162
MEMCLK10 79 163 MEMCLK11 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
1 CLK2/NC CLK3/NC 1
80 NC NC 164
9 DM_SA_PU 81 165 Page Name: DIMM 3
SMBDATA WP SA0
82 SDA SA1 166
SMBCLK 83 167 Last Revised: Page: Thursday, November 29, 2001
SCL SA2 Doc: Thursday, November 29, 2001
84 VDD VDD 168
Revision:
DIMM168 Platform Applications Engineering
1.05
Page No:
Folsom, CA 95630
10 of 33
A B C D E
A B C D E
VCC3_3 VCC12 VCC12

VCC5 VDDQ
R106
2.2K
4 4
VDDQ AGP1
18 AGP_OC# B1 OVRCNT# 12V A1
RN49 B2 A2 TYPEDET# 26
GSERR# 5V_A TYPEDET#
1 2 B3 5V_B RESV_A A3
GPAR 3 4 B4 A4
18 AGPUSBP USB+ USB- AGPUSBN 18
GPERR# 5 6 B5 A5
GDEVSEL# GND_K GND_A
7 8 14,15,30 PIRQ#B B6 INTB# INTA# A6 PIRQ#A 14,15,30
B7 CLK RST# A7 PCI_RST# 14,15,30
6 AGPCLK_CONN GREQ# GGNT#
8.2K/8P4R B8 A8 GGNT# 8
8 GREQ# REQ#/DQ27 GNT#
RN48 B9 A9
GFRAME# ST0 VCC3.3_F VCC3.3_A ST1
1 2 8 ST0 B10 ST0/DQ28 DQM3/ST1 A10 ST1 8
GIRDY# 3 4 ST2 B11 A11
GTRDY# 8 ST2 RBF# ST2/DQ29 RESV_B PIPE#
5 6 B12 RBF#/DQ30 DQ24/PIPE# A12 PIPE# 8
GSTOP# 8 RBF#
7 8 B13 GND_L GND_B A13
B14 A14 WBF#
RESV_H WBF# WBF# 8
8.2K/8P4R SBA0 B15 A15 SBA1
SBA0/DQ31 DQ25/SBA1
RN42 B16 A16
GREQ# SBA2 VCC3.3_G VCC3.3_B SBA3
1 2 B17 SBA2/DQM2 DQ26/SBA3 A17
GGNT# 3 4 SBSTB B18 A18 SBSTB1#
8 SBSTB SB_STB SB_STB# SBSTB# 8
ST0 5 6 B19 A19
ST1 SBA4 GND_M GND_C SBA5
7 8 B20 SBA4/DQ23 WE#/SBA5 A20
SBA6 B21 A21 SBA7
V3SB SBA6/DQ22 M_FREQ_SEL/SBA7
3 8.2K/8P4R B22 A22 3
RESV RESV_C
RN43 B23 A23
ST2 GND_N GND_D
1 2 B24 3.3VAUX1 RESV_D A24
RBF# 3 4 B25 A25
PIPE# GAD31 VCC3.3_H VCC3.3_C GAD30
5 6 B26 AD31/DQ21 TCLK0/AD30 A26
WBF# 7 8 GAD29 B27 A27 GAD28
AD29/DQ20 TCLK1/AD28
B28 VCC3.3_I VCC3.3_D A28
8.2K/8P4R GAD27 B29 A29 GAD26
GAD25 AD27/DQ19 CAS#/AD26 GAD24
RN44 B30 A30
SBA0 AD25/DQ18 AD24
1 2 B31 GND_O GND_E A31
SBA1 3 4 ADSTB1 B32 A32 ADSTB1#
8 ADSTB1 AD_STB1 AD_STB1# ADSTB1# 8
SBA2 5 6 GAD23 B33 A33
AD23/DQ17 RAS#/C/BE3# GCBE#3 8
SBA3 7 8 B34 A34
GAD21 VDDQ_F VDDQ_A GAD22
B35 AD21/DQ16 A0/AD22 A35
8.2K/8P4R GAD19 B36 A36 GAD20
AD19/DQ15 A9/AD20
RN46 B37 A37
SBA7 GAD17 GND_P GND_F GAD18
1 2 B38 AD17/DQ14 A11/AD18 A38
SBA6 3 4 B39 A39 GAD16
8 GCBE#2 C/BE2#/DQ13 A8/AD16
5 6 B40 VDDQ_G VDDQ_B A40
7 8 GIRDY# B41 A41 GFRAME#
8 GIRDY# IRDY#/DQ12 A10/FRAME# GFRAME# 8
B42 3.3VAUX2 RESV_E A42
8.2K/8P4R B43 A43
GND_Q GND_G
B44 RESV_K RESV_F A44
ADSTB0 8.2K R332 B45 A45
ADSTB0# 8.2K R333 GDEVSEL# VCC3.3_J VCC3.3_E GTRDY# VDDQ
2
8 GDEVSEL# B46 DEVSEL#/DQ11 A7/TRDY# A46 GTRDY# 8 2
ADSTB1 8.2K R334 B47 A47 GSTOP#
VDDQ_H CS#/STOP# GSTOP# 8
ADSTB1# 8.2K R335 GPERR# B48 A48
PERR# PME# PCI_PME# 12,14,15,22
B49 GND_R GND_H A49
GSERR# B50 A50 GPAR
SERR# A6/PAR GPAR 8
RN45 B51 A51 GAD15
SBSTB# 8 GCBE#1 C/BE1#/DQ10 A1/AD15
1 2 B52 VDDQ_I VDDQ_C A52
SBSTB 3 4 GAD14 B53 A53 GAD13 Place close PR20
SBA5 GAD12 AD14/DQ9 A5/AD13 GAD11
5 6 B54 A54
SBA4 7 8 B55
AD12/DQ8 A2/AD11
A55
to GMCH 301,1%
GAD10 GND_S GND_I GAD9 CON_AGPREF
B56 AD10/DQM1 A4/AD9 A56
8.2K/8P4R GAD8 B57 A57
AD8/DQ0 A3/C/BE0# GCBE#0 8
B58 VDDQ_J VDDQ_D A58
ADSTB0 B59 A59 ADSTB0# PR19
8 ADSTB0 AD_STB0 AD_STB0# ADSTB0# 8
GAD7 B60 A60 GAD6
AD7/DQ1 DQ5/AD6 200,1%
B61 GND_T GND_J A61
GAD5 B62 A62 GAD4
GAD3 AD5/DQ2 DQ6/AD4 GAD2
B63 AD3/DQ3 DQ7/AD2 A63
B64 A64 Q13
GAD1 VDDQ_K VDDQ_E GAD0 2N7002
B65 AD1/DQ4 DQM0/AD0 A65
8 GMCH_AGPREF B66 VREF_CG VREF_GC A66 CONN_AGPREF 8,32
AGP4XU_20
1
GAD[0..31] Page Name: AGP
8 GAD[0..31]
SBA[0..7] Doc: Thursday, November 29, 2001
8 SBA[0..7]
Revision:
1.05
Page No:
Folsom, CA 95630
11 of 33
A B C D E
CH6-18
5 4 3 2 1
VCC3_3 VCC1_8 VCC1_8 V3SB V3SB V3SB V1_8SB V1_8SB
U12A
G18
H18
R18
D10
U18
E14
E15
E16
E17
E18
P18
K19
V17
V18
V14
V15
V16
F18
T18
L19
J18
G5
R5
U5
D2
H5
V5
V6
V7
V8
E5
P5
V9
82801BA ICH2
T5
F5
J5
AD[0..31]
14,15 AD[0..31]
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_18
VCC3_3_19
VCC3_3_20
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6
VCCPS1
VCCPS2
VCCPX1
VCCPX2
VCCUSB1
VCCUSB2
VCCCS1
VCCCS2
VCCCS3
VCCAX1
VCCAX2
VCCA
AD0 AA4 HL[0..10]
AD0 HL[0..10] 8
AD1 AB4
AD2 AD1
Y4 AD2 A20M# D11 A20M# 4
D AD3 D
W5 AD3 CPUSLP# A12 CPUSLP# 4
AD4 W4 R22
AD4 FERR# FERR# 4
AD5 Y5 A11
AD5 IGNNE# IGNNE# 4
AD6 AB3 C12
AD6 INIT# INIT# 4,17
AD7 AA5 C11
AD7 INTR INTR 4
AD8 AB5 B11
AD8 NMI NMI 4
AD9 Y3 B12
AD9 SMI# SMI# 4
AD10 W6 C10
AD10 STPCLK# STPCLK# 4
AD11 W3 B13
AD11 RCIN# KBRST# 21,30
AD12 Y6 C13
AD12 A20GATE A20GATE 21,30
AD13 Y2 A13
AD13 CPUPWRGOD CPU_PWGD 4,33
AD14 AA6
AD15 AD14 HL0
Y1 AD15 HL0 A4
AD16 V2 B5 HL1
AD17 AD16 HL1 HL2
AA8 AD17 HL2 A5
AD18 V1 B6 HL3
AD19 AD18 HL3 HL4
AB8 AD19 HL4 B7
AD20 U4 A8 HL5 VCC1_8
AD21 AD20 HL5 HL6
W9 AD21 HL6 B8
AD22 U3 A9 HL7
AD23 AD22 HL7 HL8
Y9 AD23 HL8 C8
AD24 U2 C6 HL9 PR27 Place R as
AD25 AD24 HL9 HL10
AB9 AD25 HL10 C7 Close as
C
AD26 U1 C5 40.2,1%possible to C
AD27 AD26 HL11
W10 AD27 HLSTB A6 HLSTB 8 ICH
AD28 T4 A7
AD28 HLSTB# HLSTB# 8
AD29 Y10 A3
AD30 AD29 HCOMP HUBREF_ICH
T3 AD30 HUBREF B4 HUBREF_ICH 32
AD31 AA10 AD31
PIRQ#A P1 ICH_IRQ#A 30
AA3 P2 VCC1_8
14,15 C_BE#0 C_BE#0 PIRQ#B ICH_IRQ#B 30
14,15 C_BE#1 AB6 C_BE#1 PIRQ#C P3 ICH_IRQ#C 30
14,15 C_BE#2 Y8 C_BE#2 PIRQ#D N4 ICH_IRQ#D 30
14,15 C_BE#3 AA9 C_BE#3
IRQ14 F21 IRQ14 17
W11 C16 PR25
6 PCLK_0/ICH PCICLK IRQ15 IRQ15 17
14,15,30 FRAME# V3 FRAME# APICCLK N20 APICCLK_ICH 6
C101 AB7 N19 301,1%
14,15,30 DEVSEL# DEVSEL# APICD1 APICD1 4
14,15,30 IRDY# W8 IRDY# APICD0 P22 APICD0 4
10PF V4 N21
NPOP 14,15,30 TRDY# TRDY# SERIRQ SERIRQ 21,30
14,15,30 STOP# W1 STOP#
30 ICHRST# AA15 PCIRST# REQ#0 R2 PREQ#0 14,30
AA7 R3 BC119 PR26
14,15,30 PLOCK# PLOCK# REQ#1 PREQ#1 14,30
14,15 PAR W2 PAR REQ#2 T1 PREQ#2 15,30
W7 AB10 0.01UF 301,1%
14,15,30 SERR# SERR# REQ#3 PREQ#3 30
14,15,30 PERR# Y7 PERR# REQ#4 P4 PREQ#4 30
11,14,15,22 PCI_PME# Y15 PCI_PME# REQ#B/GPI1/REQ#5 L3 PREQ#5 30
B B
30 PCI_REQ#A M3 REQ#A/GPI0 GNT#0 M2 PGNT#0 14
L2 M1 Place as close as
GNT#A/GPO16 GNT#1 PGNT#1 14
GNT#2 R4 PGNT#2 15 Possible to ICH
30 ICH_IRQ#E N3 PIRQ#E/GPI2 GNT#3 T2 and via straight
30 ICH_IRQ#F N2 PIRQ#F/GPI3 GNT#4 R1 to VSS plane
30 ICH_IRQ#G N1 PIRQ#G/GPI4 GNT#B/GPO17/GNT#5 L4
30 ICH_IRQ#H M4 PIRQ#H/GPI5
17 P66DET Y11 GPI6 LAN_RXD0 G2 LAN_RXD0 24
17 S66DET AA11 GPI7 LAN_RXD1 G1 LAN_RXD1 24
30 GPI8 Y14 GPI8 LAN_RXD2 H1 LAN_RXD2 24
W14 RN69 22/8P4R
24 EXTSMI# GPI12
AB15 F3 U12_RN69-1 1 2
21,30 LPC_PME# GPI13 LAN_TXD0 LAN_TXD0 24
A15 F2 U12_RN69-3 3 4
GPO18 LAN_TXD1 LAN_TXD2 24
D14 F1 U12_RN69-5 5 6
GPO19 LAN_TXD2 LAN_TXD1 24
C14 U12_RN69-7 7 8
GPO20
L1 GPO21
B14 GPOD22 LAN_RSTSYNC H2 LAN_RSTSYNC 24
17 GPIO23 A14 GPO23 LAN_CLK G3 LAN_CLK 24
30 GPIO27 AB14 GPIOD27
24,29 PRI_DWN# AA14 GPIOD28
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
A
Page Name: ICH2 Part 1

AA21
AA22
AB21
AB22
M10
M11
M12
M13
M14
AA1
AA2
AB1
AB2
N10
N11
N12
N13
N14
A10
A21
A22
B10
B21
B22
K10
K11
K12
K13
K14
P10
P11
P12
P13
P14
L10
L11
L12
L13
L14
J10
J11
J12
J13
J14
M9
C2
C3
C4
C9
D3
D5
D6
D7
D8
D9
N9
A1
A2
B1
B2
B3
B9
E6
E7
E8
E9
K1
K9
P9
L9
J9

Revision:
1.05
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Folsom, CA 95630
12 of 33
5 4 3 2 1
A B C D E
VCC3_3 V3SB VCCRTC VCC5SBY VCMOS

6 ICH_CLK14
R141 10
Q16 C96 BC197
3
2N7002 D18
D19 R134 1K X10P 0.1UF
3
VCC5 SS12/SMD
BAT54C
R129 1K VCC5
2
1
R325 1K
4 VCC3_3 4
C104
2
VCC3_3 C91 BC125 D8 SS12/SMD
M20
U21
D12
D13
V19
K2
VCC_CLOCK 1.0UF
U12B 1.0UF 0.1UF
Target 20ms after
W15
VCPU1
VCPU2
V5R1
V5R2
VCCRTC
V5R_SUS
VCC_CLOCK is 30 GPIO25 GPIO25
V21 GPIO24
powered AA13
5 21,30 OVT# THRM#
R376 43k U33 W16 E21
6,21,28 SLP_S3# SLP_S3# PDCS#1 PDCS#1 17
1 AB18 C15
GND Vcc
A 28 SLP_S5# SLP_S5# SDCS#1 SDCS#1 17

4 ICH_PWROK R20 E19
Y PWROK PDSC#3 PDCS#3 17
C172 Y16 D15
RSM_PWROK SDCS#3 SDCS#3 17
2 JP1 W21 PDA[0..2]
B 21,33 PWRBTN# PWRBTN# PDA[0..2] 17
1.0uF R174 15K R174_JP1 1 AA17 F20 PDA0
22,30 ICH_RI# RI# PDA0
741G08 AND 2 R21 F19 PDA1
21 RSMRST# RSMRST# PDA1
C113 PDA2
3
3 Y17 SUS_STAT# PDA2 E22

AA18 A16 SDA0
21 SUSCLK SUSCLK SDA0
D12 1.0UF CCM0S AA16 D16 SDA1
9,10,21,24,30,32 SMBDATA SMBDATA SDA1
R187 AB16 B16 SDA2
21,25 PWROK 9,10,21,24,30,32 SMBCLK SMBCLK SDA2
AB17 SDA[0..2]
30 SMBALERT# SMBALTER#/GPI11 SDA[0..2] 17
SS12/SMD 1K T19 G22
21,25 CASEOPEN# INTRUDER# PDDREQ PDREQ 17
SDDREQ B18 SDREQ 17
R181 1K F22
PDDACK# PDDACK# 17
R377 0 M19 B17
3 CLK14 SDDACK# SDDACK# 17 3
C110 P20 G19
6 USBCLK CLK48 PDIOR# PDIOR# 17
Debug only - do D4 D17
6 ICH_3V66 CLK66 SDIOR# SDIOR# 17
not stuff 0.047UF G21
PDIOW# PDIOW# 17
BAT1 VBIAS T21 C17
VBIAS SDIOW# SDIOW# 17
RTCX1 U22 G20
RTCX1 PIORDY PIORDY 17
BATTERY RTCX2 T22 A17
RTCX2 SIORDY SIORDY 17
RTCRST# T20 RTCRST# PDD0
PDD0 H19
R162 H22 PDD1
PDD1 PDD2
24,29 AC_RST# V22 AC_RST# PDD2 J19
P19 J22 PDD3
19,24 AC_SYNC AC_SYNC PDD3
10M C88 R19 K21 PDD4
19,24 AC_BITCLK AC_BITCLK PDD4
P21 L20 PDD5
19,24,29 AC_SDOUT AC_SDOUT PDD5
X18PF Y22 M21 PDD6
19,24,30 AC_SDIN0 AC_SDIN0 PDD6
R149 10M W22 M22 PDD7
24,30 AC_SDIN1 AC_SDIN1 PDD7
N22 L22 PDD8
19,24,29 ICH_SPKR SPKR PDD8
Y2 L21 PDD9
17,21 LAD0 PDD9 PDD10
Y12 LAD0/FWH0 PDD10 K22
17,21 LAD1 W12 K20 PDD11
32.768KHZ 17,21 LAD2 LAD1/FWH1 PDD11 PDD12
AB13 LAD2/FWH2 PDD12 J21
C103 C102 17,21 LAD3 AB12 J20 PDD13
17,21 LFRAME# LAD3/FWH3 PDD13 PDD14
AB11 LFRAME#/FWH4 PDD14 H21
18PF 18PF Y13 H20 PDD15
21 LDRQ#0 LDRQ#0 PDD15
2 W13 PDD[0..15] 2
LDRQ#1 PDD[0..15] 17
RN70 15/8P4R D18 SDD0
SDD0 SDD1
18 USBP0P 1 2 W17 USBP0P SDD1 B19
3 4 Y18 D19 SDD2
18 USBP0N USBP0N SDD2
5 6 AB19 A20 SDD3
18 USBP1P USBP1P SDD3
RN71 15/8P4R 7 8 AA19 C20 SDD4
1 2 W18 C21 SDD5
3 4 Y19 D22 SDD6
5 6 AB20 E20 SDD7
7 8 AA20 D21 SDD8
C22 SDD9
SDD9 SDD10 VCC3_3
18 USBOC#0-1 W19 OC#0 SDD10 D20
Y20 B20 SDD11
OC#1 SDD11 SDD12
18 USBOC#2-3 Y21 OC#2 SDD12 C19
W20 A19 SDD13
OC#3 SDD13 SDD14 R403
SDD14 C18
K4 A18 SDD15 V3SB
24 EE_CS EE_CS SDD15 1K
K3 SDD[0..15]
24 EE_DIN EE_DIN SDD[0..15] 17
24 EE_DOUT J4 EE_DOUT SMLINK0 U19 SMLINK0 15,30
24 EE_SHCLK J3 EE_SHCLK SMLINK1 V20 SMLINK1 15,30
VRMPWRGD B15 VRM_PWRGD 27
U20 R324 1K
TP0
FS0 AA12
2
4
6
8
2
4
6
8
R271 R164 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
1 CP1 1
2
4
6
8
2
4
6
8
CP2 Page Name: ICH2 Part 2

560K 560K 47PF/8P4C 82801BA ICH2
47PF/8P4C Last Revised: Page: Thursday, November 29, 2001
1
3
5
7
1
3
5
7

Revision:
1
3
5
7
1
3
5
7

1.05
Page No:
Folsom, CA 95630
13 of 33
A B C D E
A B C D E
V3SB
V3SB VCC5
VCC3_3 VCC3_3
VCC3_3 VCC3_3
VCC5 VCC5
VCC5 VCC12
VCC12- VCC12 VCC12-
4 4
PCI1 PCI2
B1 -12V TRST# A1 B1 -12V TRST# A1
B2 TCK +12V A2 B2 TCK +12V A2
B3 GND TMS A3 B3 GND TMS A3
B4 TDO TDI A4 B4 TDO TDI A4
B5 +5V +5V A5 B5 +5V +5V A5
B6 A6 B6 A6 PIRQ#B
+5V INTA# PIRQ#A 11,15,30 +5V INTA#
B7 A7 PIRQ#C B7 A7 PIRQ#D
11,15,30 PIRQ#B INTB# INTC# PIRQ#C 15,30 INTB# INTC#
B8 A8 PIRQ#A B8 A8
15,30 PIRQ#D INTD# +5V INTD# +5V
B9 PRSNT#1 RESERVED A9 B9 PRSNT#1 RESERVED A9
B10 RESERVED +5V(I/O) A10 B10 RESERVED +5V(I/O) A10
B11 PRSNT#2 RESERVED A11 B11 PRSNT#2 RESERVED A11
B12 GND GND A12 B12 GND GND A12
B13 GND GND A13 B13 GND GND A13
B14 RESERVED RESERVED A14 B14 RESERVED RESERVED A14
B15 A15 B15 A15 PCI_RST#
6 PCLK_1 GND RST# PCI_RST# 11,15,30 6 PCLK_2 GND RST#
B16 CLK +5V(I/O) A16 B16 CLK +5V(I/O) A16
B17 GND GNT A17 PGNT#0 12 B17 GND GNT A17 PGNT#1 12
12,30 PREQ#0 B18 REQ# GND A18 12,30 PREQ#1 B18 REQ# GND A18
B19 A19 B19 A19 PCI_PME#
+5V(I/O) PME# PCI_PME# 11,12,15,22 +5V(I/O) PME#
AD31 B20 A20 AD30 AD31 B20 A20 AD30
AD29 AD31 AD30 AD29 AD31 AD30
B21 AD29 +3.3V A21 B21 AD29 +3.3V A21
3 B22 A22 AD28 B22 A22 AD28 3
AD27 GND AD28 AD26 AD27 GND AD28 AD26
B23 AD27 AD26 A23 B23 AD27 AD26 A23
AD25 B24 A24 AD25 B24 A24
AD25 GND AD24 AD25 GND AD24
B25 +3.3V AD24 A25 B25 +3.3V AD24 A25
C_BE#3 B26 A26 R_AD16 R133 AD16 C_BE#3 B26 A26 R_AD17 R142 AD17
AD23 C/BE#3 IDSEL 100 AD23 C/BE#3 IDSEL 100
B27 AD23 +3.3 A27 B27 AD23 +3.3 A27
B28 A28 AD22 B28 A28 AD22
B29 AD21 AD20 A29 B29 AD21 AD20 A29
AD19 B30 A30 AD19 B30 A30
B31 +3.3V AD18 A31 B31 +3.3V AD18 A31
AD17 B32 A32 AD16 AD17 B32 A32 AD16
C_BE#2 AD17 AD16 C_BE#2 AD17 AD16
B33 C/BE#2 +3.3V A33 B33 C/BE#2 +3.3V A33
B34 A34 B34 A34 FRAME#
GND FRAME# FRAME# 12,15,30 GND FRAME#
B35 A35 IRDY# B35 A35
12,15,30 IRDY# IRDY# GND IRDY# GND
B36 A36 B36 A36 TRDY#
+3.3V TRDY# TRDY# 12,15,30 +3.3V TRDY#
B37 A37 DEVSEL# B37 A37
12,15,30 DEVSEL# DEVSEL# GND DEVSEL# GND
B38 A38 B38 A38 STOP#
GND STOP# STOP# 12,15,30 GND STOP#
12,15,30 PLOCK# B39 A39 PLOCK# B39 A39
12,15,30 PERR# PERR# LOCK# +3.3V PERR# LOCK# +3.3V
B40 PERR# SDONE A40 B40 PERR# SDONE A40
B41 +3.3V SBO# A41 B41 +3.3V SBO# A41
B42 A42 SERR# B42 A42
12,15,30 SERR# SERR# GND SERR# GND
B43 A43 B43 A43 PAR
+3.3V PAR PAR 12,15 +3.3V PAR
C_BE#1 B44 A44 AD15 C_BE#1 B44 A44 AD15
AD14 C/BE#1 AD15 AD14 C/BE#1 AD15
B45 AD14 +3.3V A45 B45 AD14 +3.3V A45
2 B46 A46 AD13 B46 A46 AD13 2
B47 AD12 AD11 A47 B47 AD12 AD11 A47
AD10 B48 A48 AD10 B48 A48
B49 GND AD9 A49 B49 GND AD9 A49
AD8 B52 A52 C_BE#0 AD8 B52 A52 C_BE#0

AD7 AD8 C/BE#0 AD7 AD8 C/BE#0
B53 AD7 +3.3V A53 B53 AD7 +3.3V A53
B54 A54 AD6 B54 A54 AD6
AD5 +3.3V AD6 AD4 AD5 +3.3V AD6 AD4
B55 AD5 AD4 A55 B55 AD5 AD4 A55
AD3 B56 A56 AD3 B56 A56
B57 GND AD2 A57 B57 GND AD2 A57
AD1 B58 A58 AD0 AD1 B58 A58 AD0
AD1 AD0 AD1 AD0
B59 +5V(I/O) +5V(I/O) A59 B59 +5V(I/O) +5V(I/O) A59
ACK64# B60 A60 ACK64# B60 A60
15,30 ACK64# ACK64# REQ64# REQ64#1 30 ACK64# REQ64# REQ64#2 30
B61 +5V +5V A61 B61 +5V +5V A61
B62 +5V +5V A62 B62 +5V +5V A62
PCI_CON_32BIT PCI_CON_32BIT
AD[0..31]
12,15 AD[0..31]
1
C_BE#[0..3] Page Name: PCI 1 and 2
12,15 C_BE#[0..3]
Revision:
1.05
Page No:
Folsom, CA 95630
14 of 33
A B C D E
A B C D E
V3SB
VCC3_3 VCC3_3
VCC5 VCC5
VCC12- VCC12
4 4
PCI3
B1 -12V TRST# A1
B2 TCK +12V A2
B3 GND TMS A3
B4 TDO TDI A4
B5 +5V +5V A5
B6 +5V INTA# A6 PIRQ#C 14,30
14,30 PIRQ#D B7 INTB# INTC# A7 PIRQ#A 11,14,30
11,14,30 PIRQ#B B8 INTD# +5V A8
B9 PRSNT#1 RESERVED A9
B10 RESERVED +5V(I/O) A10
B11 PRSNT#2 RESERVED A11
B12 GND GND A12
B13 GND GND A13
B14 RESERVED RESERVED A14
B15 GND RST# A15 PCI_RST# 11,14,30
6 PCLK_3 B16 A16
CLK +5V(I/O)
B17 GND GNT A17 PGNT#2 12
12,30 PREQ#2 B18 REQ# GND A18
B19 +5V(I/O) PME# A19 PCI_PME# 11,12,14,22
AD31 B20 A20 AD30
AD29 AD31 AD30
B21 AD29 +3.3V A21
3 B22 A22 AD28 3
AD27 GND AD28 AD26
B23 AD27 AD26 A23
AD25 B24 A24
AD25 GND AD24
B25 +3.3V AD24 A25
C_BE#3 B26 A26 R_AD18 R148 AD18
AD23 C/BE#3 IDSEL 100
B27 AD23 +3.3 A27
B28 A28 AD22
AD21 GND AD22 AD20
B29 AD21 AD20 A29
AD19 B30 A30
AD19 GND AD18
B31 +3.3V AD18 A31
AD17 B32 A32 AD16
C_BE#2 AD17 AD16
B33 C/BE#2 +3.3V A33
B34 GND FRAME# A34 FRAME# 12,14,30
12,14,30 IRDY# B35 IRDY# GND A35
B36 +3.3V TRDY# A36 TRDY# 12,14,30
12,14,30 DEVSEL# B37 DEVSEL# GND A37
B38 GND STOP# A38 STOP# 12,14,30
12,14,30 PLOCK# B39 A39
12,14,30 PERR# PERR# LOCK# +3.3V
B40 PERR# SDONE A40 SMLINK0 13,30
B41 +3.3V SBO# A41 SMLINK1 13,30
12,14,30 SERR# B42 SERR# GND A42
B43 +3.3V PAR A43 PAR 12,14
C_BE#1 B44 A44 AD15
AD14 C/BE#1 AD15
B45 AD14 +3.3V A45
2 B46 A46 AD13 2
AD12 GND AD13 AD11
B47 AD12 AD11 A47
AD10 B48 A48
AD10 GND AD9
B49 GND AD9 A49
AD8 B52 A52 C_BE#0

AD7 AD8 C/BE#0
B53 AD7 +3.3V A53
B54 A54 AD6
AD5 +3.3V AD6 AD4
B55 AD5 AD4 A55
AD3 B56 A56
AD3 GND AD2
B57 GND AD2 A57
AD1 B58 A58 AD0
AD1 AD0
B59 +5V(I/O) +5V(I/O) A59
ACK64# B60 A60
14,30 ACK64# ACK64# REQ64# REQ64#3 30
B61 +5V +5V A61
B62 +5V +5V A62
PCI_CON_32BIT
1 AD[0..31]
12,14 AD[0..31]
Page Name: PCI 3
C_BE#[0..3] Last Revised: Page: Thursday, November 29, 2001
12,14 C_BE#[0..3]
Revision:
1.05
Page No:
Folsom, CA 95630
15 of 33
A B C D E
A B C D E
VCC5
VCC5 VCC1_8
F5 BC68
BC223
FUSE_1.0A 0.22UF
0.22UF
4 4
VFB3 F5_FB11
8 VID_RED 1 2 R73 R84
2
BEAD 1K FB11 1K
PR12 C50 C49 VGA1
U28 BEAD 6
75,1% 3.3PF X10PF RV
1
1
1 16 MONOPU 11
VCC3 SD2
7
2 15 GV 2
VCC1 SD1 DDCDA 12
VFB2 3 VIDEO_1 SYNC_OUT2 14 8
BV 3
8 VID_GREEN 1 2 4 13 HS 13
VIDEO_2 SYNC_IN2
9
BEAD 5 12 MON2PU 4
C46 VIDEO_3 SYNC_OUT1 VS
PR11 C47 14
6 GND SYNC_IN1 11 10
75,1% 3.3PF X10PF 5
7 10 R321 10 DDCCL 15
POWER_UP DDC_OUT2
VFB1 R322 10
8 9 VGA_CONN
8 VID_BLUE VCC2 DDC_OUT1
3 1 2 3
R85 33 R87 33
BEAD PAC-VGA201/QSOP
PR10 C43 C45 BC224 BC225 C55 C54 C57 C56 C48 C53
75,1% 3.3PF X10PF 0.22UF0.22UF 22PF 10PF 22PF 10PF 10PF 10PF
U8
QST3384 D4
24 U8_VCC
VCC VCC5
8 3VDDCDA 3 2 5VDDCDA 1 2
8 3VDDCCL 1A1 1B1 5VDDCCL
4 1A2 1B2 5 3 4
8 CRT_HSYNC 7 6 5VHSYNC R326 22 5 6 1N4148
8 CRT_VSYNC 1A3 1B3 5VVSYNC R327 22
8 1A4 1B4 9 7 8
11 10 R95 BC86
8 3VFTSDA 1A5 1B5 5VFTSDA VCC3SBY VCC1_8 RN41 2.2K/8P4R
14 15 C134 C135
8 3VFTSCL 2A1 2B1 5VFTSCL 4.7K
17 16 0.1UF
2A2 2B2 100PF 100PF
18 2A3 2B3 19
21 2A4 2B4 20
22 2A5 2B5 23
1 R97 R96
BEA# R328 2.2K VCC1_8
13 BEB# GND 12
2 4.7K 4.7K R329 2.2K 2
R350
1k Place 100pF cap
near DVO pin 40
FTVREF
VCC5 C136 C137
FTVSYNC 8
R351
FTHSYNC 8 1k 0.01uF 100pF
SL_STALL 8
7,17,21,30 PCIRST#
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
RST#
CVBS
SP2
PD#
VREF
SP0
SP1
SP3
SCL5
SCL
5V2
3V1
VDD1
VDD2
VDD3
VDD4
SDA
J3
SDA5
HS
5V1
3V2
3V3
3V4
VS
I/C
Y
C
VCC5 VCC3_3 VCC1_8 DVO CONNECTOR
49 D1 G10
53 D0 G11
G12
45 D2 G9
G3
G7
D10 G1
G2
ST# G5
STB G6
D4 G8
D7 G4
57 D/B
D11
D5
D9
D8
D6
41 D3
G10
G11
G12
C138 C139 C140 C141 C142 C143 C144
G1
G2
G3
G4
G5
G6
G7
G8
G9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
43
47
51
55
59
1
3
5
7
1.0uF 1.0uF 1.0uF 2.2uF 1.0uF 1.0uF 2.2uF

FTD11 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
1 FTD10 1
FTD9 Page Name: VGA Header and DVO Debug Header
FTD8
FTCLK0 8
FTD7 Last Revised: Page: Thursday, November 29, 2001
FTCLK1 8
FTD6 Doc: Thursday, November 29, 2001
FTBLNK# 8
FTD5 Revision:
FTD4 Platform Applications Engineering
FTD3 1.05
FTD2 1900 Prairie City Road
FTD1 Page No:
8 FTD[0..11] FTD[0..11] FTD0 Folsom, CA 95630
16 of 33
A B C D E
8 7 6 5 4 3 2 1
IDE
FWH 13 PDD[0..15]
PDD[0..15]
VCC3_3 VCC3_3 PDA[0..2]

13 PDA[0..2]
IDE1
IDERST# R113 33 IDERST_IDE1_PIN1 1 2
30 IDERST# PDD7 PDD8
3 4
D BC173 VCC3_3 PDD6 PDD9 D
BC175 BC177 BC178 5 6
R207 PDD5 7 8 PDD10
0.1UF PDD4 9 10 PDD11
0 0.1UF 0.1UF 0.1UF PDD3 11 12 PDD12
R79 PDD2 13 14 PDD13
PDD1 15 16 PDD14
4.7K PDD0 17 18 PDD15
U23 19 20
1 VPP VCC 32 21 22
13 PDREQ
7,16,21,30 PCIRST# 2 RST# CLK 31 PCLK_8 6 13 PDIOW# 23 24
R206 8.2K 3 30 FPGI4 R211 8.2K 25 26
FGPI3 FGPI4 13 PDIOR#
4 FGPI2 IC 29 13 PIORDY 27 28
5 FGPI1 GNDA 28 13 PDDACK# 29 30
6 FGPI0 VCCA 27 31 32
12 IRQ14 PDA1
7 WP# GND 26 33 34 P66DET 12
12 GPIO23 8 25 VCC3_3 R83 8.2K PDA0 35 36
TBL# VCC
9 ID3 INIT# 24 INIT# 4,12 13 PDCS#1 37 38 PDCS#3 13
10 ID2 FWH4 23 LFRAME# 13,21 24 IDEACTP# 39 40
11 ID1 RFU 22
12 21 PIN_2X20
13,21 LAD0 ID0 RFU PDA2 R80
13 FWH0 RFU 20
13,21 LAD1 14 19 C51
13,21 LAD2 FWH1 RFU 10K
15 FWH2 RFU 18
16 17 LAD3 13,21 47PF
C GND FWH3 C
FWH32
SDD[0..15]
13 SDD[0..15]
SDA[0..2]
13 SDA[0..2]
IDE2
IDERST# R112 33 IDERST_IDE2_PIN1 1 2
SDD7 3 4 SDD8
VCC3_3 SDD6 5 6 SDD9
SDD5 7 8 SDD10
SDD4 9 10 SDD11
SDD3 11 12 SDD12
R76 SDD2 13 14 SDD13
SDD1 15 16 SDD14
4.7K SDD0 17 18 SDD15
19 20
21 22
13 SDREQ
13 SDIOW# 23 24
25 26
13 SDIOR#
13 SIORDY 27 28
B
13 SDDACK# 29 30 B
31 32
12 IRQ15 SDA1 33 34 S66DET 12
VCC3_3 R75 8.2K SDA0 35 36
13 SDCS#1 37 38 SDCS#3 13
24 IDEACTS# 39 40
PIN_2X20 R70
SDA2
C44 10K
47PF
A
Page Name: FWH and UDMA100 IDE

Revision:
1.05
Page No:
Folsom, CA 95630
17 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCC5DUAL
F4 FUSE_1.0A
13 USBOC#0-1 USB1
1 2 1 VCC0
2 DATA0-
FB8 BEAD 3
BC4 DATA0+
+ EC18 4 GND0
5 VCC1
D 100UF 470PF D
6 DATA1-
1 2 7 DATA1+
8 GND1
1 2 FB21 BEAD
USB_CON2
13 USBP0N
1 2 FB22 BEAD
13 USBP0P
13 USBP1N
13 USBP1P 1 2 FB23 BEAD
FB24 BEAD
2
4
6
8
1
3
5
7
2
4
6
8
RN72 CP3
15K/8P4R
47PF/8P4C
1
3
5
7
2
4
6
8
V3SB
1
3
5
7
R266 R267
330K 330K
C C
24 CNR_OC# R268 X0 VCC5DUAL
11 AGP_OC# R269 X0 F7 FUSE_1.0A
13 USBOC#2-3
1 2
USB2
FB25 BEAD
1 2
3 4
1 2 5 6
C122 7 8
+ EC39 1 2 FB26 BEAD
9 10
100UF 470PF FB27 BEAD HEADER5X2
1 2
1 2 FB28 BEAD
FB29 BEAD
13 USBP2N
B B
13 USBP2P
13 USBP3N
2
4
6
8
13 USBP3P
2
4
6
8
CP4
1
3
5
7
RN73 47PF/8P4C
1
3
5
7
15K/8P4R
2
4
6
8
1
3
5
7
1
2 JP4
24 CNRUSBN 3 JP4 Pin 3 near USB2 Pin 5
24 CNRUSBP 4 HEADER5 JP4 Pin 4 near USB2 Pin 7
5
1
2 JP5
11 AGPUSBN 3
11 AGPUSBP 4 JP5 Pin 3 near USB2 Pin 6
5 JP5 Pin 4 near USB2 Pin 8
HEADER5
A
Page Name: USB

Revision:
1.05
Page No:
Folsom, CA 95630
18 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCC3_3 VCC5 VCC5_AUDIO
1
PFB6
BEAD
2
D D
BC140 BC139 BC136 BC129
0.1UF 0.1UF 0.1UF 0.1UF
38
42
25
26
40
44
43
U15
9
DVSS1
DVDD1
DVSS2
DVDD2
AVDD2
AVSS2
AVDD1
AVSS1
NC40
NC44
NC43
13,24,29 ICH_SPKR R336 1K R336_MC56 MC56 1UF PC_BEEP 12
20 LINE_IN_R PC_BEEP
24 LINE_IN_R
20 LINE_IN_L 23
20 MIC_IN LINE_IN_L
21 MIC1 RESET# 11 PRI_DWN_RST# 29
C 22 MIC2 SDATA_OUT 5 AC_SDOUT 13,24,29 C
20 CD_R 20 8
CD_R SDATA_IN AC_SDIN0 13,24,30
20 CD_L 18 10
20 CD_REF 19
CD_L
CD_REF
AC’97 SYNC
BIT_CLK 6
AC_SYNC
AC_BITCLK
13,24
13,24
17
16
VIDEO_R
VIDEO_L
CODEC CS1 46
20 AUX_L 14 45
20 AUX_R AUX_L CS0
15 AUX_R CHAIN_CLK 48
13 PHONE EAPD 47 EAPD 20
24 AC97SPKR R154 100 R154_MC58 MC58 1UF MONO_OUT 37
20 LNLVL_OUT_R MONO_OUT C99
36 LINE_OUT_R
20 LNLVL_OUT_L 35 LINE_OUT_L X10PF
41 LNLVL_OUT_R
39 LNLVL_OUT_L
VREFOUT
XTL_OUT
XTL_IN
FILT_R
AFILT1
AFILT2
FILT_L
VREF
RX3D
CX3D
R252
CS4299
29
30
32
31
33
34
27
VREFOUT 28
1K
2
FILT_R
AFILT1
AFILT2
FILT_L
B R253 X0 AUD_VREFOUT 20 B
VREF
CX3D
RX3D
XTAL_OUT
XTAL_IN
MC51
Y1 R254
0.1uF NPOP
1K
24.576MHZ
R337 R155 C95 C94 MC53 MC54 MC52 MC55 MC46 MC48 C98 C97
220K 220K
2700PF 2700PF 1UF 1UF 1UF 0.1UF 4.7UF 2.2UF 22PF 22PF
"SINGLE POINT CONNECTION"
A
Page Name: AC’97 Codec

Revision:
1.05
Page No:
Folsom, CA 95630
19 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Stereo HP/Spkr out

C77 R104 FB13
C87_C77 SPKROUT_R
+
1 2
JK1
100UF 22 BEAD
C78 R105 FB14

SPKROUT_L
+
1 2
D D
100UF 22 BEAD
MC47 R132 PHONEJACK
MC47_R132 C75 C74
19 LNLVL_OUT_L
1UF 20K 100PF 100PF
C87 100PF
C74_JK1
R126 20K
U11_OUTA VCC5_AUDIO
U11
MC45 R127 1 OUTA 8 R128
MC45_R127 U11_INA VDD U11_OUTB 20K C90
2 INA OUTB 7
19 LNLVL_OUT_R U11_BYPASS U11_INB 100PF
3 BYPASS INB 6
1UF 20K 4 GND 5
SHUTDN
LM4880
MC40
1UF BC123
C C
0.1UF
19 EAPD
Line_In Analog Input CD Analog Input

MC44 FB17
MC44_R122 R122 R122_FB17 1 JK2_LINE_IN_R CD2 MC43
2 R115
19 LINE_IN_R 1K CD_INR CDIN_R
JK2 1 CD_R 19
1UF BEAD 2
3 CD_ING 1K 1UF
MC42 FB16 4 CD_INL R117 MC39
MC42_R121 R121 R121_FB16 1 2 JK2_LINE_IN_L CDIN_L
19 LINE_IN_L CD_L 19
1K 2.54_WAFER_4 1K
1UF BEAD 1UF
C80 C86 PHONEJACK R116 MC38
CDIN_REF
CD_REF 19
100PF 100PF
1K 1UF
B
CD1 B
1 R125 C81 R118 C79 R124 C82
2 220K 220K 220K
3 100PF 100PF 100PF
4
2mm_WAFER_4
R119
Microphone Input
R119_FB15 JK3 AUX1 MC36
19 AUD_VREFOUT AUX_INL
2.2K 1 AUX_L 19
2
MC41 R120 FB15 3 1UF MC37
R120_MC41 1 2 JK3_MICIN 4 AUX_INR
19 MIC_IN AUX_R 19
1K 2.54_WAFER_4
1UF BEAD 1UF
C76 PHONEJACK C83 C84
C85
0.01UF 100PF 100PF 100PF
A
"SINGLE POINT CONNECTION" Page Name: Audio I/O
Revision:
1.05
Page No:
Folsom, CA 95630
20 of 33
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IRRX 23
25 VTT_SENSE IRTX 23
RI#1 22
DCD#1 22
9,10,13,24,30,32 SMBDATA R185 TXD1 22
300
RXD1 22
9,10,13,24,30,32 SMBCLK R193 DTR#1 22
300
RTS#1 22
25 -5VIN
DSR#1 22
25 -12VIN
CTS#1 22
25 +12VIN
25 +3.3VIN
D
CASEOPEN# 13,25 D
25 VCORE
SUSCLK 13
25 HM_VREF
25 VTIN3
SLP_S3# 6,13,28
FB20 R157 VCC5SBY
VCC5 1 2 IOAVCC R166 10K
PS_ON 25
FB19 0
1 2 BEAD PWROK 13,25
BC172 R167 V3SB
BEAD 0.1UF 10K
RSMRST# 13
4,25 THRMDN
PANSWIN 24,32
VCCRTC
PWRBTN# 13,33
VCC5
MDAT 23
BC154 BC161
MCLK 23
0.1UF 0.1UF
102
101
100
U17
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SDA/GP22
PLED/GP23
SUSCIN/GP30
CIRRX/GP34
VTIN3
SCL/GP21
WDTO/GP24
IRRX/GP25
IRTX/GP26
RIB#
DCDB#
DTRB#
DSRB#
RTSB#
CTSB#
CASEOPEN#
PWRCTL#/GP31
PWROK/GP32
RSMRST#/GP33
PSIN#
PSOUT#
+3.3VIN
AVCC
-12VIN
-5VIN
AGND
VCC
SUSCLKIN
VCOREA
VCOREB
+12VIN
VSS
SOUTB
SINB
MCLK
VREF
VBAT
MDAT
4,25 VTIN2 103 64
VTIN2 SUSLED/GP35 SUSLED 24
C 25 VTIN1 104 63 C
VTIN1 KDAT KDAT 23
13,30 OVT# 105 62
OVT# KCLK KCLK 23
106 VID4 VSB 61 VCC5SBY
27,29,32 VID3 107 60
VID3 KBRST KBRST# 12,30
27,29,32 VID2 108 59
VID2 GA20M A20GATE 12,30
27,29,32 VID1 109 58
VID1 KBLOCK# KEYLOCK# 24
27,29,32 VID0 110 57
VID0 RIA# RI#0 22
25 FANIO3 111 56
FANIO3 DCDA# DCD#0 22
25 FANIO2 112 55
25 FANIO1 FANIO2 VSS
113 FANIO1 SOUTA 54 TXD0 22
114 VCC SINA 53 RXD0 22
115 52 DTR#0 22
25
25
FANPWM2
FANPWM1 116
FANPWM2
FANPWM1
W83627HF DTRA#
RTSA# 51 RTS#0 22
117 VSS DSRA# 50 DSR#0 22
24 BEEP 118 49
BEEP CTSA# CTS#0 22
23 MIDI_IN 119 48 VCC5
23 MIDI_OUT MSI/GP20 VCC
120 MSO/IRQIN0 STB# 47 STB# 22
23 J1BUTTON2 121 46
GPSA2/GP17 AFD# AFD# 22
23 J2BUTTON2 122 45
GPSB2/GP16 ERR# ERR# 22
23 JOY1Y 123 44
GPY1/GP15 INIT# PAR_INIT# 22
23 JOY2Y 124 43
GPY2/P16/GP14 SLIN# SLIN# 22
23 JOY2X 125 42
23 JOY1X GPX2/P15/GP13 PD0
126 GPX1/P14/GP12 PD1 41
23 J2BUTTON1 127 40 BC151
23 J1BUTTON1 GPSB1/P13/GP11 PD2 0.1UF
128 GPSA1/P12/GP10 PD3 39
DSKCHG#
DRVDEN0
DRVDEN1
LFRAME#
LRESET#
RDATA#
SERIRQ
TRAK0#
INDEX#
PCICLK
HEAD#
VCC3V
LDRQ#
STEP#
B B
CLKIN
MOA#
MOB#
BUSY
PME#
DSB#
DSA#
ACK#
SLCT
LAD3
LAD2
LAD1
LAD0
DIR#
WD#
WE#
WP#
VCC
VSS
PD7
PD6
PD5
PD4
PE
FDD Signals Trace 8 or 10 mil PDR0 22
W83627HF
PDR1 22
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
PDR2 22
FDC1 PDR3 22
1 2 RWC#
PDR4 22
3 4 PDR5 22
5 6 DS1#
PDR6 22
7 8 PDR7 22
9 10 MOA#
ACK# 22
11 12 DSB#
BUSY 22
13 14 DSA#
PE 22
15 16 MOB#
SLCT 22
17 18 DIR#
19 20 STEP#
PCIRST# 7,16,17,30
21 22 WD# VCC5
23 24 WE#
25 26 VCC3_3
27 28
29 30
31 32 HEAD# BC162 BC155
33 34 .1U .1U
HEADER_17X2
6 SIO_CLK24
12,30 LPC_PME#
6 PCLK_7
A A
13 LDRQ#0 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
12,30 SERIRQ
13,17 LAD3
Page Name: Super I/O and FDC
13,17 LAD2 Last Revised: Page: Thursday, November 29, 2001
13,17 LAD1 Doc: Thursday, November 29, 2001
13,17 LAD0 Revision:
13,17 LFRAME# Platform Applications Engineering
1.05
Page No:
Folsom, CA 95630
21 of 33
8 7 6 5 4 3 2 1
A B C D E
VCC12- VCC12 VCC5

WAKE ON LAN
COM1
VCC5SBY
D6 D7 COM1
U9 DCD0 1
SS12/SMD SS12/SMD DSR0 6
10 1 RXDD0 2
4 -12V 12V RTS0 4
11 GND 5V 20 7
TXDD0 3
11,12,14,15 PCI_PME# WOL1 DCD0 BC99 CTS0
21 DCD#0 12 RY5 RA5 9 8
3 13 8 DTR0 .1U DTR0 4
Q21 R230 21 DTR#0 DA3 DY3 CTS0 RI0
2 21 CTS#0 14 RY4 RA4 7 9
1 15 6 TXDD0 5
21 TXD0 DA2 DY2 RTS0
21 RTS#0 16 DA1 DY1 5
100 17 4 RXDD0
21 RXD0 RY3 RA3
2
4
6
8
2
4
6
8
2N3904 HEADER_3*1(2MM) 18 3 DSR0 CONNECTOR_DB9
R229 21 DSR#0 RY2 RA2 RI0 CN2
19 2 CN3
2
4
6
8
2
4
6
8
4.7K 21 RI#0 RY1 RA1
GD75232
100PF/8P4C 100PF/8P4C
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
WAKE ON MODEM
13,30 ICH_RI# U10 COM2
R107 10 1 CTS1
RI0 Q14 -12V 12V DSR1
11 GND 5V 20
2N3904 DTR1
3 10K R108 12 9 DCD1 BC54 RXDD1 3
2.2K 21 DCD#1 RY5 RA5 DTR1 .1U
13 8 COM2
21 DTR#1 DA3 DY3 CTS1 DCD1
14 RY4 RA4 7 1 2
21 CTS#1 TXDD1 TXDD1
21 TXD1 15 DA2 DY2 6 3 4
16 5 RTS1
21 RTS#1 DA1 DY1 RXDD1 RTS1 5 6
R109 17 4
RI1 Q15 21 RXD1 RY3 RA3 DSR1 RI1 7 8
21 DSR#1 18 RY2 RA2 3 9 10
2N3904 19 2 RI1
R110 21 RI#1 RY1 RA1
10K HEADER_5X2
2.2K GD75232
2
4
6
8
2
4
6
8
CN11 CN9
2
4
6
8
2
4
6
8
21 AFD#
Parallel Port 100PF/8P4C 100PF/8P4C
1
3
5
7
1
3
5
7
21 ERR#
VCC5
1
3
5
7
1
3
5
7
D2
U5
SS12/SMD
21 PAR_INIT# 1 28
P1 P8 BC49
2 21 SLIN# 2 27 .1U 2
P2 P7 LPT1
21 STB# 3 26 1
SI1 SO1
14
21 PDR0 4 25 2
SI2 SO2
15
21 PDR1 5 24 3
SI3 SO3
16
21 PDR2 6 23 4
SI4 SO4
17
21 PDR3 7 22 5
SI5 GND
18
21 SLCT 8 21 6
P3 SO5
19
21 PDR4 9 20 7
SI6 VCC
20
21 PE 10 19 8
P4 SO6
21
21 PDR5 11 18 9
SI7 SO7
22
21 BUSY 12 17 10
P5 SO8
23
21 PDR6 13 16 11
SI8 SO9
1 21 PDR7
24 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1
14 SI9 P6 15 12
25 Page Name: Serial, Parallel, WOL, and WOR
13
PAC-S1284 Doc: Thursday, November 29, 2001
21 ACK# LPT Revision:
1.05
Page No:
Folsom, CA 95630
22 of 33
A B C D E
A B C D E
VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5

R103 0
F6 XFUSE_1.0A
2
FB12
R92 R99 R94 R93 R102 R101 BEAD

C70
4 4.7K 4.7K 4.7K 4.7K 4
1
4.7K 4.7K
470PF
J1
1
RN40 1K/8P4R 9
8 7 J1BUT1 2
21 J1BUTTON1 J2BUT1
21 J2BUTTON1 6 5 10
4 3 JOY_1X 3
21 JOY1X JOY_2X
21 JOY2X 2 1 11
4
R98 47 MIDI_OUTPUT 12
21 MIDI_OUT RN39 1K/8P4R 5
8 7 JOY_2Y 13
21 JOY2Y JOY_1Y
21 JOY1Y 6 5 6
4 3 J2BUT2 14
21 J2BUTTON2 J1BUT2
21 J1BUTTON2 2 1 7
R91 47 MIDI_INPUT 15
21 MIDI_IN
8
C60 C66 GAME_PORT
8
6
4
2
8
6
4
2
1000PF 22PF C73
8
6
4
2
8
6
4
2
3
C64 C68 C62 C59 CN8 CN10 3
1000PF 22PF 470PF
470PF 470PF
7
5
3
1
7
5
3
1
C63 C67 470PF/8P4C 470PF/8P4C
22PF 1000PF Game Port
7
5
3
1
7
5
3
1
C65 C71
22PF 1000PF
VCC5DUAL R17 0
FB1
F1 XFUSE_1.0A 1 2
BEAD
R18 0
F2 XFUSE_1.0A
FB3 U1
1 2 CN1_U1
21 KDAT 1
2
BEAD
3
2 FB5 2
4
1 2 5
21 KCLK
6
BEAD
RN4 4.7K/8P4R
13
8 7 14
6 5 FB2
15
4 3 1 2
2 1 16
BEAD
17
FB4
1 2 7
21 MDAT
8
BEAD
9
FB6
10
21 MCLK 1 2 11
12
BEAD
KB/MOUSE
IR1 CN1
VCC5 1 8 7
8 7
2 6 5 C1 C2
21 IRRX 3
4
4
2
6
4
2
5
3
1
3
1
2.2UF 2.2UF Keyboard Document: Intel(R) 815E Chipset Universal Socket 370 CRB
1 5 1
21 IRTX
HEADER_1X5
470PF8P4C Mouse Page Name: PS/2, Game, and IR
IR Platform Applications Engineering
Revision:
1.05
Page No:
Folsom, CA 95630
23 of 33
A B C D E
8 7 6 5 4 3 2 1
Power V3SB VCC5SBY VCC5 VCC3_3 VCC12-VCC5SBY VCC12V3SB VCC5

Switch CNRSLOT1
SW2
B1 RESERVED RESERVED A1
1 1 2 2 B2 RESERVED RESERVED A2
B3 RESERVED GND A3
R246 B4 A4
R233 R242 R244 R243 2.2K GND RESERVED
3 4 R238 B5 A5
3 4 10K 220 10K 150 220 RESERVED RESERVED
B6 RESERVED GND A6
SW_4 B7 A7
D GND LAN_TXD2 LAN_TXD2 12 D
12 LAN_TXD1 B8 LAN_TXD1 LAN_TXD0 A8 LAN_TXD0 12
12 LAN_RSTSYNC B9 LAN_RSTSYNC GND A9
PN1 B10 A10 LAN_CLK 12
R238_PN1 GND LAN_CLK
1 12 LAN_RXD2 B11 LAN_RXD2 LAN_RXD1 A11 LAN_RXD1 12
2 12 LAN_RXD0 B12 LAN_RXD0 RESERVED A12
3 B13 GND USB+ A13 CNRUSBP 18
KEYLOCK B14 A14
21 KEYLOCK# 4 RESERVED GND
5 B15 +5VDUAL USB- A15 CNRUSBN 18
12 EXTSMI# 18 CNR_OC# B16 A16
R243_PN1 6 USB_OC# +12V
7 B17 GND GND A17
D15_PN1 HDD LED B18 A18 R272 C125 R273 C126
8 -12V +3.3VDUAL
9 B19 +3.3VD +5VD A19 15K 15K
R242_PN1 47PF 47PF
10 PWR_SW
21,32 PANSWIN 11
12 B20 GND GND A20
R241 BC185 B21 A21
10K 13 SMI_SW 13 EE_DIN EE_DOUT EE_DIN EE_DOUT 13
R240 R240_PN1 B22 A22
0.1UF 14 13 EE_SHCLK EE_SHCLK EE_CS
0 B23 A23 EE_CS 13
C119 GND SMB_A1
HEADER_14 B24 A24
9,10,13,21,30,32 SMBCLK SMB_A0 SMB_A2
B25 SMB_SCL SMB_SDA A25 SMBDATA 9,10,13,21,30,32
0.1UF 12,29 PRI_DWN# B26 A26
PRIMARY_DN# AC97_RESET# AC_RST# 13,29
B27 GND RESERVED A27
D15 1N4148 13,19 AC_SYNC B28 A28
AC97_SYNC AC97_SD_IN1 AC_SDIN1 13,30
13,19,29 AC_SDOUT B29 A29
C 17 IDEACTP# AC97_SD_OUT AC97_SD_IN0 AC_SDIN0 13,19,30 C
13,19 AC_BITCLK B30 A30
AC97_BITCLK GND
D14 1N4148 CNR
R247
17 IDEACTS#
20K
SW3
VCC5 1 2
1 2
VCC5SBY VCC5
3 4 VCC5 VCC5
R255 3 4
10K SW_4
SMBCLK
Reset R235 R234
Switch 10K 150 SMBDATA
PN2
25,32 HWRST# 1 RESET SMB2 SMB1

2
3 1 1
4 2 2
5 3 3
B SPEAKER 4 4 B
R237_PN2 6
7 5 5
8
SMBCON SMBCON
9 GREEN LED
10
11
D16
21 SUSLED Q22 R237 12 RESERVE VCC5SBY R239 330
2N3904 13
0 14
LED
HEADER_14
R237_2
VCC5 VCC5
SP1
R236
R223
10K R232 68 33 BUZZER
21 BEEP Q19 R231 68

R256 0 2N3904
JP2
13,19,29 ICH_SPKR R226 2.2K Q20 Document: Intel(R) 815E Chipset Universal Socket 370 CRB
A 1 2 2N3904 BC184 A
3 4 0.1UF
Page Name: Front Panel Headers and CNR
XHEADER 2X2
19 AC97SPKR Revision:
JP2 PC_BEEP SELECTION Platform Applications Engineering
1-2 ON TRADITIONAL 1.05
3-4 ON CONTROLLED by AC97 CODEC 1900 Prairie City Road
Page No:
Folsom, CA 95630
24 of 33
8 7 6 5 4 3 2 1
A B C D E
VCC3_3 VCC5SBY VCC5 V3SB
ATXPR1
11 3.3V 3.3V 1
VCC12- 12 2 BC164 D10
-12V 3.3V .1U 1N4148 R190 R189
13 GND GND 3
14 4 VCC5SBY 15K
21 PS_ON PS_ON +5V 4.7K
14
15 GND GND 5
16 6 U20C U19A
GND +5V
17 GND GND 7
VCC_5- 18 8 ATXPWROK 5 6 1 2
4 -5V PWROK 4
19 +5V AUX5V 9
VCC5 VCC5SBY 74LVC14A C115 R192
20 +5V +12V 10 VCC12 74LVC06A 33K
2.2UF
7
ATX_PWCON
VCC5SBY
U20F U19F
R245 100 13 12 13 12 VCC5SBY

24,32 HWRST#
74LVC14A U20D U19E
V3SB V3SB 74LVC06A
9 8 11 10 PWROK 13,21
74LVC14A
R323 BC165 V3SB VCC5SBY 74LVC06A
1K .1U
U20A U19B
14
4 DBRESET# 1 2 3 4
7
3
74LVC14A 3
74LVC06A JP3
Temperature Sensing
1
2
HEADER_2
21 VTIN3
PR38 RT2
t
VCC12 VCC5 21 HM_VREF
10K,1% X10K_1%-THRM/0603
R218
21 VTIN1
"system use"
4.7K
Q18 CHASSIS FAN R210 PR39 RT1
t
R217 1K 2N2907 D13 R212
+12CHFAN 4,21 VTIN2
30K 10K,1% 10K_1%-THRM/0603
1N4148 1K C118
Q17 EC38
FAN3 "power use"
+ 3 3300PF
2N7002 FANIO1 21
2
21 FANPWM1 R216 22UF 4,21 THRMDN
510 1
PR37 PR36
HEADER_3 VCC12
2 28K,1% 10K,1%
Voltage Sensing 2
VCC12 VCC5
+12VIN 21
R11 VCCVID R209
VCORE 21
4.7K
Q2 CPU FAN 10K
2N2907 D1 R19 VTT R208
R10 1K VTT_SENSE 21
+12CPUFAN 10K
1N4148 1K
VCC3_3 R214
Q1 FAN1 +3.3VIN 21
EC3 + 3
2N7002 FANIO2 21 10K
21 FANPWM2 2 PR35 PR34
R16 510 22UF 1 VCC12-
56K,1% 232K,1%
HEADER_3
-12VIN 21
VCC12 VCC5
-5VIN 21
VCCRTC R213 10M PR33 PR32
VCC_5-
13,21 CASEOPEN# PWR FAN 56K,1% 120K,1%
EC35 + D5 R100
If case is opened,
1 this switch should be closed. 22UF 1K
1N4148
S1 FAN2 Page Name: ATX Power and HW Monitor
3 FANIO3 21
HEADER_2PIN 2 Last Revised: Page: Thursday, November 29, 2001
1 Doc: Thursday, November 29, 2001
Revision:
HEADER_3 Platform Applications Engineering
1.05
Page No:
Folsom, CA 95630
25 of 33
A B C D E
A B C D E
VCC5SBY VCC12 VCC3_3
VCC5 Q39
1
U31_FORCE1 PHD55N03LT VDDQ
1
R354 C155 C156 C157 C158 C159
3.3k R357
4 4
0.1uF 100uF 100uF 4.7uF 4.7uF
3
0
D23 BAT54C U31_SENSE1
R356
3
3.3k R355_C147 R358 R401 R400
C147
1M - NPOP VCC3_3 220 220
11 TYPEDET# C148 1.0uF Q48_B Q48
R355 PNP
VCC3_3 0.1uF 0 Q49_B Q49
U31 NPN
8 VCC FORCE 1 7
R359 U31_SHDN1# 5 6 R402
10k SHDN1# SENSE 1 VCC3_3
3 SHDN2# FORCE 2 1 470
4 GND SENSE 2 2
U31_SHDN2# Empty for ADM1051AJR
ADM1051A
3 3
Q40
U31_FORCE2 MTD3055VLT4 C150 C151 C152 C153 C149
VCC1_8
U31_SENSE2 100uF 100uF 4.7uF 4.7uF 0.1uF
VCC5 R360 VCC12
100 1% Target is
R378
really 1.85V
3
2.2k
D24 R361
3
BAT54C 5620 1%
VTTPWRGD12 6
Q43
2N7002 VTT
1
VCC5
VCC5 R379
1
2 1k 2
VTT VCC5 U32A ASSERTED LOW!
VCC3_3 R380
VR1 20k V1_8SB U32B R381
8 VCC VTTPWRGD 4
2 3 1k
VOUT C160 IN+ 1 D24_U32 Q44
3 VIN OUT 1 1 5 IN+ 2
R364 2 7 2N7002
VR1_FB 22uF Tantalum IN- 1 C173 OUT 2
ADJ 1 4 GND 6 IN- 2
C162 0.1 uF
C174 LT1587-ADJ 49.9 1% V1_8SB 2.0ms delay
10 uF 0.1uF LM393 Ch1 LM393 Ch2
nominal VTTPWRGD5# 27
R366
732 1%
Q41
Document: Intel(R) 815E Chipset Universal Socket 370 CRB
FDN335N R367 U32-2 Page Name: VRegs: Vddq, Vcc1_8, and Vtt
4,6,7 TUAL5 R368 Page: Thursday, November 29, 2001
1 Last Revised: 1
10 1% 1k 1% Doc: Thursday, November 29, 2001
Revision:
1.05
Page No:
Folsom, CA 95630
26 of 33
A B C D E
A B C D E
VCC5 L7 1.7uH
Q45_L7
C175 C176 C177 C178 C179 C180 C181

10uF 0.1uF 3300uF 3300uF 0.1uF 4.7uF 4.7uF
U34_R384
4 4
VCC12 C182 0.001uF
U34 U34_C182
R382 10 (805) R382_U34 16 11 Q45
VID3 VCC CS+ SUD50N03-07 R383 R384
1 VID3 CS- 10
C183 C184 VID2 2 19 220 220
0.1uF 4.7uF VID1 VID2 PGND U34-18 R385 4.7 (805)
3 VID1 DRVH 18 VCCVID
VID0 U34-17 R386 2.2 (805) L8 1.2uH
4 VID0 DRVL 17
VID4 5 9 VCCVID_FB Q45_L8
VID25 FB R389 2 mOhm (2512)
29,32 VID[0:4] 8 SD PWRGD 6 VRM_PWRGD 13
7 R388 C185 C186 C187
26 VTTPWRGD5# U34_R391 REF Q46_R386 820uF 820uF 1000uF
13 COMP LRDRV 14
U34_C18812 15 U34_1415 2.2 (805)
VCC5 C188 CT LRFB
20 GND Q46
ADP3170 SUD50N03-07 C189 C190 C191 C192
R390 100pF 4700pF 820uF 820uF 1000uF
R391 0
3 25.5k 1% 3
R393 R392 0
C193
0.001uF C194
154k 1% 0.1uF
V3SB
New V1_SB Circuitry
This takes the place of

R404 the old V1_8SB circuit.
V1_8SB
2 32.4 1% 2
C197
R405
38.3 1%

Page Name: VRegs: VCCVID, V1_8SB
1 Last Revised: Page: Thursday, November 29, 2001 1
Revision:
1.05
Page No:
Folsom, CA 95630
27 of 33
A B C D E
A B C D E
VCC5SBY VCC12 VCC3_3 VCC5 VCC2_5

Q3
ADJ
EC17 EC11 EC19 3 VIN VOUT 2
C7 + + +
LM1117ADJ
4 0.1UF 100UF 10UF 100UF 4
1
+ EC6 PR3 + EC5
14
1
U2 10UF 100,1% 100UF
Q3_Feedback
5VSB
12V
Q7
Q4 15 U2_Q7
U2_Q4 DRV2 HUF76121D3S/TO252
3 3V3DLSB
NZT651/SOT223 PR2
VSEN2 16 VCC3SBY
4 100,1%
V3SB U2_R20 3V3DL VCC5SBY
9 FAULT/MSET EC14
C5 +
EC20
+ C18
R20 1UF 1500UF
10UF 1UF 10K EC10
+
11 U2_Q5
5VDLSB Q5 100UF
6 NDS356AP/SOT23
6,13,21 SLP_S3# S3
13 SLP_S5# 7 S5
5 EN5VDL 5VDL 12 VCC5DUAL
VCC5SBY 2
GND
U2_C4 EN3VDL
3 13 SS DLA 10 3
C8
C4 RT9641
1UF
8
0.1UF
U2_Q8
Q8
4 G2 D2 5
VCC3_3 3 6
S2 D2
Do not stuff this box.
2 G1 D1 7
Debug note:
VCC5 1 8 VCC1_8
S1 D1 Stuff only one box.
Stuff this box
VCC3_3 VCMOS R369
2 FDS8936 / SI9936 Q42 1.13 1% 2
EC22 EC15
+ + 1206 pack
ADJ
3 VIN VOUT 2
100UF 100UF
LT1117ADJ
+ EC42 + EC43
1
PR44
10UF 10UF R370
49.9 1% 9.31 1%
1210 pack
Q42_Feedback
PR45
10 1%
1
Page Name: VRegs: Duals, 3.3SB, 2.5, VCMOS

Revision:
1.05
Page No:
Folsom, CA 95630
28 of 33
A B C D E
A B C D E
V3SB
2
4
6
8
RN59
2.2K/8P4R
1
3
5
7
4 VCC3_3 SW1 DIPSW-8 4
1 16
2 15
3 14
4 13
5 12 SW1_R262 R262 8.2K
AC_SDOUT 13,19,24
6 11 SW1_R263 R263 8.2K
ICH_SPKR 13,19,24
7 10
8 9
D17
13,24 AC_RST#
1N4148
VCC5SBY
3 3
U19C
12,24 PRI_DWN# 5 6 PRI_DWN_RST# 19
R153 74LVC06A
10K
SW 7 ON BOARD AC97 CODEC

OFF PRIMARY CODEC
ON DISABLE
VCC3_3 V3SB
J5
2 1 2 3 1
3,32 JPR_VID0 2 1
2
3 3 2
5 4 5 6 4
3,32 JPR_VID1 5 4
6 6
8 7 8 9 7 SW 5 AC_SDOUT
3,32 JPR_VID2 8 7
9 9 ON USE CPU FREQ STRAP IN ICH REGISTER
11 10 11 12 10 OFF FORCE CPU FREQ STRAP TO SAFE MODE(1111)
3,32 JPR_VID3 11 10
12 12
14 13 14 15 13 SW 6 STRAP(SPKR)
3,32 JPR_VID4 14 13
15 15 ON NO REBOOT ON 2ND WATCHDOG TIMEOUT
17 16 17 18 16 OFF REBOOT ON 2ND WATCHDOG TIMEOUT
4,32 BSEL#1 17 16
18 18
20 19 20 21 19
4,32 BSEL#0 20 19
21 21
7x3 JPR HDR

2
4
6
8
2
4
6
8
RP5 RP6
1K/8P4R 1K/8P4R
1
1
3
5
7
1
3
5
7
Page Name: System Config DIP Switches

21,27,32 VID0 Page: Thursday, November 29, 2001
21,27,32 VID1 Last Revised:
21,27,32 VID2
21,27,32 VID3 R394 8.2k
Revision:
27,32 VID4 Platform Applications Engineering
7 R_REFCLK FMOD1 6 1.05
7 R_BSEL#0 FMOD0 6 1900 Prairie City Road
Page No:
R395 8.2k Folsom, CA 95630
29 of 33
A B C D E
A B C D E
PCI VCC5 ICH2 V3SB VCC3_3 VCC3_3 VCC5

RP2 RN55
12,14,15 PERR# 1 5 13 SMBALERT# 1 2
12,14,15 SERR# R1 C 13,22 ICH_RI#
2 R2 3 4
12,14,15 PLOCK# 3 9,10,13,21,24,32 SMBCLK 5 6 BC163 R196
12,14,15 STOP# R3 9,10,13,21,24,32 SMBDATA .1U 1K
14
4 R4 C 10 7 8
12,14,15 DEVSEL# 6
12,14,15 TRDY# R5 V3SB U18A
7 8.2K/8P4R
12,14,15 IRDY# R6
8 RN60 1 2 IDERST# 17
12,14,15 FRAME# R7 12,21 LPC_PME#
9 R8 1 2
3 4 74LVC07A
4 13,15 SMLINK0 4
2.7K/10P8R 5 6
13,15 SMLINK1
7
RN58 7 8
1 2
12,15 PREQ#2 3 4 4.7K/8P4R V3SB VCC3_3
12,14 PREQ#1 5 6 RN54 VCC3_3
12,14 PREQ#0 7 8 1 2
12 GPI8
13 GPIO25 3 4
2.7K/8P4R 5 6 R197
12 GPIO27
RN64 1K
14
7 8
1 2
12 PREQ#3 3 4 8.2K/8P4R VCC3_3 U18B
12 PREQ#5 5 6 RN51 3 4 PCI_RST# 11,14,15
12 PREQ#4 7 8 12 PCI_REQ#A 1 2
13,21 OVT# 3 4 74LVC07A
2.7K/8P4R 12,21 KBRST# 5 6
12,21 A20GATE
7
RN66 7 8
14,15 ACK64# 1 2
14 REQ64#1 3 4 8.2K/8P4R VCC3_3 VCC3_3
14 REQ64#2 5 6 VCC3_3 VCC3_3 VCC3_3
15 REQ64#3 7 8
12,21 SERIRQ R276 8.2K
2.7K/8P4R R188 R198
13,19,24 AC_SDIN0 R147 10K 1K 1K
14
14
3 3
13,24 AC_SDIN1 R152 10K U18D U18C
12 ICHRST# 9 8 R188_U18 5 6 PCIRST# 7,16,17,21
74LVC07A 74LVC07A
VCC3_3
7
RN74 RN75
11,14,15 PIRQ#A 1 2 1 2
11,14,15 PIRQ#B 3 4 3 4
14,15 PIRQ#C 5 6 5 6
14,15 PIRQ#D 7 8 7 8
0/8P4R 8.2K/8P4R
RN76 RN77
1 2 1 2
3 4 3 4 VCC3_3
5 6 5 6
7 8 7 8
X0/8P4R 8.2K/8P4R
14
12 ICH_IRQ#A U20B
12 ICH_IRQ#B U18E 3 4
12 ICH_IRQ#C VCC5SBY 11 10
2 12 ICH_IRQ#D 74LVC14A 2
74LVC07A
12 ICH_IRQ#E
12 ICH_IRQ#F U20E
7
12 ICH_IRQ#G U19D 11 10
12 ICH_IRQ#H
9 8 74LVC14A
VCC3_3
74LVC06A
14
U18F
13 12
74LVC07A
7
1
Page Name: Pullup/Pulldown Rs and Unused Gates

Revision:
1.05
Page No:
Folsom, CA 95630
30 of 33
A B C D E
A B C D E
VCC12 " ATX POWER " VCC12- " ATX POWER "
VCC3_3 " ATX POWER " VCC5 " ATX POWER " VCC_5- " ATX POWER "
EC26 BC168 BC180 BC143 BC157 EC36 BC142 BC156 BC167 BC179
EC33 BC85 BC83 EC27 BC41 BC53 EC28 BC69 BC70
22UF 0.1UF 0.1UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF
22UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF 22UF 0.1UF 0.1UF
4 4
VCCVID
MC3 MC4 MC2 MC1 MC5 MC6 MC8 MC9 MC10 MC13 MC14 MC15 MC49 MC50 MC64 MC65
4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R 4.7UF/X7R
VCC3SBY " DIMM0 : Near Power Pins " VDDQ " Display Cache : Near the Power Pins "
MC31 MC30 MC11 MC16 BC76 BC66 BC39 BC19 BC8 BC10 MC35 MC34 MC33 MC32 BC101 BC102 BC103 BC104 BC112 BC111 BC110 BC108
4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
3 3
VCC1_8 " GMCH : 0.1U//0.01U at each conner and each side-center "
MC26 MC24 BC78 BC71 BC50 BC42 BC43 BC44 BC45 BC81 BC75 BC114 BC105 BC95 BC96 BC79 BC46 BC47
4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
VCC3SBY " GMCH : Near System Mem Quadrant " VDDQ " GMCH : Near Display Cache Quadrant " VCC3SBY " DIMM1 : Near Power Pins "
" Within 70 mils of GMCH "
BC87 BC82 BC80 BC74 BC88 BC65 BC48 BC51 BC52 BC94 BC91 BC97 BC92 BC93 BC98 MC12 MC17 MC27 MC25 BC11 BC20 BC40 BC67 BC77 BC84
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
VCC3_3 " ICH : 0.1U//0.01U at each conner " V3SB " ICH : Near Power Pins " VCC1_8 " ICH : Near Power Pins " V1_8SB " ICH : Near Power Pins "
2 2
BC131 BC132 BC138 BC121 BC150 BC149 BC147 BC124 MC57 MC59 BC204 BC205 BC206 BC207 BC115 BC113 BC116 BC208 BC209 BC210 BC211 BC212
0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
VCC3_3 " misc. " VCC3SBY " DIMM2 : Near Power Pins "
BC100 BC107 BC106 BC109 BC122 BC128 BC145 BC146 BC144 BC158 BC159 BC160 BC169 BC170 BC171 BC183 BC182 BC181 BC187 BC186 MC60 MC61 MC62 MC63 BC213 BC214 BC215 BC216 BC217 BC218
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 4.7UF 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
H1 HOLE A H3 HOLE A H4 HOLE A H5 HOLE A H6 HOLE A H7 HOLE A H8 HOLE A H9 HOLE A
1
1 8 1 8 1 8 1 8 1 8 1 8 1 8 1 8 Document: Intel(R) 815E Chipset Universal Socket 370 CRB 1
2 7 2 7 2 7 2 7 2 7 2 7 2 7 2 7
3 6 3 6 3 6 3 6 3 6 3 6 3 6 3 6 Page Name: Decoupling Caps
4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5
Revision:
1.05
Page No:
Folsom, CA 95630
31 of 33
A B C D E
A B C D E
4 21,27,29 VID[4:0] J4 4
VID0 1 2 VID1
3,29 JPR_VID[4:0] VID2 1 2 VID3
3 3 4 4
VID4 5 6
5 6
7 7 8 8
9 9 10 10
11 11 12 12
13 13 14 14
15 15 16 16 BSEL#1 4,29
17 17 18 18 BSEL#0 4,29
19 20 R_SMBDATA R_SMBDATA 6
19 20 R_SMBCLK
21 21 22 22 R_SMBCLK 6
23 24 JPR_VID0
21,24 PANSWIN JPR_VID1 23 24 JPR_VID2
25 25 26 26
JPR_VID3 27 28 JPR_VID4 R396 0
27 28
24,25 HWRST# 29 29 30 30 SMBDATA 9,10,13,21,24,30
SMBCLK 9,10,13,21,24,30
3 2x15 HDR 3
R397 0
VTT VTT VCC1_8 VCC3SBY VDDQ
J6 J7 J8 J9 J10
3 3 3 3 3
2 GTLREF 4,7 2 GTLREFA 4 2 HUBREF_ICH 12 2 2 CONN_AGPREF 8,11
1 1 1 1 1
HEADER_3 HEADER_3 HEADER_3 HEADER_3 HEADER_3
2 2

Page Name: Internal Debug headers
1 Last Revised: Page: Thursday, November 29, 2001 1
Revision:
1.05
Page No:
Folsom, CA 95630
32 of 33
A B C D E
A B C D E
4 4
VCC1_8 VCC1_8 V3SB
R409 R410 R411

4.7k 1K 20k
PWRBTN# 13,21
R412 1K
Q51
2N3904
Q51_Q52
R408
Q50
4 THERMTRIP# 2N3904
0 R416
3
Q52_R416 Q52 3
4,7 CPURST# 2N3904
2.2k
2 2
4,12 CPU_PWGD Stuff either R5 or R415. See p4.

R413
510
R415 0
N6395404 N6395403 4
R414 C198
1.3k X0.01uF
1
No-stuff C198 - debug site only Page Name: Thermtrip
Revision:
1.05
Page No:
Folsom, CA 95630
33 of 33
A B C D E

Intel 815e Schematics

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A B C D E

Intel® Pentium® III and FC-PGA Celeron™ Processor/815E Chipset

Revision 1.05 - Fab C

FRONT PANEL & CNR 24 obtained by calling

Page Name: Title Page

VRM 370-PIN SOCKET PROCESSOR CLOCK

USB PORT 1-4 USB

Page Name: Block Diagram

Page Name: 370-pin Socket Part 1

BSEL#1 BSEL#0 FSB

Place near AB36 R338 CMOSREF generation circuit

VTT Do not populate in assembly - debug sites only.

Page Name: VTT Decoupling

X10PF X10PF X10PF X10PF X10PF 26 R48 33

MC66 BC221 BC222 U29

C34 C31 C23 C22 X10PF

Platform Applications Engineering

VTT Debug sites only. SM_MAC#[4..7]

VCC3SBY VCC3SBY VCC3SBY VCC3SBY

VCC3_3 VCC12 VCC12

VCC3_3 VCC1_8 VCC1_8 V3SB V3SB V3SB V1_8SB V1_8SB

Page Name: ICH2 Part 1

Last Revised: Page: Thursday, November 29, 2001

VCC3_3 V3SB VCCRTC VCC5SBY VCMOS

VCC3_3 C91 BC125 D8 SS12/SMD

A 28 SLP_S5# SLP_S5# SDCS#1 SDCS#1 17

3 Y17 SUS_STAT# PDA2 E22

CP2 Page Name: ICH2 Part 2

Doc: Thursday, November 29, 2001

Platform Applications Engineering

AD8 B52 A52 C_BE#0 AD8 B52 A52 C_BE#0

AD8 B52 A52 C_BE#0

VCC5 VCC3_3 VCC1_8 DVO CONNECTOR

1.0uF 1.0uF 1.0uF 2.2uF 1.0uF 1.0uF 2.2uF

VCC3_3 VCC3_3 PDA[0..2]

Page Name: FWH and UDMA100 IDE

24 CNR_OC# R268 X0 VCC5DUAL

11 AGP_OC# R269 X0 F7 FUSE_1.0A

Page Name: USB

VCC3_3 VCC5 VCC5_AUDIO

BC140 BC139 BC136 BC129

0.1UF 0.1UF 0.1UF 0.1UF

"SINGLE POINT CONNECTION"

Page Name: AC’97 Codec

Stereo HP/Spkr out

C78 R105 FB14

Line_In Analog Input CD Analog Input

VCC12- VCC12 VCC5

VCC5 VCC5 VCC5 VCC5 VCC5 VCC5 VCC5

R92 R99 R94 R93 R102 R101 BEAD

C60 C66 GAME_PORT

Power V3SB VCC5SBY VCC5 VCC3_3 VCC12-VCC5SBY VCC12V3SB VCC5

25,32 HWRST# 1 RESET SMB2 SMB1

21 BEEP Q19 R231 68

VCC3_3 VCC5SBY VCC5 V3SB

R245 100 13 12 13 12 VCC5SBY

VCC5SBY VCC12 VCC3_3

VCC5 R360 VCC12

C175 C176 C177 C178 C179 C180 C181

This takes the place of

Document: Intel(R) 815E Chipset Universal Socket 370 CRB

VCC5SBY VCC12 VCC3_3 VCC5 VCC2_5

Page Name: VRegs: Duals, 3.3SB, 2.5, VCMOS

12,24 PRI_DWN# 5 6 PRI_DWN_RST# 19