Verilog HDL Lab Manual

Verilog HDL Lab Manual Dated: 29/04/2011
FPGA DESIGN FLOW
8.1 Programmable Logic Design Flow
Design Specifications
Design Entry
Functional
Simulation RTL Model
(Zero Delay)
Target Device
Libraries (Vender
Synthesis
T Specific)
Gate level Gate level
E description using
S Simulation
target library cells Design Constraints
T
Area / Speed
B
E Gate level Model
N
C Timing Mapping +
H Simulation Translation Target Device
(Gate + Gate level model to Libraries (Vender
Interconnect device architecture Specific)
Delays)
Place and Route
Placing the design in Design Constraints
device while optimizing Area / Speed
it for speed and area
Programming file
generation
Libraries Bit Stream
(Simprims
and
Unisims) Download onto
FPGA/ CPLD
Prepared By:
Parag Parandkar Asst. Prof. ECE Dept., CDSE, Indore (M.P.)
parag.vlsi@gmail.com
FPGA Design Flow for Xilinx
The Design flow followed by Xilinx devices is as shown as under:
Xilinx FPGAs are reprogrammable and when combined with an HDL design flow can greatly reduce
the design and verification cycle.
Broadly the stages can be categorized as:

Prepared By:
1. Design Entry may have two alternatives:
a) Performing HDL coding for synthesis as the target.( Xilinx HDL Editor).
b) Using Cores(Xilinx Core Generator).
2. Functional Simulation of synthesizable HDL code (MTI ModelSim).
3. Design Synthesis ( Xilinx project navigator).
4. Design Implementation (Xilinx Design Manager).
The stages are linked as follows:
VERILOG HDL/Verilog
Code Design Entry
Functional Simulation
Synthesis
Post Synthesis Simulation
Implementation
Timing Simulation
Program onto FPGA
Design Entry
The first stage of Xilinx design flow is a design entry process. A design must be specified by using
either a schematic editor or HDL text-based tool.
Functional Simulation
Upon the finish of the design entry stage, the functional simulation of the design is being performed,
which is used to verify functionality of the design assuming no delays, whatsoever. This assumes no target
technology selection at this stage and hence assumes zero delay in simulation.
Complex designs must be intensively simulated, at different simulation points, during the design flow.
Simulation verifies the operation of the design before it is actually implemented as hardware. One of the most
prevalent methods for simulation is testbenching. Testbenches (VERILOG HDL) or text fixtures (Verilog) are
used to specify circuit stimuli and responses.
Roughly, simulation can be divided as functional and timing simulation. Primarily, the functional simulation
verifies that the design’s specifications are correctly understood and coded. Timing information, produced
Prepared By:
during the device implementation stage, is not available during the functional simulation. Functional simulation
can be used after synthesis, too.
Comparison between the pre- and post-synthesis simulations’ results checks the results of the HDL compiler’s
work and the HDL code’s correctness.
Timing simulation operates with the real delays (results of device implementation) and is used for verification
of implemented design. Timing data are given in an .sdf file (Standard Delay Format).
Xilinx supports functional and timing simulations at different points of the design flow:
Ø Register Transfer Level (RTL) simulation.
Ø Post-synthesis functional simulation (Pre-NGDBuild).
Ø Post-implementation back-annotated timing simulation.
Design Synthesis
After this process, the synthesis is performed. Here for the first time in the design flow the target
technology (choice of a particular FPGA device family) is being performed. This target technology selection
will remain the same, henceforth in the design flow, upto the final implementation stage, where finally
generated Bit stream file gets downloaded onto that FPGA.
The output of the synthesis process is creation of gate level netlist. This refers to the EDIF
implementation netlist of the FPGA design. Besides the EDIF implementation netlist, the XNF (Xilinx netlist
format) netlist can be used as well.
Although the XNF is now becoming rather obsolete. The EDIF netlist is used as an input file to the
Xilinx Implementation tool and specifies how the core will be implemented.
The Electronic Design Interchange Format (EDIF) is a format used to exchange design data between different
CAD systems. In the world of FPGA design, it is used for interchange of data between different EDA
(Electronic Design Automation) software tools. EDIF files are used for FPGA implementation only. They are
the result of design synthesis and can be generated from different design entry EDA tools: schematic or HDL
design tools. EDIF files are inputs to the Xilinx implementation tools during the translation step (NGDBuild).
Design Implementation
Design Implementation includes the following steps:
i) Translate
ii) Map
iii) Place and Route
In the Translate step, which is the first step in the implementation process, EDIF netlist must be further
converted into Native Generic Database file (NGD), by means of a program called NGDBuild. The NGD file
resulting from an NGDBuild run contains the logical description of the design that can be mapped into a
targeted Xilinx FPGA device family. It is important to stress that NGDBuild merges all available EDIF netlists
from the working directory. This is actually the step where the black-box netlist becomes merged with the rest
of FPGA design.
In the next stage, the Map stage, the NGD file is an input into a MAP program that maps logical design
to a Xilinx FPGA. The output of the MAP program is an NCD (Native Circuit Description) file. The NCD is a
physical representation of the design mapped to the components of internal FPGA architecture.
The mapped design is ready to be placed and routed. The PAR program does this job. The input to PAR
is a mapped (not routed) NCD file, while the output is a fully routed NCD file.
Review reports are generated by the Implement Design process, such as the Map Report or Place &
Route Report, and change any of the following to improve your design:
Prepared By:
Ø Process properties
Ø Constraints
Ø Source files
Synthesis and again implementation of the design is being made until design requirements are met.
Timing verification of the design can be made at different points in the design flow as follows:
i) Run static timing analysis at the following points in the design flow:
Ø After Map.
Ø After Place and Route.
ii) Running Timing Simulations at the following points in the design flow:
Ø After Map (for a partial timing analysis of CLB and IOB delays).
Ø After Place and Route (for full timing analysis of block and net delays).
Program onto FPGA

Programming on the Xilinx device can be made as follows:
Ø Creation of a programming file (BIT) to program FPGA.
Ø Generate a PROM, ACE, JTAG file for debugging or to download to the device.
Ø Use iMPACT to program the device through programming cable.
Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with the configuration
bitstream. The configuration bitstream is generated from the fully routed NCD file, by means of a BitGen
program. The output of BitGen is a binary file with the .BIT extension that can be formatted for different
PROM devices.
Prepared By:
EXPERIEMENT NO. 1
Simulation using all the modeling styles and Synthesis of all the logic gates using
Verilog HDL
AIM:
Perform Zero Delay Simulation of all the logic gates
written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. then,
Synthesize each one of them on two different EDA tools.
Electronics Design Automation Tools used:

i) FPGA Advantage 3.1 (includes Model Sim simulation tool and Leonardo
Spectrum Synthesis Tool)
ii) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).
Block Diagram:
A And, Nand,
Or, Nor, C
Xor, Xnor
B
Truth table:
And Gate: Or Gate:
A B Y A B Y
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
Nand Gate: Nor Gate:

A B Y A B Y
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
Prepared By:
Xor Gate: Xnor Gate:

A B Y A B Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
Boolean Equation:
And Gate: Y = (A.B) Or Gate: Y = (A + B)

Nand Gate: Y = (A.B)’ Nor Gate: Y = (A+B)’
Xor Gate: Y = A.B’ + A’.B Xnor Gate: Y = A.B + A’.B’
Verilog Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):
Module andg(a,b,c);
input a,b;
output c;
assign c = a & b;
endmodule
Module andg1(a,b,c);
input a,b;
always(a,b)
begin
if (a==1’b0 or b == 1’b0)
c = 1’b0;
else if (a==1’b0 or b == 1’b1)
c = 1’b0;
c = 1’b0;
c = 1’b1;
end
endmodule
Or gate(Dataflow, behavioral modeling):
Module org (a,b,c);

input a,b;
output c;
assign c = a | b;
endmodule
Prepared By:
Nand Gate (In Dataflow modeling):
Module nandg (a,b,c);

input a,b;
output c;
assign c = ~(a & b);

endmodule
Nor Gate (In Dataflow modeling):

Module norg (a,b,c);
input a,b;
output c;
assign c = ~(a | b);

endmodule
Xor gate(In Dataflow modeling):
Module xorg (a,b,c);

input a,b;
output c;
assign c = a ^ b;
endmodule
Module xorg2 (a,b,c);

input a,b;
output c;
assign c = (~a & b) | (a & ~b);

endmodule
Xnor Gate (In Dataflow modeling):

Module xnorg (a,b,c);
input a,b;
output c;
assign c = ~(a ^ b);

endmodule
Test Bench (Applicable to all the logic gates):

module nandg_tst_v;
reg a;
reg b;
wire c;
nandg uut (
Prepared By:
.a(a),
.b(b),
.c(c)
);
initial
begin
a = 0;
b = 0;
#100 a = 0;
b = 1;
#100 a = 1;
b = 0;
#100 a = 1;
b = 1;
end
endmodule
Simulation Waveform:
Nand Gate:
Synthesis (Xor gate):
Prepared By:
EDA Tool Name: Xilinx Project Navigator – 8.1
Synthesis Report (Xilinx project Navigator):
===============================================================
* Synthesis Options Summary *
===============================================================
---- Source Parameters
Input File Name : "xorg.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters

Output File Name : "xorg"
Output Format : NGC
Target Device : xc3s50-5-pq208
* Final Report *
===============================================================
Final Results
RTL Top Level Output File Name : xorg.ngr
Top Level Output File Name : xorg
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Prepared By:
Design Statistics
# IOs :3
Cell Usage :
# BELS :1
# LUT2 :1
# IO Buffers :3
# IBUF :2
# OBUF :1
=========================================================================
Device utilization summary:

---------------------------
Selected Device : 3s50pq208-5
Number of Slices: 1 out of 768 0%

Number of 4 input LUTs: 1 out of 1536 0%
Number of IOs: 3
Number of bonded IOBs: 3 out of 124 2%
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.760ns
Prepared By:
EXPERIEMENT NO. 2
Simulation using all the modeling styles and Synthesis of 1-bit half adder and 1-bit
Full adder using verilog HDL
AIM:
Perform Zero Delay Simulation of 1-bit half adder and 1-bit Full adder written in behavioral, dataflow and
structural modeling style in VERILOG HDL using a Test bench. Then, Synthesize each one of them on two
different EDA tools.

Block Diagram:
1-bit Half Adder:
A Half Adder Sum

(1-bit)
B Carry
1-bit Full Adder:
A Full Adder Sum

B (1-bit) Cout
Cin
Truth table:
Half Adder:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Prepared By:
Full Adder:
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Boolean Equation:
Half Adder:
Sum = A B
Carry = A.B
Full Adder:
Sum = A B Cin
Cout = A.B + A.Cin + B.Cin
VERILOG HDL Code:

Half Adder (Using dataflow, Behavioral Modeling):
module ha(a, b, s, co);

input a;
input b;
output s;
output co;
assign s = a ^ b;
assign co = a &b;
endmodule
module ha1(a, b, s, co);

input a;
input b;
output s;
output co;
reg s,co;
always @(a or b)
begin
s = a ^ b;
co = a &b;
end
endmodule
Prepared By:
Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):
module fa(a, b, cin, sum, cout);

input a;
input b;
input cin;
output sum;
output cout;
assign sum = a ^ b ^ cin;

assign cout = (a& b) |(b & cin) |(a & cin);
endmodule
module fa1(a, b, cin, sum, cout);

input a;
input b;
input cin;
output sum;
output cout;
reg sum,cout;
always @(a or b or cin)

begin
case ({a,b,cin})
3'b000: begin
sum = 1'b0;
cout = 1'b0;
end
3'b001: begin
sum = 1'b1;
cout = 1'b0;
end
3'b010: begin
sum = 1'b1;
cout = 1'b0;
end
3'b011: begin
sum = 1'b0;
cout = 1'b1;
end
3'b100: begin
sum = 1'b1;
cout = 1'b0;
end
3'b101: begin
sum = 1'b0;
cout = 1'b1;
end
3'b110: begin
Prepared By:
sum = 1'b0;
cout = 1'b1;
end
3'b111: begin
sum = 1'b1;
cout = 1'b1;
end
default: begin
sum = 1'b0;
cout = 1'b0;
end
endcase
end
endmodule
module fa2(a, b, cin, sum, cout);

input a;
input b;
input cin;
output sum;
output cout;
wire w1, w2, w3;
ha ha_i1 (.a(a),
.b(b),
.s(w1),
.co(w3)
);
ha ha_i2 (.a(w1),
.b(cin),
.s(sum),
.co(w2)
);
org org_i (.a(w2),

.b(w3),
.c(cout)
);
endmodule
VERILOG HDL Test Bench:
Half Adder:
module ha_tst_v;
reg a;
reg b;
wire s;
Prepared By:
wire co;
ha1 uut (
.a(a),
.b(b),
.s(s),
.co(co)
);
initial
begin
a = 0;
b = 0;
#100 a = 0;
b = 1;
#100 a = 1;
b = 0;
#100 a = 1;
b = 1;
end
endmodule;
Full Adder:
module fa_tst_v;
reg a;
reg b;
reg cin;
wire sum;
wire cout;
fa uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial
begin
a = 0;
b = 0;
cin = 0;
#100 a = 0;
b = 0;
cin = 1;
#100 a = 0;
b = 1;
cin = 0;
#100 a = 0;
Prepared By:
b = 1;
cin = 1;
#100 a = 1;
b = 0;
cin = 0;
#100 a = 1;
b = 0;
cin = 1;
#100 a = 1;
b = 1;
cin = 0;
#100 a = 1;
b = 1;
cin = 1;
end
endmodule
Half Adder:
Prepared By:
Full Adder:
Synthesis:
Half Adder:
Prepared By:
Full Adder:
Prepared By:
Synthesis Report (Xilinx Project Navigator):
Full Adder:
======================================================* Synthesis Options
Summary *
---- Source Parameters
Input File Name : "fa2.prj"

Output File Name : "fa2"
Output Format : NGC
===============================================================*
HDL Analysis *
===============================================================Analyzing top module
<fa2>.
Module <fa2> is correct for synthesis.
Analyzing module <ha> in library <work>.

Module <ha> is correct for synthesis.
Analyzing module <org> in library <work>.

Module <org> is correct for synthesis.
===============================================================* HDL
Synthesis *
===============================================================
Performing bidirectional port resolution...
Synthesizing Unit <ha>.

Related source file is "ha.v".
Found 1-bit xor2 for signal <s>.
Unit <ha> synthesized.
Synthesizing Unit <org>.

Related source file is "org.v".
Unit <org> synthesized.
Synthesizing Unit <fa2>.
Related source file is "fa.v".
Unit <fa2> synthesized.
===============================================================
HDL Synthesis Report
Macro Statistics
Prepared By:
# Xors :2
1-bit xor2 :2
======================================================
* Advanced HDL Synthesis *
======================================================
Loading device for application Rf_Device from file '3s50.nph' in environment C:\Xilinx.
======================================================
Advanced HDL Synthesis Report
Macro Statistics
# Xors :2
1-bit xor2 :2
======================================================
* Final Report *
=====================================================================
Final Results
RTL Top Level Output File Name : fa2.ngr
Top Level Output File Name : fa2
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
=====================================================================

---------------------------
Number of Slices: : 1 out of 768 0%

Number of 4 input LUTs : 2 out of 1536 0%
Number of IOs: :5
Number of bonded IOBs: : 5 out of 124 4%
Prepared By:
EXPERIEMENT NO. 3
Simulation using all the modeling styles and Synthesis of 2:1 Multiplexer and 4:1
Multiplexer using VERILOG HDL
Aim:
Perform Zero Delay Simulation of 2:1 Multiplexer and 4:1 Multiplexer written in behavioral, dataflow and
structural modeling style in VERILOG HDL using a Test bench. Then, Synthesize each one of them on two

Block Diagram:
2:1 Multiplexer:
A
2:1
Y
B Multiplexer
4:1 Multiplexer:
A
4:1
B Multiplexer Y
C
D
S1 S0
Truth table:
Prepared By:
2:1 Multiplexer:
S A B Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
4:1 Multiplexer:
A B Y
0 0 A
0 1 B
1 0 C
1 1 D
Boolean Equation:
2:1 Multiplexer:
Y = A.S’ + B.S
4:1 Multiplexer:
Y = A.S1’.S0’ + B.S1’.S0 + C.S1.S0’ + D.S1.S0
VERILOG HDL Code:

2:1 Multiplexer ( in dataflow and behavioral modeling style) :
module mux21(a, b, s, c);
input a;
input b;
input s;
output c;
assign c = s ? a : b;
endmodule
module mux21a(a, b, s, c);

input a;
input b;
input s;
output c;
Prepared By:
reg c;
always @(a or b or s)
begin
if (s)
c = a;
else
c = b;
end
endmodule
4:1 Multiplexer( in behavioral, dataflow and structural modeling styles):
module mux41(a, s,c);

input [3:0] a;
input [1:0] s;
output c;
assign c = (!s[0] & !s[1] & a[0]) | (s[0] & !s[1] & a[1]) | (!s[0] & s[1] & a[2]) | (s[0] &
s[1] & a[3]);
endmodule
module mux41a (a,s,c);

input [3:0] a;
input [1:0] s;
output c;
reg c;
always @(a or s)
begin
case(s)
2'b00: c = a[0];
2'b01: c = a[1];
2'b10: c = a[2];
2'b11: c = a[3];
default: c = a[0];
endcase
end
endmodule
module mux41b (a,s,c);

input [3:0] a;
input [1:0] s;
output c;
wire w1,w2;
mux21 mux21_i1 (.a(a[0]),

Prepared By:
.b(a[1]),
.s(s[1]),
.c(w1)
);
mux21 mux21_i2 (.a(a[2]),

.b(a[3]),
.s(s[1]),
.c(w2)
);
mux21 mux21_i3 (.a(w1),

.b(w2),
.s(s[0]),
.c(c)
);
endmodule

2:1 Multiplexer:
module mux21_tst_v;
reg a;
reg b;
reg s;
wire c;
mux21 uut (
.a(a),
.b(b),
.s(s),
.c(c) );
initial
begin
a = 0;
b = 1;
s = 0;
#100
s = 1;
end
endmodule
4: 1 Multiplexer:
module mux41_tst_v;
reg [3:0] a;
reg [1:0] s;
wire c;
Prepared By:
mux41 uut (
.a(a),
.s(s),
.c(c)
);
initial
begin
a = 4'b0101;
s = 2'b00;
#100 s = 2'b00;
#100 s = 2'b01;
#100 s = 2'b10;
#100 s = 2'b11;
end
endmodule
Mux41:
Prepared By:
Synthesis:
2 :1 Multiplexer:
4 :1 Multiplexer:
Prepared By:
Synthesis Report:
===============================================================*
Synthesis Options Summary *
===============================================================---- Source Parameters
Input File Name : "mux41.prj"
Prepared By:

Output File Name : "mux41"
Output Format : NGC
===============================================================
* HDL Compilation *
===============================================================
Compiling verilog file "mux21.v" in library work
Module <mux21> compiled
Compiling verilog file "mux41.v" in library work
Module <mux21a> compiled
Module <mux41> compiled
Module <mux41a> compiled
Module <mux41b> compiled
No errors in compilation
Analysis of file <"mux41.prj"> succeeded.
===============================================================
* Final Report *
===============================================================
Final Results
RTL Top Level Output File Name : mux41.ngr
Top Level Output File Name : mux41
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :3
# LUT3 :2
# MUXF5 :1
# IO Buffers :7
# IBUF :6
# OBUF :1
===============================================================

---------------------------
Prepared By:
Number of Slices: 1 out of 768 0%
Number of 4 input LUTs: 2 out of 1536 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 124 5%
Prepared By:
EXPERIEMENT NO. 4
Simulation and Synthesis of 1:4 Demultiplexer using VERILOG HDL
Aim:
Perform Zero Delay Simulation 1:4 Demultiplexer in VERILOG HDL using a Test bench. Then, Synthesize
on two different EDA tools.

Block Diagram:
1:4
A Demultiplexer Y
Truth Table:
Input Select Output

A 00 Y(0)
B 01 Y(1)
C 10 Y(2)
D 11 Y(3)
Boolean Equation:
Y(3) = A.S.(1)’.S(0)’
Y(2) = B.S.(1)’.S(0)
Y(1) = C.S.(1).S(0)’
Y(0) = D.S.(1).S(0)
VERILOG HDL Code:

module demux12(a, s, c);
Prepared By:
input a;
input s;
output [1:0] c;
assign c[1] = a & ~ s;
assign c[0] = a & s;
endmodule
module demux12a(a, s, c);

input a;
input s;
output [1:0] c;
reg c;
always @(a or s)
begin
if (s)
c = (a & ~s);
else
c = (a & s);
end
endmodule
VERILOG HDL test bench:

module demux12_tst_v;
reg a;
reg s;
wire [1:0] c;
demux12 uut (
.a(a),
.s(s),
.c(c) );
initial
begin
a = 0;
s = 0;
#10; s = 1;
end
endmodule
Prepared By:
Synthesis:
Prepared By:
EXPERIEMENT NO. 5
Simulation and Synthesis of 2:4 Decoder using VERILOG HDL
Aim:
Perform Zero Delay Simulation 2:4 Decoder in VERILOG HDL using a Test bench. Then, Synthesize on two

Block Diagram:
2:4
A Decoder Y
Truth Table:
A Y
00 0001
01 0010
10 0100
11 1000
Boolean Equation:
Y(0) = A(1)’. A(0)’

Y(1) = A(1)’.A(0)
Y(2) = A(1).A(0)’
Y(3) = A(1). A(0)
VERILOG HDL Code:

Prepared By:
module decoder24 (a,b);

input [1:0] a;
output [3:0]b;
reg [3:0] b;
always @(a)
begin
b[3] = a[1] & a[0];
b[2] = !a[1] & a[0];
b[1] = a[1] & !a[0];
b[0] = !a[1] & !a[0];
end
endmodule

module decoder_tst_v;
reg [1:0] a;
wire [3:0] b;
decoder24 uut (
.a(a),
.b(b)
);
initial
begin
a = 2'b00;
#100 a = 2'b01;
#100 a = 2'b10;
#100 a = 2'b11;
end
endmodule
Prepared By:
Synthesis:
Prepared By:
EXPERIEMENT NO. 6
Simulation and Synthesis of 4:2 Encoder using VERILOG HDL
Aim:
Perform Zero Delay Simulation 4:2 Encoder in VERILOG HDL using a Test bench. Then, Synthesize on two

Block Diagram:
A 4:2 Y
Encoder
Truth Table:
A Y
1000 00
0100 01
0010 10
0001 11
Boolean Equation:
Y(1) = A(1) + A(0)
Y(0) = A(2) + A(0)
VERILOG HDL Code:
module encoder24(a, b);

input [3:0] a;
output [1:0] b;
reg [1:0] b;
always @(a)
Prepared By:
begin
case (a)
4'b0001: b = 2'b00;
4'b0010: b = 2'b01;
4'b0100: b = 2'b10;
4'b1000: b = 2'b11;
default: b = 2'b00;
endcase
end
endmodule

module encoder_tst_v;
reg [3:0] a;
wire [1:0] b;
decoder24 uut (
.a(a),
.b(b)
);
initial
begin
a = 4'b0001;
#100 a = 4'b0010;
#100 a = 4'b0100;
#100 a = 4'b1000;
#100 $stop;
end
endmodule
Prepared By:
Synthesis:
Prepared By:
EXPERIEMENT NO. 7
Simulation and Synthesis of 4:2 Priority Encoder using VERILOG HDL
Aim:
Perform Zero Delay Simulation 4:2 Priority Encoder in VERILOG HDL using a Test bench. Then, Synthesize
on two different EDA tools.

Block Diagram:
4:2 Y
A Priority
Encoder
Truth Table:
A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1
A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 1
Prepared By:
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
Boolean Equation:
Y(1) = A(3) + A(2)
Y (0) = A(2)’.A(1) + A(3).A(2) + A(3).A(0)
VERILOG HDL Code:
module pri_encoder42(a, b);

input [3:0] a;
output [1:0] b;
reg [1:0] b;
always @(a)
begin
if (a[3])
b = 2'b00;
else if (a[2])
b = 2'b01;
else if(a[1])
b = 2'b10;
else if (a[0])
b = 2'b11;
end
endmodule
module pri_encoder_tst_v;
reg [3:0] a;
wire [1:0] b;
pri_encoder42 uut (
.a(a),
.b(b)
);
initial
begin
a = 4'b0001;
#10 a = 4'b0010;
#10 a = 4'b0011;
#10 a = 4'b0100;
#10 a = 4'b0101;
#10 a = 4'b0110;
#10 a = 4'b0111;
Prepared By:
#10 a = 4'b1000;
#10 a = 4'b1001;
#10 a = 4'b1010;
#10 a = 4'b1011;
#10 a = 4'b1100;
#10 a = 4'b1101;
#10 a = 4'b1110;
#10 a = 4'b1111;
#10 $stop;
end
endmodule
Prepared By:
Synthesis:
Prepared By:
EXPERIEMENT NO. 8
Simulation and Synthesis of magnitude comparator 1-bit using VERILOG HDL
Aim:
Perform Zero Delay Simulation of magnitude comparator 1-bit in VERILOG HDL using a Test bench. Then,
Synthesize on two different EDA tools.

Block Diagram:
AgtB
A Magnitude
Comparator AltB
B
1-bit AeqB
Truth Table:
A B AgtB AltB AeqB

0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
Boolean Equation:
AgtB = A.B’
AltB = A’.B
AeqB = A’.B’ + A.B
VERILOG HDL Code:
module magcomp1(a, b, agtb, aeqb, altb);

input a;
input b;
output agtb;
Prepared By:
output aeqb;
output altb;
assign agtb = (a > b);

assign altb = (a < b);
assign aeqb = (a ==b);
endmodule

module magcomp1_tst_v;
reg a;
reg b;
wire agtb;
wire aeqb;
wire altb;
magcomp1 uut (
.a(a),
.b(b),
.agtb(agtb),
.aeqb(aeqb),
.altb(altb) );
initial
begin
a = 0;
b = 0;
#100 a = 0; b = 1;
#100 a = 1; b = 0;
#100 a = 1; b = 1;
end
endmodule
Prepared By:
Synthesis:
EDA Tool Name: Xilinx Project Navigator – 8.1:
Prepared By:
EXPERIEMENT NO. 9
Simulation and Synthesis of D flip flop using VERILOG HDL
Aim:
Perform Zero Delay Simulation of d flip flop in VERILOG HDL using a Test bench. Then, Synthesize on
EDA tool.

VERILOG HDL Code:

D-flip flop with asynchronous and synchronous reset:
module dff(d, clk, reset, q);
input d;
input clk;
input reset;
output q;
reg q;
always @(posedge clk or posedge reset)

begin
if (reset)
q <= 1'b0;
else
q <= d;
end
endmodule
module dff_a(d, clk, reset, q);

input d,clk,reset;
output q;
reg q;
always@(posedge clk)
begin
if (reset)
q <= 1'b0;
else
q <= d;
end
endmodule
Prepared By:
Test Bench of D flip flop asynchronous/synchronous reset:
module dff_tst_v;
reg d;
reg clk;
reg reset;
wire q;
dff uut (
.d(d),
.clk(clk),
.reset(reset),
.q(q)
);
initial
begin
d = 0;
clk = 1;
reset = 1;
#20 reset = 0;
d = 1;
#10 d = 0;
#20 d = 1;
#10 d = 0;
end
always
#5 clk = ~ clk;
endmodule
Prepared By:
Synthesis:
Prepared By:
EXPERIEMENT NO. 10
Simulation and Synthesis of JK, T Flip Flop using VERILOG HDL
Aim:
Perform Zero Delay Simulation of JK, T, Flip flop in VERILOG HDL using a Test bench. Then, Synthesize
on EDA tools.

i) FPGA Advantage 3.1 (includes Model Sim simulation tool)
VERILOG HDL Code:

JK-flip flop:
module jkff(j, k, clk, reset, q);
input j;
input k;
input clk;
input reset;
output q;
reg q;
begin
if(reset == 1'b1)
q <= 1'b0;
else
case ({j,k})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
default: q <= q;
endcase
end
endmodule
T-flip flop:
module tff(t, clk, reset, q);
input t;
input clk;
input reset;
output q;
reg q;
Prepared By:
always @(negedge clk or posedge reset)

begin
if (reset == 1'b1)
q <= 1'b0;
else if (t == 1'b1)
q <= ~ q;
else if (t == 1'b0)
q <= q;
end
endmodule
Test Bench of JK flip flop:

module jkff_tst_v;
reg j;
reg k;
reg clk;
reg reset;
wire q;
jkff uut (
.j(j),
.k(k),
.clk(clk),
.reset(reset),
.q(q) );
initial
begin
j = 0;
k = 0;
clk = 1;
reset = 1;
#20 reset = 0;
#10 j = 0;
k = 1;
#10 j = 1;
k = 0;
#10 j = 1;
k = 1;
end
always
#5 clk = ~ clk;
endmodule
Prepared By:
Test Bench of T flip flop:
module tff_tst_v;
reg t;
reg clk;
reg reset;
wire q;
tff uut (
.t(t),
.clk(clk),
.reset(reset),
.q(q)
);
initial
begin
t = 0;
clk = 1;
reset = 1;
#20 reset = 1'b0;
t = 1'b1;
#20 t = 1'b0;
#30 t = 1'b1;
end
always
#5 clk = ~ clk;
endmodule
Prepared By:
JKFF:
TFF:
Prepared By:
Synthesis:
JKFF:
TFF:
Prepared By:
EXPERIEMENT NO. 11
Simulation and Synthesis of SISO, SIPO, PIPO shift registers using VERILOG
HDL
Aim:
Perform Zero Delay Simulation of SISO, SIPO, PIPO shift registers in VERILOG HDL using a Test bench.
Then, Synthesize on EDA tools.

VERILOG HDL Code:
SISO shift register:

module siso(sin, clk, reset, sout);
input sin;
input clk;
input reset;
output sout;
wire w1,w2,w3;
dff abc1 (.d(sin),
.clk(clk ),
.reset(reset),
.q(w1)
);
dff abc2 (.d(w1),

.clk(clk),
.reset(reset),
.q(w2)
);
dff abc3 (.d(w2),

.clk(clk),
.reset(reset),
.q(w3)
);
dff abc4 (.d(w3),

Prepared By:
.clk(clk),
.reset(reset),
.q(sout)
);
endmodule
module siso1(sin, clk, reset, sout);

input sin;
input clk;
input reset;
output sout;
reg sout;
reg r1,r2,r3;

begin
if (!reset)
begin
sout <= 1'b0;
r1 <= 1'b0;
r2 <= 1'b0;
r3 <= 1'b0;
end
else
begin
r1 <= sin;
r2 <= r1;
r3 <= r2;
sout <= r3;
end
end
endmodule
SIPO shift register:

module sipo(sin, clk, reset, pout);
input sin;
input clk;
input reset;
output [3:0] pout;
dff a1 (.d(sin),
.clk(clk ),
.reset(reset),
.q(pout[0])
);
dff a2 (.d(pout[0]),
Prepared By:
.clk(clk),
.reset(reset),
.q(pout[1])
);
.clk(clk),
.reset(reset),
.q(pout[2])
);
.clk(clk),
.reset(reset),
.q(pout[3])
);
endmodule
PIPO:
module pipo(pin, clk, reset, pout);

input [3:0] pin;
input clk;
input reset;
output [3:0] pout;
reg [3:0] pout;
always @ (posedge clk or posedge reset)
begin
if (reset)
pout <= 4'b0000;
else
pout <= pin;
end
endmodule
Test Bench of SISO:

module siso_tst_v;
reg sin;
reg clk;
reg reset;
wire sout;
siso uut ( .sin(sin),
.clk(clk),
Prepared By:
.reset(reset),
.sout(sout)
);
initial
begin
sin = 0;
clk = 1;
reset = 1;
#20 reset = 0;
sin = 1'b1;
#10 sin = 1'b0;
#10 sin = 1'b1;
#10 sin = 1'b1;
#40;
end
always
#5 clk = ~ clk;
endmodule
Test Bench of SIPO:

module sipo_tst_v;
reg sin;
reg clk;
reg reset;
wire [3:0] pout;
sipo uut ( .sin(sin),

.clk(clk),
.reset(reset),
.pout(pout)
);
initial
begin
sin = 0;
clk = 1;
reset = 1;
#300
reset = 1'b0;
sin = 1'b1;
#100 sin = 1'b0;
#100 sin = 1'b1;
#100 sin = 1'b1;
end
Prepared By:
always
#50 clk = ~ clk;
endmodule
Test Bench for PIPO:

module pipo_tst_v;
reg [3:0] pin;

reg clk;
reg reset;
wire [3:0] pout;
pipo uut ( .pin(pin),

.clk(clk),
.reset(reset),
.pout(pout)
);
initial
begin
pin = 4'b0000;
clk = 1;
reset = 1;
#100 reset = 0;
pin = 4'b1010;
#100 pin = 4'b0110;
end
always
#50 clk = ~ clk;
endmodule
Prepared By:
SISO:
SIPO:
Prepared By:
PIPO:
Synthesis:
SISO:
Prepared By:
SIPO:
PIPO:
Prepared By:
EXPERIEMENT NO. 12
Simulation and Synthesis of Asynchronous counter and synchronous counter using

VERILOG HDL
Aim:
Perform Zero Delay Simulation of asynchronous and synchronous counter in VERILOG HDL using a Test
bench. Then, Synthesize on EDA tools.

iii) FPGA Advantage 3.1 (includes Model Sim simulation tool)
iv) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
VERILOG HDL Code:
Asynchronous up counter:
module asynccnt3 (clk, reset, count);

input clk;
input reset;
output [2:0] count;
tff a1 (.t(1'b1),
.clk (clk),
.reset (reset),
.q(count[0]) );
tff a2 (.t(1'b1),
.clk (count[0]),
.reset (reset),
.q (count[1]) );
tff a3 (.t(1'b1),
.clk (count[1]),
.reset (reset),
.q (count[2]) );
endmodule
Synchronous up counter:
module synccntr3(clk, reset, cnt_en, load, load_val, count);
input clk;
input reset;
input cnt_en;
input load;
input [2:0] load_val;
Prepared By:
output [2:0] count;
reg [2:0] count;

begin
if (reset)
count <= 3'b000;
else if (load)
count <= load_val;
else if (cnt_en)
count <= count + "001";
end
endmodule
Test Bench of Asynchronous up counter:
module asynccnt3_tst_v;
reg clk;
reg reset;
wire [2:0] count;
asynccnt3 uut ( .clk(clk),
.reset(reset),
.count(count)
);
initial
begin
clk = 1;
reset = 1;
#10 reset = 0;
#150;
end
always
#5 clk = ~ clk;
endmodule
Test Bench of Synchronous up counter:

module synccntr_tst_v;
reg clk;
reg reset;
reg cnt_en;
reg load;
reg [2:0] load_val;
Prepared By:
wire [2:0] count;
synccntr3 uut (
.clk(clk),
.reset(reset),
.cnt_en(cnt_en),
.load(load),
.load_val(load_val),
.count(count)
);
initial
begin
clk = 1;
reset = 1;
load = 0;
load_val = 0;
cnt_en = 0;
#10 reset = 0;
load = 1'b1;
load_val = 3'b011;
#10 cnt_en = 1'b1;
load = 1'b0;
#80 cnt_en = 1'b0;
end
always
#5 clk = ~ clk;
endmodule
Prepared By:
Prepared By:
Synthesis:
Prepared By:
Prepared By:

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Verilog HDL Lab Manual Dated: 29/04/2011

FPGA DESIGN FLOW

8.1 Programmable Logic Design Flow

Broadly the stages can be categorized as:

The stages are linked as follows:

Post Synthesis Simulation

Program onto FPGA

Program onto FPGA

Electronics Design Automation Tools used:

Nand Gate: Nor Gate:

Xor Gate: Xnor Gate:

And Gate: Y = (A.B) Or Gate: Y = (A + B)

Verilog Code (In different modeling styles):

Or gate(Dataflow, behavioral modeling):

Module org (a,b,c);

Nand Gate (In Dataflow modeling):

Module nandg (a,b,c);

assign c = ~(a & b);

Nor Gate (In Dataflow modeling):

assign c = ~(a | b);

Xor gate(In Dataflow modeling):

Module xorg (a,b,c);

Module xorg2 (a,b,c);

assign c = (~a & b) | (a & ~b);

Xnor Gate (In Dataflow modeling):

assign c = ~(a ^ b);

Test Bench (Applicable to all the logic gates):

Synthesis (Xor gate):

Synthesis Report (Xilinx project Navigator):

---- Target Parameters

Device utilization summary:

Selected Device : 3s50pq208-5

Number of Slices: 1 out of 768 0%

Minimum period: No path found

Electronics Design Automation Tools used:

A Half Adder Sum

1-bit Full Adder:

A Full Adder Sum

VERILOG HDL Code:

module ha(a, b, s, co);

module ha1(a, b, s, co);

Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):

module fa(a, b, cin, sum, cout);

assign sum = a ^ b ^ cin;

module fa1(a, b, cin, sum, cout);

always @(a or b or cin)

module fa2(a, b, cin, sum, cout);

org org_i (.a(w2),

VERILOG HDL Test Bench:

---- Target Parameters

Analyzing module <ha> in library <work>.

Analyzing module <org> in library <work>.

Synthesizing Unit <ha>.

Synthesizing Unit <org>.

Device utilization summary:

Selected Device : 3s50pq208-5

Number of Slices: : 1 out of 768 0%

Electronics Design Automation Tools used:

VERILOG HDL Code:

module mux21a(a, b, s, c);

4:1 Multiplexer( in behavioral, dataflow and structural modeling styles):

module mux41(a, s,c);

module mux41a (a,s,c);