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SCHOOL OF ELECTRONICS ENGINEERING, VIT UNIVERSITY

Assignment - VLSI
Verilog HDL based simple Digital Circuit
Modeling
Adithya Pulli
08bec258
11/1/2010

Simple Digital Circuits – Encoder, Decoder, MUX, Demux, adder, registers and counter are modeled
using verilog HDL. The circuits are functionally verified with the test benches.
8X3 Encoder
Abstraction level: Behavioural Modelling

Truth table:

I[7] I[6] I[5] I[4] I[3] I[2] I[1] I[0] O[2] O[1] O[0]
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

HDL Code:

module enc_8_3(o,i);
input [7:0]i;
output reg [2:0]o;

always @*
begin
case (i)
8'b10000000 : o=3'b000;
8'b01000000 : o=3'b001;
8'b00100000 : o=3'b010;
8'b00010000 : o=3'b011;
8'b00001000 : o=3'b100;
8'b00000100 : o=3'b101;
8'b00000010 : o=3'b110;
8'b00000001 : o=3'b111;
endcase
end

endmodule

Test bench code:

module tb_enc_3_8;
reg [7:0]i;
wire [2:0]o;

VLSI System Design – ECE301 Fall - 2010


enc_8_3 enc0 (o,i);

initial
begin
i=8'b10000000;
#10 i=8'b01000000;
#10 i=8'b00100000;
#10 i=8'b00010000;
#10 i=8'b00001000;
#10 i=8'b00000100;
#10 i=8'b00000010;
#10 i=8'b00000001;
end

initial
$monitor ($time," enc_input = %b enc_output = %b",i,o);
endmodule

Output:
Shell/command line:
# 0 enc_input = 10000000 enc_output = 000
# 10 enc_input = 01000000 enc_output = 001
# 20 enc_input = 00100000 enc_output = 010
# 30 enc_input = 00010000 enc_output = 011
# 40 enc_input = 00001000 enc_output = 100
# 50 enc_input = 00000100 enc_output = 101
# 60 enc_input = 00000010 enc_output = 110
# 70 enc_input = 00000001 enc_output = 111
Screen Shot:

VLSI System Design – ECE301 Fall - 2010


4X2 Priority Encoder
Abstraction level: Behavioural Modelling

Truth table:

I[3] I[2] I[1] I[0] O[1] O[0]


1 X X X 0 0
0 1 X X 0 1
0 0 1 X 1 0
0 0 0 1 1 1
HDL Code:

module pri_enc_4_2(o,i);
input [3:0]i;
output reg [1:0]o;
always @*
begin
casex (i)
4'b1xxx : o=2'b00;
4'b01xx : o=2'b01;
4'b001x : o=2'b10;
4'b0001 : o=2'b11;
endcase
end
endmodule

Test bench code:

module tb_pri_enc_4_2;
reg [3:0]i;
wire [1:0]o;
pri_enc_4_2 penc0 (o,i);
initial
begin
i=4'b0001;
#10 i=4'b0010;
#10 i=4'b0011;
#10 i=4'b0100;
#10 i=4'b0101;
#10 i=4'b0110;
#10 i=4'b0111;
#10 i=4'b1000;
#10 i=4'b1001;

VLSI System Design – ECE301 Fall - 2010


#10 i=4'b1010;
#10 i=4'b1011;
#10 i=4'b1100;
#10 i=4'b1101;
#10 i=4'b1110;
#10 i=4'b1111;
end
initial
$monitor ($time," enc_input = %b enc_output = %b",i,o);
endmodule

Output:
Shell/command line:
# 0 enc_input = 0001 enc_output = 11
# 10 enc_input = 0010 enc_output = 10
# 20 enc_input = 0011 enc_output = 10
# 30 enc_input = 0100 enc_output = 01
# 40 enc_input = 0101 enc_output = 01
# 50 enc_input = 0110 enc_output = 01
# 60 enc_input = 0111 enc_output = 01
# 70 enc_input = 1000 enc_output = 00
# 80 enc_input = 1001 enc_output = 00
# 90 enc_input = 1010 enc_output = 00
# 100 enc_input = 1011 enc_output = 00
# 110 enc_input = 1100 enc_output = 00
# 120 enc_input = 1101 enc_output = 00
# 130 enc_input = 1110 enc_output = 00
# 140 enc_input = 1111 enc_output = 00

Screen Shot:

VLSI System Design – ECE301 Fall - 2010


3X8 Decoder
Abstraction level: Behavioural Modelling

Truth table:

O[2] O[1] O[0] I[7] I[6] I[5] I[4] I[3] I[2] I[1] I[0]
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

HDL Code:

module dec_3_8(o,i);

input [2:0]i;
output reg [7:0]o;

always @*
begin
case (i)
3'b000 : o=8'b10000000;
3'b001 : o=8'b01000000;
3'b010 : o=8'b00100000;
3'b011 : o=8'b00010000;
3'b100 : o=8'b00001000;
3'b101 : o=8'b00000100;
3'b110 : o=8'b00000010;
3'b111 : o=8'b00000001;
endcase
end

endmodule

Test bench code:

module tb_dec_8_3;
reg [2:0]i;
wire [7:0]o;

VLSI System Design – ECE301 Fall - 2010


dec_3_8 dec0 (o,i);
initial
begin
i=3'b000;
#10 i=3'b001;
#10 i=3'b010;
#10 i=3'b011;
#10 i=3'b100;
#10 i=3'b101;
#10 i=3'b110;
#10 i=3'b111;
end
initial
$monitor ($time," dec_input = %b dec_output = %b",i,o);
endmodule

Output:
Shell/command line:
# 0 dec_input = 000 dec_output = 10000000
# 10 dec_input = 001 dec_output = 01000000
# 20 dec_input = 010 dec_output = 00100000
# 30 dec_input = 011 dec_output = 00010000
# 40 dec_input = 100 dec_output = 00001000
# 50 dec_input = 101 dec_output = 00000100
# 60 dec_input = 110 dec_output = 00000010
# 70 dec_input = 111 dec_output = 00000001
Screen Shot:

VLSI System Design – ECE301 Fall - 2010


8X1 Multiplexer
Abstraction level: Behavioural Modelling

Truth table:

S[2] S[1] S[0] O


0 0 0 I[0]
0 0 1 I[1]
0 1 0 I[2]
0 1 1 I[3]
1 0 0 I[4]
1 0 1 I[5]
1 1 0 I[6]
1 1 1 I[7]
HDL Code:

module mux_8_1(o,i,s);
input [7:0]i;
input [2:0]s;
output reg o;
always @*
begin
case (s)
3'b000 : o=i[0];
3'b001 : o=i[1];
3'b010 : o=i[2];
3'b011 : o=i[3];
3'b100 : o=i[4];
3'b101 : o=i[5];
3'b110 : o=i[6];
3'b111 : o=i[7];
endcase
end
endmodule

Test bench code:


module tb_mux_8_1;
reg [7:0]i;
reg [2:0]s;
wire o;
mux_8_1 mux0 (o,i,s);
initial
begin

VLSI System Design – ECE301 Fall - 2010


i=8'b11110000;s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;

#10 i=8'b10101010;s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;

end
initial
$monitor ($time," mux_input = %b sel = %b mux_output = %b",i,s,o);
endmodule

Output:

Shell/command line:

# 0 mux_input = 11110000 sel = 000 mux_output = 0


# 10 mux_input = 11110000 sel = 001 mux_output = 0
# 20 mux_input = 11110000 sel = 010 mux_output = 0
# 30 mux_input = 11110000 sel = 011 mux_output = 0
# 40 mux_input = 11110000 sel = 100 mux_output = 1
# 50 mux_input = 11110000 sel = 101 mux_output = 1
# 60 mux_input = 11110000 sel = 110 mux_output = 1
# 70 mux_input = 11110000 sel = 111 mux_output = 1
# 80 mux_input = 10101010 sel = 000 mux_output = 0
# 90 mux_input = 10101010 sel = 001 mux_output = 1
# 100 mux_input = 10101010 sel = 010 mux_output = 0
# 110 mux_input = 10101010 sel = 011 mux_output = 1
# 120 mux_input = 10101010 sel = 100 mux_output = 0
# 130 mux_input = 10101010 sel = 101 mux_output = 1
# 140 mux_input = 10101010 sel = 110 mux_output = 0

VLSI System Design – ECE301 Fall - 2010


# 150 mux_input = 10101010 sel = 111 mux_output = 1

Screen Shot:

1X8 De-Multiplexer
Abstraction level: Behavioural Modelling

Truth table:

S[2] S[1] S[0] O[0] O[1] O[2] O[3] O[4] O[5] O[6] O[7]
0 0 0 I 0 0 0 0 0 0 0
0 0 1 0 I 0 0 0 0 0 0
0 1 0 0 0 I 0 0 0 0 0
0 1 1 0 0 0 I 0 0 0 0
1 0 0 0 0 0 0 I 0 0 0
1 0 1 0 0 0 0 0 I 0 0
1 1 0 0 0 0 0 0 0 I 0
1 1 1 0 0 0 0 0 0 0 I

HDL Code:

module demux_1_8(o,i,s);

input i;
input [2:0]s;
output reg [7:0]o;

always @*
begin

VLSI System Design – ECE301 Fall - 2010


o=8'b0;
case (s)
3'b000 : o[0]=i;
3'b001 : o[1]=i;
3'b010 : o[2]=i;
3'b011 : o[3]=i;
3'b100 : o[4]=i;
3'b101 : o[5]=i;
3'b110 : o[6]=i;
3'b111 : o[7]=i;
endcase
end
endmodule

Test bench code:

module tb_demux_1_8;
reg i;
reg [2:0]s;
wire [7:0]o;

demux_1_8 demux0 (o,i,s);

initial
begin
i=1'b0;s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;

#10 i=1'b1;s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;

VLSI System Design – ECE301 Fall - 2010


end

initial
$monitor ($time," demux_input = %b sel = %b demux_output = %b",i,s,o);
endmodule

Output:

Shell/command line:

# 0 demux_input = 0 sel = 000 demux_output = 00000000


# 10 demux_input = 0 sel = 001 demux_output = 00000000
# 20 demux_input = 0 sel = 010 demux_output = 00000000
# 30 demux_input = 0 sel = 011 demux_output = 00000000
# 40 demux_input = 0 sel = 100 demux_output = 00000000
# 50 demux_input = 0 sel = 101 demux_output = 00000000
# 60 demux_input = 0 sel = 110 demux_output = 00000000
# 70 demux_input = 0 sel = 111 demux_output = 00000000
# 80 demux_input = 1 sel = 000 demux_output = 00000001
# 90 demux_input = 1 sel = 001 demux_output = 00000010
# 100 demux_input = 1 sel = 010 demux_output = 00000100
# 110 demux_input = 1 sel = 011 demux_output = 00001000
# 120 demux_input = 1 sel = 100 demux_output = 00010000
# 130 demux_input = 1 sel = 101 demux_output = 00100000
# 140 demux_input = 1 sel = 110 demux_output = 01000000
# 150 demux_input = 1 sel = 111 demux_output = 10000000

Screen Shot:

VLSI System Design – ECE301 Fall - 2010


4 Bit Ripple Carry Adder
Abstraction level: Structural Modelling

Circuit Diagram:

4bit Adder:

full_add:fa3
full_add:fa2
full_add:fa1
full_add:fa0 a
a sum
a sum b
a[3..0] a sum b carry carry
sum b carry c in
b[3..0] b carry c in
carry c in
c_in c in
sum[3..0]

Full Adder:

hf_add:ha1
hf_add:ha0 carry~0
a sum
carry
b c
a a sum
b b c
sum

c_in

Half Adder:

c~0
a
c
b

sum~0
sum

HDL Code:

module hf_add(sum,c,a,b);
input a,b;
output sum,c;
assign sum=a^b;
assign c=a&b;
endmodule

module full_add(sum,carry,a,b,c_in);

VLSI System Design – ECE301 Fall - 2010


input a,b,c_in;
output sum,carry;
wire s0,c0,c1;
hf_add ha0(s0,c0,a,b);
hf_add ha1(sum,c1,c_in,s0);
assign carry = c0|c1;
endmodule

module addr_4_bit(sum,carry,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output carry;
wire carry0,carry1,carry2;
full_add fa0(sum[0],carry0,a[0],b[0],c_in);
full_add fa1(sum[1],carry1,a[1],b[1],carry0);
full_add fa2(sum[2],carry2,a[2],b[2],carry1);
full_add fa3(sum[3],carry,a[3],b[3],carry2);
endmodule

Test bench code:


module tb_addr_4_bit;
reg [3:0]a,b;
reg c_in;
wire [3:0]sum;
wire carry;

addr_4_bit addr0 (sum,carry,a,b,c_in);

initial
begin
c_in=1'b0;a=4'b1000;b=4'b0101;
#10 b=0110;
#10 b=1110;
#10 a=1100; b=1111;
#10 b=0110;
#10 c_in=1'b1;
end
initial
$monitor ("%d + %d = %d , c_in = %b",a,b,{carry,sum},c_in);
endmodule

VLSI System Design – ECE301 Fall - 2010


Output:

Shell/command line:

# 8 + 5 = 13 , c_in = 0
# 8 + 14 = 22 , c_in = 0
# 8 + 6 = 14 , c_in = 0
# 12 + 7 = 19 , c_in = 0
# 12 + 14 = 26 , c_in = 0
# 12 + 14 = 27 , c_in = 1

Screen Shot:

D Flip Flop
Abstraction level: Behavioural Modelling

Truth table:

D Q Q’
0 0 1
1 1 0
Clk: Positive Edge Triggered
Preset: Active low, asynchronous
Clear: Active low, asynchronous

HDL Code:

module d_ff(out,out_bar,in,clk,prst,clr);
input in,clk,prst,clr;
output reg out,out_bar;

VLSI System Design – ECE301 Fall - 2010


always @(posedge clk, negedge prst, negedge clr)
begin
if (clr==1'b0)
begin
out=1'b0;
out_bar=~out;
end
else if (prst==1'b0)
begin
out=1'b1;
out_bar=~out;
end
else
begin
out=in;
out_bar=~out;
end
end
endmodule

Test bench code:


module tb_d_ff;
reg clk,clr,in;
reg prst;
wire out,out_bar;
d_ff dff0 (out,out_bar,in,clk,prst,clr);
initial
begin
clk = 1'b0;
clr = 1'b1;
#1 prst = 1'b0;
#15 prst = 1'b1;
end
always #10 clk=~clk;
always
begin
#15 in=1'b0;
#20 in=1'b1;
#20 clr=1'b0;
end
initial

VLSI System Design – ECE301 Fall - 2010


$monitor ($time," out = %b prst = %b in = %b clr = %b",out,prst,in,clr);
endmodule

Output:

Screen Shot:

D Latch
Abstraction level: Behavioural Modelling

Truth table:

D Q Q’
0 0 1
1 1 0
Clk: Positive Level Triggered
Preset: Active low, asynchronous
Clear: Active low, asynchronous

HDL Code:

module d_latch(out,out_bar,in,clk,prst,clr);
input in,clk,prst,clr;
output reg out,out_bar;
always @(clk, prst, clr)
begin
if (clr==1'b0)
begin
out=1'b0;

VLSI System Design – ECE301 Fall - 2010


out_bar=~out;
end
else if (prst==1'b0)
begin
out=1'b1;
out_bar=~out;
end
else if (clk==1'b1)
begin
out=in;
out_bar=~out;
end
end
endmodule

Test bench code:

module tb_d_ff;
reg clk,clr,in;
reg prst;
wire out,out_bar;
d_latch dlatch0 (out,out_bar,in,clk,prst,clr);
initial
begin
clk = 1'b0;
clr = 1'b1;
prst = 1'b1;
end

always #10 clk=~clk;

always
begin
in = 1'b1;
#15 in=1'b0;
#18 in=1'b1;
#15 in=1'b0;
end
initial
$monitor ($time," out = %b prst = %b in = %b clr = %b",out,prst,in,clr);
endmodule

VLSI System Design – ECE301 Fall - 2010


Output:

Screen Shot:

4bit Serial in Serial out register


Abstraction level: Behavioural Modelling

Circuit Diagram:

d_ff:d0
d in d_ff:d1
clk clk
out in d_ff:d2
pre prst
clk
clr clr out in d_ff:d3
prst
clk
clr out in
prst
clk out q
clr
prst out bar q_bar
clr

HDL Code:

module d_ff(out,out_bar,in,clk,prst,clr);
input in,clk,prst,clr;
output reg out,out_bar;
always @(posedge clk, negedge prst, negedge clr)
begin
if (clr==1'b0)
begin
out=1'b0;
out_bar=~out;
end
else if (prst==1'b0)

VLSI System Design – ECE301 Fall - 2010


begin
out=1'b1;
out_bar=~out;
end
else
begin
out=in;
out_bar=~out;
end
end
endmodule

module siso_4bit(q,q_bar,d,clk,pre,clr);
input d,pre,clr;
input clk;
output q,q_bar;
wire q0,q1,q2,q_bar0,q_bar1,q_bar2;

d_ff d0(q0,q_bar0,d,clk,pre,clr);
d_ff d1(q1,q_bar1,q0,clk,pre,clr);
d_ff d2(q2,q_bar2,q1,clk,pre,clr);
d_ff d3(q,q_bar,q2,clk,pre,clr);

endmodule

Test bench code:


module tb_siso_4bit;
reg d,pre,clr;
reg clk;
wire q,q_bar;
siso_4bit siso0 (q,q_bar,d,clk,pre,clr);
initial
begin
clk=1'b0;
pre=1'b1;
clr=1'b1;
end
always #10 clk=~clk;
initial
begin
#7 d=1'b1;
#20 d=1'b0;

VLSI System Design – ECE301 Fall - 2010


#20 d=1'b1;
#20 d=1'b0;
#150 clr=1'b0;
end
endmodule

Output:
Screen Shot:

Modulo 10 Counter
Abstraction level: Behavioural Modelling

State Diagram:

0000
1001 0001

1000 0010

0111 0011

0110 0100
0101

VLSI System Design – ECE301 Fall - 2010


HDL Code:

module mod_10_cntr(clk,rst,out);
input clk,rst;
output reg [3:0]out;
always @(posedge clk , negedge rst )
begin
if ((rst==1'b0) || (out==4'b1001))
out=3'b0;
else
out=out+1;
end
endmodule

Test bench code:

module tb_mod_10_cntr;
reg clk;
reg rst;
wire [3:0]out;
mod_10_cntr cntr0(clk,rst,out);
initial
begin
clk = 1'b0;
rst = 1'b0;
#5 rst = 1'b1;
end
always #10 clk=~clk;
initial #242 rst=1'b0;
initial
$monitor ($time," out = %b rst = %b",out,rst);
endmodule

Output:

Shell/command line:

# 0 out = 0000 rst = 0


# 5 out = 0000 rst = 1
# 10 out = 0001 rst = 1
# 30 out = 0010 rst = 1
# 50 out = 0011 rst = 1
# 70 out = 0100 rst = 1

VLSI System Design – ECE301 Fall - 2010


# 90 out = 0101 rst = 1
# 110 out = 0110 rst = 1
# 130 out = 0111 rst = 1
# 150 out = 1000 rst = 1
# 170 out = 1001 rst = 1
# 190 out = 0000 rst = 1
# 210 out = 0001 rst = 1
# 230 out = 0010 rst = 1
# 242 out = 0000 rst = 0

Screen Shot:

VLSI System Design – ECE301 Fall - 2010