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MEROM/CRESTLINE FORM FACTOR REFERENCE DESIGN REV 1.1 D D Crestline Crestline Fan IMVP VR Clocking
MEROM/CRESTLINE
FORM FACTOR REFERENCE DESIGN
REV 1.1
D
D
Crestline
Crestline
Fan
IMVP VR
Clocking
PWM
GFX VR
VCCP VR
Merom/Penryn
Header
Pages 52-54
PG 37
PG 49
PG 48
PG 5
478 uFCPGA
DB200
ITP
PG 38
CPU
CRT
PG 3,4
PG 20
Thermal
SYSTEM Discharge
DDR VR
Sensor
PG 56
PG 47
LVDS/ALS/BLI
PG 16
PG 5
FSB
Dual Channel
PG 17
DDR2
VGA
Crestline
SYSTEM VR
HDMI
Pages 13-15
1299
PG 46
LVDS
PG 18
FCBGA
SDVO
Pages
C
Azalia
HDMI
SLEEP CONTROL
C
6-11
Controller
Port Header
PG 57
USB0
PG 19
PG 29
X4 DMI
Port Header
C-LINK
interface
BATTERY CHARGER VR
USB1
CardBus
PG 51
PG 29
SATA HDD
PG 33,34
PG 30
Sky Forest
SATA PORT 0
33 Mhz PCI
SATA Dock
USB2
PG 45
Minicard 1
PG 26
ICH8-M
MOBILE POWER
C-LINK
PG 25
ON SEQUENCE
SATA PORT 2
PCIEx1
(LANE1)
Port Header
Dock
676
PG 55
USB3
PG 45
PCIEx1
(LANE2)
Minicard 2
PG 29
BGA
PG 25
PCIEx1
(LANE3)
PATA
ODD
Port Header
ODD
PG 62
Pages 21-24
PCIEx1
(LANE4)
PG 32
B
USB4
Interposer
Sky Forrest
B
PG
PG 29
PCIEx1
(LANE5)
PGS 68-69
USB 2.0
26
AIC
Expresscard & IR
GLCI
(LANE6)
MINICARD
DOCKING
USB5
Azalia
PG 45
Dock
PG 25
SPI
PG 45
Azalia
MINICARD
RJ45
RJ11
Nineveh LAN
LAN Switch
USB6
MDC
PG 35
PG 36
Page 27
PG 25
I/O Xpander
PG 39
BLUETOOTH
Nut Tree
Audio
Nut Tree
USB7
HDR
SPI
SPI
Dock
Page 28
PG 61
PG 45
PG 41
Audio
TPM
Flash
Flash
PG 58
PG 44
PG 36
PG 36
DOCKING
USB8
PG 45
SIO
SMC/KSC
Touch Pad
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
Sky Forest
Serial Header
PG 40
HDR
PG 42
USB9
Title
Title
Title
PG 26
PG 31
Title Page
Title Page
Title Page
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
SCN KBD
Touch Pad
A
A
A
Keyboard
HDR
PG 31
Date:
Date:
Date:
Sheet
Sheet
Sheet
1
1
1
of
of
of
64
64
64
5
4
3
2
1
LPC, 33MHz
SODIMM0
HDR
SODIMM1
5 4 3 2 1 OAKMONT FORM FACTOR REFERENCE PLATFORM D D SCHEMATIC ANNOTATIONS AND
5
4
3
2
1
OAKMONT FORM FACTOR REFERENCE PLATFORM
D
D
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
2
I
C / SMB Addresses
Voltage Rails
System Support
Device
Refdes
Binary
Hex
Bus *
POWER PLANE
VOLTAGE
ACTIVE IN
DESCRIPTION
Clock Generator
U32
1101
001x
D2
SMB_ICH_M3
Part Reference
Feature/Function
Strapping
+VBATA
9V-12.5V
S0 to S5, M0 to M-off
Battery Rail in Mobile Power Mode
DB200 Clock Buffer
U7
1101
110x
DC
SMB_ICH_M3
+VBAT
9V-12.5V
S0 to S5, M0 to M-off
Battery Rail in Mobile Power Mode
SO-DIMM0
J8
1010
000x
A0
SMB_ICH_M2
J6
ITP Connector
+V5A
5V
S0 to S5, M0 to M-off
SO-DIMM1
J9
1010
010x
A4
SMB_ICH_M2
J19
Boot BIOS Strap
+V5
5V
S0/M0, S3/M1, S3/M-off
SO-DIMM0 Thermal Sensor
J8
0011
000x
30
SMB_ICH_M2
J20
H8 Program Shunt header
Default (1 2)
+V5S
5V
S0/M0
SO-DIMM1 Thermal Sensor
J9
0011
010x
34
SMB_ICH_M2
J21
H8 External Reflash Connector
Default (1 2)
+V3.3A
3.3V
S0 to S5, M0 to M-off
DDR Thermal Sensor
U6
0100
110x
4C
SMB_ICH_M2
J23
SIO Program Header
+V3.3M
3.3V
S0 to S5, M0, M1
Board ID Port Expander
U35
0011
000x
30
SMB_BS
+V3.3
3.3V
S0/M0, S3/M1, S3/M-off
Ambient Light Sensor
J7
0111
001x
72
ALS
+V3.3S
3.3V
S0/M0
CPU Thermal Sensor
U19
0100
110x
4C
SMB_THRM
+V1.5S
1.5V
S0/M0
IMVP6 Amb. Temp. Sensor
U5
1001
101x
9A
SMB_THRM
+V1.8
1.8V
S0/M0, (S3 to S5)/M1, S3/M-off
DDR core
Battery
J4
0001
011x
16
SMB_BS
+V0.9
0.9V
S0/M0, (S3 to S5)/M1, S3/M-off
DDR command & control pull up.
H8
U60
TBD
TBD
SMB_ME
+V1.25M
1.25V
S0/M0, S3/M1, S3/M-off
TPM
U59
0100
1110
4E
LPC
+V1.25S
1.25V
S0/M0
5-CH-I2C HUB
U63
0011
xxxx
3x
SMB_ICH
+V1.05S
1.05V
S0/M0
GMCH, ICH core, and FSB rail
Minicard 1
J39
N/A
N/A
SMB_ICH_A1
Interposer Add-In-Cards
+V1.05M
1.05V
S0/M0, S3/M1, S3/M-off
Minicard 2
J32
N/A
N/A
SMB_ICH_A1
+VCC_CORE
0.700V-1.77V
S0/M0
CPU core rail
Express Card
J2000
N/A
N/A
SMB_ICH_A1
REF DEZ
Feature Support
Bus Supported
Power Requirements
C
+VCC_GFXCORE
0.7V-1.25V
S0/M1
GMCH Graphics core rail
C
Sky Forest
CR2000
LED_NETDETECT
N/A
CR2001
LED_PWR-GD/TURBO
N/A
+V5S
Page 63 & 64
CR2002
LED_S3
N/A
+V3.3S
J2000
EXPRESSCARD 54MM CONNECTOR
PCIEx1(LANE3)
+V3.3A
USB (PORT 2)
J2001
SPEAKER HEADER
AUDIO FROM CODEC (Azalia)
+V1.5S
Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander.
J2002
60-Pin Plug
N/A
The rest come out of EC.
SW2000
NETDETECT SWITCH
N/A
SW2001
LID SWITCH
N/A
U2007
IRDA
IR (LPC)
CR3000
LED_WWAN
N/A
Nut Tree
CR3001
LED_WLAN
N/A
Power supplied
CR3002
LED_BLUE TOOTH
N/A
Page 61
by LED driving
CR3003
LED_Caps-lock
N/A
SOT-23
SOT23-5
Net Naming Conventions
signals
1
1
5
CR3004
LED_Num-lock
N/A
Suffix
CR3005
LED_HDD Activity
N/A
#
= Active Low Signal
CR3006
LED_S3
N/A
3
As seen from top
2
CR3007
LED_Battery (Full/Low)
N/A
Prefix
CR3008
LED_PWR-GD/TURBO
N/A
H
= Host
MIC3000
Microphone
AUDIO FROM CODEC (Azalia)
2
3
4
M
= DDR Memory
SW3000
POWER_SWITCH
SYSTEM_GROUND
SW3001
RF_KILL_SWITCH
SYSTEM_GROUND
TP = Test Point (does not connect anywhere else)
ODD
50-PIN DVD RECEPTACLE (Short)
J4000
Connects to Oakmont PB
IDE
+V5S
Interposer
Page 62
50-PIN DVD RECEPTACLE (Long)
J4001
Connects to ODD
IDE
B
B
Power States
Wake Events
SIGNAL
SLP
SLP
SLP
S4
SLP
+V*A
+V*M
+V*
+V*S
Clocks
S3#
S4#
S5#
STATE#
M#
Wake Events
State Supported
STATE
RI# from serial port
S3
PME# from Cardbus
S3
S0 (Full ON) /M0
HIGH
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
Mini-card, Express-card wake event
S3
Wake on LAN
S3/M1
LID switch attached to SMC
S3
USB
S3
S3 (Suspend to RAM) / M1
LOW
HIGH
OFF
ON
HIGH
HIGH
HIGH
ON
ON
ON
HDA wake on ring
S3
SmLink for AOLII
S3
Hot Key from Scan matrix keyboard
S3
OFF
S4 (Suspend To Disk) /M1
LOW
HIGH
ON
OFF
ON
HIGH
HIGH
LOW
ON
PWRBTN#
S3
(DDR ON)
Netdetect
S3, S4, S5 / M1
S5 (Soft OFF) /M1
LOW
HIGH
HIGH
ON
ON
ON
OFF
ON
LOW
LOW
S3 (Suspend to RAM) / M-Off
LOW
HIGH
HIGH
HIGH
OFF
ON
OFF
OFF
LOW
ON
S4 (Suspend To Disk) /M-Off
LOW
OFF
OFF
OFF
OFF
LOW
HIGH
LOW
LOW
ON
S5 (Soft OFF) /M-Off
LOW
OFF
OFF
OFF
OFF
LOW
LOW
LOW
LOW
ON
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
A
Title
Title
Title
NOTES
NOTES
NOTES
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
Date:
Date:
Date:
Sheet
Sheet
Sheet
2
2
2
of
of
of
64
64
64
5
4
3
2
1
5 4 3 2 1 4,6,9,10,20,21,24,45,48,54,56 +V1.05S DATA GRP 0 DATA GRP 0 DATA GRP
5
4
3
2
1
4,6,9,10,20,21,24,45,48,54,56
+V1.05S
DATA GRP 0
DATA GRP 0
DATA GRP 1
DATA GRP 1
6
H_A#[35:3]
U22A
U22A
H_A#3
J4
H1
R613
R613
A[3]#
ADS#
H_ADS#
6
H_A#4
56
56
L5
E2
A[4]#
BNR#
H_BNR#
6
H_A#5
L4
G5
A[5]#
BPRI#
H_BPRI#
6
H_A#6
K5
A[6]#
H_A#7
M3
H5
D
A[7]#
DEFER#
H_DEFER#
6
D
H_A#8
N2
F21
A[8]#
DRDY#
H_DRDY#
6
H_A#9
J1
E1
A[9]#
DBSY#
H_DBSY#
6
H_A#10
N3
A[10]#
H_A#11
P5
F1
A[11]#
BR0#
H_BREQ#
6
H_A#12
P2
A[12]#
H_A#13
IERR#
L2
D20
A[13]#
IERR#
H_A#14
P4
B3
A[14]#
INIT#
H_INIT#
21
H_A#15
P1
A[15]#
H_A#16
R1
H4
A[16]#
LOCK#
H_LOCK#
6
M1
6
H_ADSTB#0
ADSTB[0]#
H_CPURST#
6,20
C1
6
H_REQ#[4:0]
RESET#
H_RS#[2:0]
6
H_REQ#0
H_RS#0
K3
F3
REQ[0]#
RS[0]#
H_REQ#1
H_RS#1
H2
F4
REQ[1]#
RS[1]#
H_REQ#2
H_RS#2
K2
G3
REQ[2]#
RS[2]#
H_REQ#3
J3
G2
REQ[3]#
TRDY#
H_TRDY#
6
H_REQ#4
L1
REQ[4]#
G6
6
H_A#[35:3]
HIT#
H_HIT#
6
H_A#17
Y2
E4
A[17]#
HITM#
H_HITM#
6
H_A#18
U5
A[18]#
H_A#19
R3
AD4
A[19]#
BPM[0]#
ITP_BPM#0
20
H_A#20
W6
AD3
A[20]#
BPM[1]#
ITP_BPM#1
20
H_A#21
U4
AD1
A[21]#
BPM[2]#
ITP_BPM#2
20
H_A#22
Y5
AC4
A[22]#
BPM[3]#
ITP_BPM#3
20
H_A#23
U1
AC2
A[23]#
PRDY#
ITP_BPM#4
20
H_A#24
R4
AC1
ITP_BPM#5
20
A[24]#
PREQ#
H_A#25
T5
AC5
A[25]#
TCK
ITP_TCK
20
H_A#26
T3
AA6
A[26]#
TDI
ITP_TDI
20
H_A#27
W2
AB3
+V1.05S
4,6,9,10,20,21,24,45,48,54,56
A[27]#
TDO
ITP_TDO
20
H_A#28
W5
AB5
A[28]#
TMS
ITP_TMS 20
H_A#29
Y4
AB6
A[29]#
TRST#
ITP_TRST#
20
H_A#30
U2
C20
A[30]#
DBR#
ITP_DBRESET#
20,55
H_A#31
V4
R612
R612
A[31]#
6
H_D#[63:0]
H_D#[63:0]
6
H_A#32
75
75
U22B
U22B
W3
A[32]#
H_A#33
H_D#32
AA4
THERMAL
THERMAL
H_D#0
E22
Y22
A[33]#
D[0]#
D[32]#
H_A#34
H_D#1
H_D#33
AB2
F24
AB24
C
A[34]#
D[1]#
D[33]#
C
H_A#35
H_D#2
H_D#34
AA3
D21
E26
V24
A[35]#
PROCHOT#
H_PROCHOT#
52
D[2]#
D[34]#
H_D#3
H_D#35
V1
A24
G22
V26
6
H_ADSTB#1
ADSTB[1]#
THERMDA
H_THERMDA
5
D[3]#
D[35]#
H_D#4
H_D#36
B25
F23
V23
THERMDC
H_THERMDC
5
D[4]#
D[36]#
PM_THRMTRIP# should connect
H_D#5
H_D#37
A6
G25
T22
21
H_A20M#
A20M#
D[5]#
D[37]#
H_D#6
H_D#38
A5
C7
to ICH8 and GMCH without
E25
U25
21
FERR#
THERMTRIP#
PM_THRMTRIP#
7,21
H_FERR#
D[6]#
D[38]#
H_D#7
H_D#39
C4
T-ing (No stub)
E23
U23
21
H_IGNNE#
IGNNE#
D[7]#
D[39]#
H_D#8
H_D#40
K24
Y25
D[8]#
D[40]#
H_D#9
H_D#41
D5
G24
W22
21
H_STPCLK#
STPCLK#
D[9]#
D[41]#
C6
H
H
CLK
CLK
H_D#10
H_D#42
J24
Y23
21
H_INTR
LINT0
D[10]#
D[42]#
H_D#11
H_D#43
B4
A22
J23
W24
21
H_NMI
LINT1
BCLK[0]
CLK_CPU_BCLK
37
D[11]#
D[43]#
H_D#12
H_D#44
A3
A21
H22
W25
21
H_SMI#
SMI#
BCLK[1]
CLK_CPU_BCLK#
37
D[12]#
D[44]#
H_D#13
H_D#45
F26
AA23
D[13]#
D[45]#
TP_CPU_RSVD01
H_D#14
H_D#46
M4
K22
AA24
RSVD[01]
D[14]#
D[46]#
TP_CPU_RSVD02
H_D#15
H_D#47
N5
H23
AB25
RSVD[02]
D[15]#
D[47]#
TP_CPU_RSVD03
T2
J26
Y26
RSVD[03]
6
H_DSTBN#0
DSTBN[0]#
DSTBN[2]#
H_DSTBN#2
6
TP_CPU_RSVD04
V3
H26
AA26
RSVD[04]
6
H_DSTBP#0
DSTBP[0]#
DSTBP[2]#
H_DSTBP#2
6
TP_CPU_RSVD05
B2
H25
U22
RSVD[05]
6
H_DINV#0
DINV[0]#
DINV[2]#
H_DINV#2
6
TP_CPU_RSVD06
C3
RSVD[06]
6
H_D#[63:0]
H_D#[63:0]
6
TP_CPU_RSVD07
D2
RSVD[07]
TP_CPU_RSVD08
H_D#16
H_D#48
D22
N22
AE24
RSVD[08]
D[16]#
D[48]#
TP_CPU_RSVD09
H_D#17
H_D#49
D3
K25
AD24
RSVD[09]
D[17]#
D[49]#
TP_CPU_RSVD10
H_D#18
H_D#50
F6
P26
AA21
RSVD[10]
D[18]#
D[50]#
H_D#19
H_D#51
R23
AB22
D[19]#
D[51]#
H_D#20
H_D#52
L23
AB21
D[20]#
D[52]#
H_D#21
H_D#53
M24
AC26
D[21]#
D[53]#
Merom Ball-out Rev 1a_Oakmont
Merom Ball-out Rev 1a_Oakmont
H_D#22
H_D#54
L22
AD20
D[22]#
D[54]#
H_D#23
H_D#55
Layout note:
M23
AE22
D[23]#
D[55]#
H_D#24
H_D#56
Comp0,2 connect with Zo=27.4ohm (14
P25
AF23
D[24]#
D[56]#
Layout Note:
H_D#25
H_D#57
mils width on SL, 18 mils width on
P23
AC25
D[25]#
D[57]#
MS), make trace length shorter than
1. Leave Escape routing for TP_CPU_RSVD[01:06] Signals for future functionality.
H_D#26
H_D#58
P22
AE21
D[26]#
D[58]#
0.5".
H_D#27
H_D#59
2. Route TP_CPU_RSVD[07:10] signals to TP via and place gnd via w/in 100mils.
T24
AD21
D[27]#
D[59]#
Comp1,3 connect with Zo=55ohm, make
4,6,9,10,20,21,24,45,48,54,56
+V1.05S
H_D#28
H_D#60
R24
AC22
D[28]#
D[60]#
trace length shorter than 0.5".
H_D#29
H_D#61
L25
AD23
D[29]#
D[61]#
H_D#30
H_D#62
T25
AF22
D[30]#
D[62]#
H_D#31
H_D#63
N25
AC23
B
D[31]#
D[63]#
R610
R610
B
L26
AE25
6
H_DSTBN#1
1K
DSTBN[1]#
H_DSTBN#3
6
1K
DSTBN[3]#
M26
AF24
1%
1%
6
H_DSTBP#1
DSTBP[1]#
DSTBP[3]#
H_DSTBP#3
6
N24
AC20
6
H_DINV#1
DINV[1]#
DINV[3]#
H_DINV#3
6
Layout note: Zo=55 ohm,
H_GTLREF
COMP0
R604
R604
27.4
27.4
1%
1%
AD26
R26
GTLREF
COMP[0]
CPU_TEST01
0.5" max for GTLREF.
C23
MISC
MISC
COMP1
U26
R605
R605
54.9
54.9
1%
1%
TEST1
COMP[1]
CPU_TEST02
COMP2
R521
R521
27.4
27.4
1%
1%
D25
AA1
TEST2
COMP[2]
R609
R609
TP_CPU_TEST03
COMP3
C24
Y1
R519
R519
54.9
54.9
1%
1%
TEST3
COMP[3]
2K
2K
CPU_TEST4
AF26
1%
1%
TEST4
TP_CPU_TEST05
AF1
E5
TEST5
DPRSTP#
H_DPRSTP#
7,21,52
TP_CPU_TEST06
A26
B5
TEST6
DPSLP#
H_DPSLP#
21
D24
DPWR#
H_DPWR#
6
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
B22
D6
ICH
ICH
BSEL[0]
PWRGOOD
H_PWRGD
21
7,37
MCH_BSEL0
B23
D7
H_CPUSLP#
6
7,37
MCH_BSEL1
BSEL[1]
SLP#
C21
AE6
7,37
MCH_BSEL2
BSEL[2]
PSI#
PSI#
52
Merom Ball-out Rev 1a_Oakmont
Merom Ball-out Rev 1a_Oakmont
Place C552 close to the CPU_TEST4 pin.
Make sure CPU_TEST4 routing is reference
to GND and away from other noisy signals.
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
Title
Title
Title
Merom (1 of 2)
Merom (1 of 2)
Merom (1 of 2)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Date:
Date:
Date:
Sheet
Sheet
Sheet
3
3
3
of
of
of
64
64
64
5
4
3
2
1
RESERVED
RESERVED
XDP/ITP SIGNALS
XDP/ITP SIGNALS
CONTROL
CONTROL
R623
R623
1K
1K
NO_STUFF
NO_STUFF
1%
1%
R611
R611
1K
1K
NO_STUFF
NO_STUFF
1%
1%
C550
C550
0.1uF
0.1uF
10%
10%
NO_STUFF
NO_STUFF
DATA GRP 2DATA
DATA GRP 2DATA
GRP 3
GRP 3
5 4 3 2 1 53,54,56 +VCC_CORE 53,54,56 +VCC_CORE U22C U22C A7 AB20 VCC[001] VCC[068]
5
4
3
2
1
53,54,56
+VCC_CORE
53,54,56
+VCC_CORE
U22C
U22C
A7
AB20
VCC[001]
VCC[068]
A9
AB7
VCC[002]
VCC[069]
A10
AC7
D
VCC[003]
VCC[070]
D
A12
AC9
VCC[004]
VCC[071]
A13
AC12
VCC[005]
VCC[072]
A15
AC13
VCC[006]
VCC[073]
A17
AC15
VCC[007]
VCC[074]
A18
AC17
VCC[008]
VCC[075]
A20
AC18
VCC[009]
VCC[076]
B7
AD7
VCC[010]
VCC[077]
B9
AD9
VCC[011]
VCC[078]
U22D
U22D
B10
AD10
VCC[012]
VCC[079]
B12
AD12
A4
P6
VCC[013]
VCC[080]
VSS[001]
VSS[082]
B14
AD14
A8
P21
VCC[014]
VCC[081]
VSS[002]
VSS[083]
B15
AD15
A11
P24
VCC[015]
VCC[082]
VSS[003]
VSS[084]
B17
AD17
A14
R2
VCC[016]
VCC[083]
VSS[004]
VSS[085]
B18
AD18
A16
R5
VCC[017]
VCC[084]
VSS[005]
VSS[086]
B20
AE9
A19
R22
VCC[018]
VCC[085]
VSS[006]
VSS[087]
C9
AE10
A23
R25
VCC[019]
VCC[086]
VSS[007]
VSS[088]
C10
AE12
AF2
T1
VCC[020]
VCC[087]
VSS[008]
VSS[089]
C12
AE13
B6
T4
VCC[021]
VCC[088]
VSS[009]
VSS[090]
C13
AE15
B8
T23
VCC[022]
VCC[089]
VSS[010]
VSS[091]
C15
AE17
B11
T26
VCC[023]
VCC[090]
VSS[011]
VSS[092]
C17
AE18
B13
U3
VCC[024]
VCC[091]
VSS[012]
VSS[093]
C18
AE20
B16
U6
VCC[025]
VCC[092]
VSS[013]
VSS[094]
D9
AF9
B19
U21
VCC[026]
VCC[093]
VSS[014]
VSS[095]
D10
AF10
B21
U24
VCC[027]
VCC[094]
VSS[015]
VSS[096]
D12
AF12
B24
V2
VCC[028]
VCC[095]
VSS[016]
VSS[097]
D14
AF14
C5
V5
VCC[029]
VCC[096]
VSS[017]
VSS[098]
D15
AF15
C8
V22
VCC[030]
VCC[097]
VSS[018]
VSS[099]
D17
AF17
C11
V25
VCC[031]
VCC[098]
VSS[019]
VSS[100]
+V1.05S
3,6,9,10,20,21,24,45,48,54,56
D18
AF18
C14
W1
VCC[032]
VCC[099]
VSS[020]
VSS[101]
E7
AF20
C16
W4
VCC[033]
VCC[100]
VSS[021]
VSS[102]
E9
C19
W23
VCC[034]
VSS[022]
VSS[103]
E10
G21
C2
W26
VCC[035]
VCCP[01]
VSS[023]
VSS[104]
E12
V6
C22
Y3
VCC[036]
VCCP[02]
VSS[024]
VSS[105]
Customer
E13
J6
+
+
C382
C382
C542
C542
C25
Y6
VCC[037]
VCCP[03]
VSS[025]
VSS[106]
Recommended
220uF
220uF
270uF
270uF
E15
K6
D1
Y21
C
VCC[038]
VCCP[04]
10%
10%
VSS[026]
VSS[107]
bulk Cap
C
E17
M6
D4
Y24
VCC[039]
VCCP[05]
VSS[027]
VSS[108]
E18
J21
D8
AA2
VCC[040]
VCCP[06]
VSS[028]
VSS[109]
E20
K21
D11
AA5
VCC[041]
VCCP[07]
VSS[029]
VSS[110]
F7
M21
D13
AA8
VCC[042]
VCCP[08]
VSS[030]
VSS[111]
F9
N21
D16
AA11
VCC[043]
VCCP[09]
VSS[031]
VSS[112]
F10
N6
D19
AA14
VCC[044]
VCCP[10]
VSS[032]
VSS[113]
F12
R21
D23
AA16
VCC[045]
VCCP[11]
VSS[033]
VSS[114]
F14
R6
D26
AA19
VCC[046]
VCCP[12]
VSS[034]
VSS[115]
F15
T21
E3
AA22
VCC[047]
VCCP[13]
VSS[035]
VSS[116]
10,18,24
26,48,56
+V1.5S
F17
T6
E6
AA25
VCC[048]
VCCP[14]
VSS[036]
VSS[117]
F18
V21
E8
AB1
VCC[049]
VCCP[15]
VSS[037]
VSS[118]
F20
W21
E11
AB4
VCC[050]
VCCP[16]
VSS[038]
VSS[119]
AA7
E14
AB8
VCC[051]
VSS[039]
VSS[120]
AA9
B26
E16
AB11
VCC[052]
VCCA[01]
VSS[040]
VSS[121]
AA10
C26
E19
AB13
VCC[053]
VCCA[02]
VSS[041]
VSS[122]
53,54,56
+VCC_CORE
C151
C151
AA12
LAYOUT NOTE: PLACE C551
E21
AB16
VCC[054]
VSS[042]
VSS[123]
AA13
AD6
C549
C549
10uF
10uF
NEAR PIN B26
E24
AB19
VCC[055]
VID[0]
H_VID0
52
VSS[043]
VSS[124]
0.01uF
0.01uF
AA15
AF5
F5
AB23
VCC[056]
VID[1]
H_VID1
52
VSS[044]
VSS[125]
AA17
AE5
10%
10%
F8
AB26
VCC[057]
VID[2]
H_VID2
52
VSS[045]
VSS[126]
AA18
AF4
F11
AC3
VCC[058]
VID[3]
H_VID3
52
VSS[046]
VSS[127]
AA20
AE3
F13
AC6
VCC[059]
VID[4]
H_VID4
52
VSS[047]
VSS[128]
AB9
AF3
F16
AC8
VCC[060]
VID[5]
H_VID5
52
VSS[048]
VSS[129]
AC10
AE2
R524
R524
F19
AC11
VCC[061]
VID[6]
H_VID6
52
VSS[049]
VSS[130]
100
100
AB10
F2
AC14
VCC[062]
1%
1%
VSS[050]
VSS[131]
AB12
F22
AC16
VCC[063]
VSS[051]
VSS[132]
Layout Note:
AB14
AF7
F25
AC19
VCC[064]
VCCSENSE
VCCSENSE
52
VSS[052]
VSS[133]
Route VCCSENSE and VSSSENSE traces at
AB15
G4
AC21
VCC[065]
VSS[053]
VSS[134]
27.4 Ohms with 50 mil spacing.
AB17
G1
AC24
VCC[066]
VSS[054]
VSS[135]
Place PU and PD within 1 inch of CPU.
AB18
AE7
G23
AD2
VCC[067]
VSSSENSE
VSSSENSE
52
VSS[055]
VSS[136]
G26
AD5
VSS[056]
VSS[137]
Merom Ball-out Rev 1a_Oakmont
Merom Ball-out Rev 1a_Oakmont
R525
R525
H3
AD8
VSS[057]
VSS[138]
100
100
H6
AD11
1%
1%
VSS[058]
VSS[139]
H21
AD13
VSS[059]
VSS[140]
H24
AD16
VSS[060]
VSS[141]
J2
AD19
B
VSS[061]
VSS[142]
B
J5
AD22
VSS[062]
VSS[143]
J22
AD25
VSS[063]
VSS[144]
J25
AE1
VSS[064]
VSS[145]
K1
AE4
VSS[065]
VSS[146]
K4
AE8
VSS[066]
VSS[147]
K23
AE11
VSS[067]
VSS[148]
K26
AE14
VSS[068]
VSS[149]
L3
AE16
VSS[069]
VSS[150]
L6
AE19
VSS[070]
VSS[151]
L21
AE23
VSS[071]
VSS[152]
L24
AE26
VSS[072]
VSS[153]
M2
A2
VSS[073]
VSS[154]
M5
AF6
VSS[074]
VSS[155]
M22
AF8
VSS[075]
VSS[156]
M25
AF11
VSS[076]
VSS[157]
N1
AF13
VSS[077]
VSS[158]
N4
AF16
VSS[078]
VSS[159]
N23
AF19
VSS[079]
VSS[160]
N26
AF21
VSS[080]
VSS[161]
P3
A25
VSS[081]
VSS[162]
AF25
VSS[163]
Merom Ball-out Rev 1a_Oakmont
Merom Ball-out Rev 1a_Oakmont
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
Title
Title
Title
Merom (2 of 2)
Merom (2 of 2)
Merom (2 of 2)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Date:
Date:
Date:
Sheet
Sheet
Sheet
4
4
4
of
of
of
64
64
64
5
4
3
2
1
12
5 4 3 2 1 7,9,10,16 19,22 26,28,30,32 34,38,40,42,44,45,49,50,52,55 58 +V3.3S 7,9,10,16 19,22 26,28,30,32
5
4
3
2
1
7,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
7,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
CPU Thermal Sensor
Layout Note:
R116
R116
R109
R109
U19: Place at
10K
10K
10K
10K
Route H_THERMDA and
C520
C520
SouthEast corner of
H_THERMDC on same layer
0.1uF
0.1uF
CPU, near
w/ 10 mil trace & 10 mil
R596
R596
H_THERMDA/C pins
10K
10K
spacing. Route away from
noise sources with ground
U29
U29
guard tracks on each side.
1
8
VDD
SCLK
SMB_THRM_CLK
42
Note: No-Stuff R141 for normal operation.
R103
R103
499
499
ADT_THERM_DXP
2
7
3
H_THERMDA
D+
SDATA
SMB_THRM_DATA
42
D
1%
1%
C521
C521
D
1000pF
1000pF
ADT_THERM_DXN
THRM_ALERT#
3
6
R10525
R10525
0
0
D-
ALRT#/THM2#
PM_THRM#
23,42
R122
R122
499
499
5%
5%
NO_STUFF
NO_STUFF
3
H_THERMDC
1%
1%
ADT_THM#
4
5
THM#
GND
ADT7461A-TEMP MON
ADT7461A-TEMP MON
System thermal monitoring
7,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
7,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
C354
C354
PLACE PULLUPS BY DEVICE
R484
R484
0.1uF
0.1uF
Q95: Place below fan
at west edge of board
10K
10K
U5: Place north of
Q1: Place near
IMVP on primary side
RHE at extreme
C
C
North edge of
SMB_THRM_CLK
42
R41
R41
0
0
U7
U7
7481_D1P
board
3
SMB_THRM_DATA
42
1
10
VDD
SCLK
7481_D1P_R
C357
C357
2
9
1
3
D1+
SDATA
7481_D1N_R
7481_THRM2#
1000pF
1000pF
3
8
D1-
ALRT#/THM2#
Q68
Q68
7481_D2P
C48
C48
Q1
Q1
10%
10%
4
7
1
THM#
D2+
2
2N3904
2N3904
R42
R42
0
0
7481_D2N
1000pF
1000pF
2N3904
2N3904
7481_D1N
7481_THRM#
5
6
GND
D2-
10%
10%
2
ADT7481ARMZ-1 TEMP MON
ADT7481ARMZ-1 TEMP MON
7,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
R496
R496
10K
10K
R482
R482
0
0
NO_STUFF
NO_STUFF
R483
R483
0
0
PM_THRM#
23,42
NO_STUFF
NO_STUFF
B
B
CPU Fan Power Control
OPA567_ISIN_R
7,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
16
18,24,26,28,30
32,34,49,50,52,53,56,57
+V5S
OPA567_NEGIN
C136
C136
C131
C131
0.1uF
0.1uF
4.7uF
4.7uF
10%
10%
10%
10%
EU2
EU2
R591
R591
V+
V+
2
1.07k
1.07k
8 TF
TF
EN
EN
VOUT_OPAMP
1%
1%
OPA567
OPA567
OUT
OUT
R593
R593
15K
15K
OPA567_POSIN
IF IF
3
42 CPU_PWM_FAN
9 + +
IS IS
1%
1%
HS
HS
V-
V-
C533
C533
CPU_TACHO_FAN
42
1uF
1uF
10%
10%
3
R603
R603
1.74K
1.74K
Q70
Q70
1%
1%
BAT54
BAT54
1
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
J12
J12
J11
J11
CONN3_HDR
CONN3_HDR
CONN2_HDR
CONN2_HDR
Title
Title
Title
R607
R607
R599
R599
CPU Thermal Sensor & Fan
CPU Thermal Sensor & Fan
CPU Thermal Sensor & Fan
20K
20K
3.32K
3.32K
1%
1%
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
Date:
Date:
Date:
Sheet
Sheet
Sheet
5
5
5
of
of
of
64
64
64
5
4
3
2
1
4
1
5
12
13
6
10
7
11
3
3
2
2
1
1
2 1
2 1
5 4 3 2 1 U17A U17A H_A#[35:3] 3 H_A#3 J13 3 H_D#[63:0] H_A#_3 H_D#0
5
4
3
2
1
U17A
U17A
H_A#[35:3]
3
H_A#3
J13
3
H_D#[63:0]
H_A#_3
H_D#0
H_A#4
E2
B11
H_D#_0
H_A#_4
H_D#1
H_A#5
G2
C11
H_D#_1
H_A#_5
H_D#2
H_A#6
G7
M11
H_D#_2
H_A#_6
D
H_D#3
H_A#7
M6
C15
D
H_D#_3
H_A#_7
H_D#4
H_A#8
H7
F16
H_D#_4
H_A#_8
H_D#5
H_A#9
H3
L13
H_D#_5
H_A#_9
H_D#6
H_A#10
G4
G17
H_D#_6
H_A#_10
H_D#7
H_A#11
F3
C14
H_D#_7
H_A#_11
+V1.05S
3,4,9,10,20,21,24,45,48,54,56
H_D#8
H_A#12
N8
K16
H_D#_8
H_A#_12
H_D#9
H_A#13
H2
B13
H_D#_9
H_A#_13
H_D#10
H_A#14
M10
L16
H_D#_10
H_A#_14
H_D#11
H_A#15
N12
J17
H_D#_11
H_A#_15
R173
R173
H_D#12
H_A#16
N9
B14
H_D#_12
H_A#_16
221
221
H_D#13
H_A#17
H5
K19
1%
1%
H_D#_13
H_A#_17
H_SWING
H_D#14
H_A#18
P13
P15
H_D#_14
H_A#_18
H_D#15
H_A#19
K9
R17
H_D#_15
H_A#_19
H_D#16
H_A#20
M2
B16
H_D#_16
H_A#_20
H_D#17
H_A#21
W10
H20
H_D#_17
H_A#_21
H_D#18
H_A#22
Y8
L19
H_D#_18
H_A#_22
H_D#19
H_A#23
V4
D17
H_D#_19
H_A#_23
R10526
R10526
H_D#20
H_A#24
M3
M17
H_D#_20
H_A#_24
100
100
C167
C167
H_D#21
H_A#25
J1
N16
1%
1%
H_D#_21
H_A#_25
0.1uF
0.1uF
H_D#22
H_A#26
N5
J19
H_D#_22
H_A#_26
H_D#23
H_A#27
N3
B18
H_D#_23
H_A#_27
H_D#24
H_A#28
W6
E19
H_D#_24
H_A#_28
H_D#25
H_A#29
W9
B17
H_D#_25
H_A#_29
H_D#26
H_A#30
N2
B15
H_D#_26
H_A#_30
H_D#27
H_A#31
Y7
E17
H_D#_27
H_A#_31
H_D#28
H_A#32
Y9
C18
H_D#_28
H_A#_32
H_D#29
H_A#33
P4
A19
H_D#_29
H_A#_33
H_RCOMP
H_D#30
H_A#34
W3
B19
H_D#_30
H_A#_34
H_D#31
H_A#35
N1
N19
H_D#_31
H_A#_35
H_D#32
AD12
H_D#_32
R177
R177
H_D#33
AE3
G12
H_D#_33
H_ADS#
H_ADS#
3
24.9
24.9
H_D#34
AD9
H17
1%
1%
H_D#_34
H_ADSTB#_0
H_ADSTB#0
3
C
H_D#35
C
AC9
G20
H_D#_35
H_ADSTB#_1
H_ADSTB#1
3
H_D#36
AC7
C8
H_D#_36
H_BNR#
H_BNR#
3
H_D#37
AC14
E8
H_D#_37
H_BPRI#
H_BPRI#
3
H_D#38
AD11
F12
H_D#_38
H_BREQ#
H_BREQ#
3
H_D#39
AC11
D6
H_D#_39
H_DEFER#
H_DEFER#
3
H_D#40
AB2
C10
H_D#_40
H_DBSY#
H_DBSY#
3
H_D#41
AD7
AM5
H_D#_41
HPLL_CLK
CLK_MCH_BCLK
37
H_D#42
AB1
AM7
H_D#_42
HPLL_CLK#
CLK_MCH_BCLK#
37
H_D#43
Y3
H8
H_D#_43
H_DPWR#
H_DPWR#
3
H_D#44
AC6
K7
H_D#_44
H_DRDY#
H_DRDY#
3
+V1.05S
3,4,9,10,20,21,24,45,48,54,56
H_D#45
AE2
E4
H_D#_45
H_HIT#
H_HIT#
3
H_D#46
AC5
C6
H_D#_46
H_HITM#
H_HITM#
3
R175
R175
54.9
54.9
H_SCOMP
H_D#47
AG3
G10
H_D#_47
H_LOCK#
H_LOCK#
3
1%
1%
H_D#48
AJ9
B7
H_D#_48
H_TRDY#
H_TRDY#
3
H_D#49
AH8
H_D#_49
H_D#50
AJ14
H_D#_50
R176
R176
54.9
54.9
H_SCOMP#
H_D#51
AE9
H_D#_51
1%
1%
H_D#52
AE11
H_D#_52
H_D#53
AH12
K5
H_D#_53
H_DINV#_0
H_DINV#0
3
H_D#54
AJ5
L2
H_D#_54
H_DINV#_1
H_DINV#1
3
H_D#55
AH5
AD13
H_D#_55
H_DINV#_2
H_DINV#2
3
H_D#56
AJ6
AE13
H_D#_56
H_DINV#_3
H_DINV#3
3
H_D#57
AE7
H_D#_57
H_D#58
AJ7
M7
H_D#_58
H_DSTBN#_0
H_DSTBN#0
3
H_D#59
AJ2
K3
H_D#_59
H_DSTBN#_1
H_DSTBN#1
3
H_D#60
AE5
AD2
H_D#_60
H_DSTBN#_2
H_DSTBN#2
3
H_D#61
AJ3
AH11
H_D#_61
H_DSTBN#_3
H_DSTBN#3
3
H_D#62
AH2
H_D#_62
H_D#63
AH13
L7
H_D#_63
H_DSTBP#_0
H_DSTBP#0
3
K2
H_DSTBP#_1
H_DSTBP#1
3
AC2
H_DSTBP#_2
H_DSTBP#2
3
H_SWING
B3
AJ10
B
H_SWING
H_DSTBP#_3
H_DSTBP#3
3
B
Note: H_CPURST#
H_RCOMP
C2
H_RCOMP
H_REQ#[4:0]
3
H_REQ#0
M14
has T topology
H_REQ#_0
H_SCOMP
H_REQ#1
W1
E13
H_SCOMP
H_REQ#_1
H_SCOMP#
H_REQ#2
W2
A11
H_SCOMP#
H_REQ#_2
H_REQ#3
H13
H_REQ#_3
H_REQ#4
B6
B12
3,20
H_CPURST#
H_CPURST#
H_REQ#_4
E5
3
H_CPUSLP#
H_CPUSLP#
H_RS#[2:0]
3
H_RS#0
E12
H_RS#_0
H_RS#1
D7
H_RS#_1
3,4,9,10,20,21,24,45,48,54,56
+V1.05S
H_RS#2
D8
H_RS#_2
B9
H_AVREF
A9
H_DVREF
R154
R154
1K
1K
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
1%
1%
H_VREF
R146
R146
C149
C149
2K
2K
0.1uF
0.1uF
1%
1%
10%
10%
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
Title
Title
Title
CRESTLINE (1 OF 6)
CRESTLINE (1 OF 6)
CRESTLINE (1 OF 6)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
Date:
Date:
Date:
Sheet
Sheet
Sheet
6
6
6
of
of
of
64
64
64
5
4
3
2
1
HOST
HOST
LVDS LVDS TV TV VGA VGA 5 4 3 2 1 U17B U17B 5,9,10,16 19,22
LVDS
LVDS
TV
TV
VGA
VGA
5
4
3
2
1
U17B
U17B
5,9,10,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
R84
R84
10K
10K
CLK_MCH_OE#
1%
1%
TP_MCH_RSVD1
R71
R71
10K
10K
PM_EXTTS#0
P36
RSVD1
TP_MCH_RSVD2
1%
1%
P37
AV29
RSVD2
SM_CK_0
13
TP_MCH_RSVD3
R83
10K
10K
PM_EXTTS#1
R35
BB23
RSVD3
SM_CK_1
M_CLK_DDR0
13
R83
TP_MCH_RSVD4
1%
1%
N35
BA25
RSVD4
SM_CK_3
14
10
+VCC_PEG
TP_MCH_RSVD5
AV23
M_CLK_DDR3
M_CLK_DDR1
AR12
U17C
U17C
RSVD5
SM_CK_4
M_CLK_DDR4
14
TP_MCH_RSVD6
AR13
RSVD6
TP_MCH_RSVD7
AM12
AW30
J40
RSVD7
SM_CK#_0
M_CLK_DDR#0
13
17
L_BKLT_CTRL
L_BKLT_CTRL
TP_MCH_RSVD8
PEG_COMP
R70
R70
24.9
24.9
AN13
BA23
H39
N43
RSVD8
SM_CK#_1
M_CLK_DDR#1
13
17
L_BKLT_EN
L_BKLT_EN
PEG_COMPI
TP_MCH_RSVD9
1%
1%
J12
AW25
E39
M43
RSVD9
SM_CK#_3
M_CLK_DDR#3
14
17
L_CTRL_CLK
L_CTRL_CLK
PEG_COMPO
TP_MCH_RSVD10
AR37
AW23
E40
RSVD10
SM_CK#_4
M_CLK_DDR#4
14
17
L_CTRL_DATA
L_CTRL_DATA
TP_MCH_RSVD11
AM36
C37
RSVD11
17
LVDS_DDC_CLK
L_DDC_CLK
TP_MCH_RSVD12
TP_PEG_RX#0
AL36
BE29
D35
J51
RSVD12
SM_CKE_0
M_CKE0
13,15
17
LVDS_DDC_DATA
L_DDC_DATA
PEG_RX#_0
TP_MCH_RSVD13
AM37
AY32
K40
L51
RSVD13
SM_CKE_1
M_CKE1
13,15
L_VDD_EN
PEG_RX#_1
SDVOB_INTN
18
17
LVDS_VDD_EN
D
TP_MCH_RSVD14
TP_PEG_RX#2
D20
BD39
N47
D
RSVD14
SM_CKE_3
M_CKE3
14,15
PEG_RX#_2
LVDS_IBG
TP_PEG_RX#3
BG37
L41
T45
SM_CKE_4
M_CKE4
14,15
LVDS_IBG
PEG_RX#_3
TP_LVDS_VBG
TP_PEG_RX#4
L43
T50
LVDS_VBG
PEG_RX#_4
TP_PEG_RX#5
BG20
N41
U40
SM_CS#_0
M_CS#0
13,15
LVDS_VREFH
PEG_RX#_5
TP_PEG_RX#6
BK16
N40
Y44
SM_CS#_1
M_CS#1
13,15
LVDS_VREFL
PEG_RX#_6
TP_PEG_RX#7
BG16
D46
Y40
SM_CS#_2
M_CS#2
14,15
17
LVDSA_CLK#
LVDSA_CLK#
PEG_RX#_7
TP_MCH_RSVD20
TP_PEG_RX#8
H10
BE13
C45
AB51
RSVD20
SM_CS#_3
M_CS#3
14,15
17
LVDSA_CLK
LVDSA_CLK
PEG_RX#_8
TP_MCH_RSVD21
TP_PEG_RX#9
B51
D44
W49
RSVD21
17
LVDSB_CLK#
LVDSB_CLK#
PEG_RX#_9
TP_MCH_RSVD22
TP_PEG_RX#10
BJ20
BH18
E42
AD44
RSVD22
SM_ODT_0
M_ODT0
13,15
17
LVDSB_CLK
LVDSB_CLK
PEG_RX#_10
TP_MCH_RSVD23
TP_PEG_RX#11
BK22
BJ15
AD40
RSVD23
SM_ODT_1
M_ODT1
13,15
PEG_RX#_11
TP_MCH_RSVD24
TP_PEG_RX#12
BF19
BJ14
G51
AG46
RSVD24
SM_ODT_2
M_ODT2
14,15
17
LVDSA_DATA#0
LVDSA_DATA#_0
PEG_RX#_12
TP_MCH_RSVD25
TP_PEG_RX#13
BH20
BE16
E51
AH49
RSVD25
SM_ODT_3
M_ODT3
14,15
17
LVDSA_DATA#1
LVDSA_DATA#_1
PEG_RX#_13
TP_MCH_RSVD26
TP_PEG_RX#14
BK18
F49
AG45
RSVD26
17
LVDSA_DATA#2
LVDSA_DATA#_2
PEG_RX#_14
TP_MCH_RSVD27
SM_RCOMP
TP_PEG_RX#15
BJ18
BL15
C48
AG41
RSVD27
SM_RCOMP
17
LVDSA_DATA#3
LVDSA_DATA#_3
PEG_RX#_15
TP_MCH_RSVD28
SM_RCOMP#
BF23
BK14
RSVD28
SM_RCOMP#
TP_MCH_RSVD29
TP_PEG_RX0
BG23
G50
J50
RSVD29
17
LVDSA_DATA0
LVDSA_DATA_0
PEG_RX_0
TP_MCH_RSVD30
SM_RCOMP_VOH
BC23
BK31
E50
L50
RSVD30
SM_RCOMP_VOH
17
LVDSA_DATA1
LVDSA_DATA_1
PEG_RX_1
SDVOB_INTP
18
TP_MCH_RSVD31
SM_RCOMP_VOL
TP_PEG_RX2
BD24
BL31
F48
M47
RSVD31
SM_RCOMP_VOL
17
LVDSA_DATA2
LVDSA_DATA_2
PEG_RX_2
TP_PEG_RX3
D47
U44
17
LVDSA_DATA3
LVDSA_DATA_3
PEG_RX_3
TP_PEG_RX4
AR49
T49
SM_VREF_0
M_VREF_MCH
13,14,47
PEG_RX_4
TP_MCH_RSVD34
TP_PEG_RX5
BH39
AW4
G44
T41
RSVD34
SM_VREF_1
17
LVDSB_DATA#0
LVDSB_DATA#_0
PEG_RX_5
TP_MCH_RSVD35
TP_PEG_RX6
AW20
B47
W45
RSVD35
17
LVDSB_DATA#1
LVDSB_DATA#_1
PEG_RX_6
TP_MCH_RSVD36
TP_PEG_RX7
BK20
B45
W41
RSVD36
17
LVDSB_DATA#2
LVDSB_DATA#_2
PEG_RX_7
TP_PEG_RX8
AB50
PEG_RX_8
TP_PEG_RX9
B42
Y48
DPLL_REF_CLK
DREFCLK
37
PEG_RX_9
TP_MCH_RSVD39
TP_PEG_RX10
B44
C42
E44
AC45
RSVD39
DPLL_REF_CLK#
DREFCLK#
37
17
LVDSB_DATA0
LVDSB_DATA_0
PEG_RX_10
TP_MCH_RSVD40
TP_PEG_RX11
C44
H48
A47
AC41
RSVD40
DPLL_REF_SSCLK
DREFSSCLK
37
17
LVDSB_DATA1
LVDSB_DATA_1
PEG_RX_11
TP_MCH_RSVD41
TP_PEG_RX12
A35
H47
A45
AH47
RSVD41
DPLL_REF_SSCLK#
DREFSSCLK#
37
17
LVDSB_DATA2
LVDSB_DATA_2
PEG_RX_12
TP_MCH_RSVD42
TP_PEG_RX13
B37
AG49
RSVD42
PEG_RX_13
TP_MCH_RSVD43
TP_PEG_RX14
B36
K44
AH45
RSVD43
PEG_CLK
CLK_PCIE_3GPLL
37
PEG_RX_14
TP_MCH_RSVD44
TP_PEG_RX15
B34
K45
AG42
RSVD44
PEG_CLK#
CLK_PCIE_3GPLL#
37
PEG_RX_15
TP_MCH_RSVD45
C34
RSVD45
C
+V3.3S 5,9,10,16 19,22 26,28,30,32 34,38,40,42,44,45,49,50,52,55 58
R124
R124
150
150
1%
1%
TVA_DAC
C
E27
N45
TVA_DAC
PEG_TX#_0
SDVOB_RN
18
R119
R119
150
150
1%
1%
TVB_DAC
G27
U39
DMI_TXN[3:0]
22
TVB_DAC
PEG_TX#_1
18
DMI_TXN0
R111
R111
150
150
1%
1%
TVC_DAC
Don’t need to strap CFG[4:3].
AN47
K27
U47
DMI_RXN_0
TVC_DAC
PEG_TX#_2
SDVOB_GN
SDVOB_BN
18
DMI_TXN1
AJ38
N51
BIOS will read SPD and
DMI_RXN_1
PEG_TX#_3
SDVOB_CLKN
18
DMI_TXN2
TP_PEG_TX#4
AN42
F27
R50
determine DDR frequency.
DMI_RXN_2
TVA_RTN
PEG_TX#_4
DMI_TXN3
TP_PEG_TX#5
AN46
J27
T42
DMI_RXN_3
TVB_RTN
PEG_TX#_5
TP_PEG_TX#6
L27
Y43
DMI_TXP[3:0]
22
TVC_RTN
PEG_TX#_6
DMI_TXP0
TP_PEG_TX#7
AM47
W46
3,37
MCH_BSEL0
DMI_RXP_0
PEG_TX#_7
DMI_TXP1
TP_TV_DCONSEL_0
TP_PEG_TX#8
P27
AJ39
M35
W38
3,37
MCH_BSEL1
CFG_0
DMI_RXP_1
TV_DCONSEL_0
PEG_TX#_8
DMI_TXP2
TP_TV_DCONSEL_1
TP_PEG_TX#9
N27
AN41
P33
AD39
3,37
MCH_BSEL2
CFG_1
DMI_RXP_2
TV_DCONSEL_1
PEG_TX#_9
DMI_TXP3
TP_PEG_TX#10
N24
AN45
AC46
CFG_2
DMI_RXP_3
PEG_TX#_10
TP_MCH_CFG_3
TP_PEG_TX#11
C21
AC49
CFG_3
DMI_RXN[3:0]
22
PEG_TX#_11
TP_MCH_CFG_4
DMI_RXN0
TP_PEG_TX#12
C23
AJ46
AC42
CFG_4
DMI_TXN_0
PEG_TX#_12
R129
R129
4.02K
4.02K
TP_MCH_CFG_5
DMI_RXN1
TP_PEG_TX#13
F23
AJ41
AH39
CFG_5
DMI_TXN_1
PEG_TX#_13
NO STUFF 1%
NO STUFF 1%
TP_MCH_CFG_6
DMI_RXN2
TP_PEG_TX#14
N23
AM40
AE49
CFG_6
DMI_TXN_2
PEG_TX#_14
TP_MCH_CFG_7
DMI_RXN3
TP_PEG_TX#15
G23
AM44
AH44
CFG_7
DMI_TXN_3
PEG_TX#_15
TP_MCH_CFG_8
J20
CFG_8
DMI_RXP[3:0]
22
MCH_CFG_9
DMI_RXP0
C20
AJ47
H32
M45
CFG_9
DMI_TXP_0
16
CRT_BLUE
CRT_BLUE
PEG_TX_0
18
TP_MCH_CFG_10
DMI_RXP1
R24
AJ42
G32
T38
CFG_10
DMI_TXP_1
CRT_BLUE#
PEG_TX_1
18
TP_MCH_CFG_11
DMI_RXP2
SDVOB_RP
L23
AM39
K29
T46
CFG_11
DMI_TXP_2
16
CRT_GREEN
CRT_GREEN
PEG_TX_2
SDVOB_GP
SDVOB_BP
18
MCH_CFG_12
DMI_RXP3
J23
AM43
J29
N50
CFG_12
DMI_TXP_3
CRT_GREEN#
PEG_TX_3
SDVOB_CLKP
18
MCH_CFG_13
TP_PEG_TX4
E23
F29
R51
CFG_13
16
CRT_RED
CRT_RED
PEG_TX_4
TP_MCH_CFG_14
R89
R89
150
150
1%
1%
TP_PEG_TX5
E20
E29
U43
CFG_14
CRT_RED#
PEG_TX_5
TP_MCH_CFG_15
R94
R94
150
150
1%
1%
TP_PEG_TX6
K23
W42
CFG_15
PEG_TX_6
R95
R95
TP_MCH_CFG_16
TP_PEG_TX7
M20
R91
R91
150
150
1%
1%
Y47
4.02K
4.02K
CFG_16
PEG_TX_7
TP_MCH_CFG_17
TP_PEG_TX8
M24
K33
Y39
1%
1%
CFG_17
16
CRT_DDC_CLK
CRT_DDC_CLK
PEG_TX_8
TP_MCH_CFG_18
TP_PEG_TX9
NO_STUFF
NO_STUFF
L32
G35
AC38
CFG_18
16
CRT_DDC_DATA
CRT_DDC_DATA
PEG_TX_9
MCH_CFG_19
HSYNC
TP_PEG_TX10
N33
F33
AD47
CFG_19
CRT_HSYNC
PEG_TX_10
TP_MCH_CFG_20
R88
R88
30.1
30.1
1%
1%
CRTIREF
TP_PEG_TX11
L35
C32
AC50
CFG_20
16
CRT_HSYNC
CRT_TVO_IREF
PEG_TX_11
R87
R87
30.1
30.1
1%
1%
VSYNC
TP_PEG_TX12
E33
AD43
16
CRT_VSYNC
CRT_VSYNC
PEG_TX_12
TP_PEG_TX13
AG39
PEG_TX_13
TP_PEG_TX14
E35
AE50
B
GFX_VID_0
DFGT_VID_0
49
PEG_TX_14
B
TP_PEG_TX15
G41
A39
AH43
DFGT_VID_1
49
23 PM_BMBUSY#
PM_BM_BUSY#
GFX_VID_1
PEG_TX_15
+V1.8_GMCH
9,10,45
R588
R588
L39
C38
3,21,52
H_DPRSTP#
PM_DPRSTP#
GFX_VID_2
DFGT_VID_2
49
L36
B39
1.30K
1.30K
13,15
PM_EXTTS#0
PM_EXT_TS#_0
GFX_VID_3
DFGT_VID_3
49
0.5%
0.5%
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
J36
E36
14,15
PM_EXTTS#1
PM_EXT_TS#_1
GFX_VR_EN
DFGT_VR_EN
49
10,37,48,56,57
+V1.25M
R99
R99
AW49
23,52
DELAY_VR_PWRGOOD
PWROK
1K
1K
R10527R10527
100100
RST_IN#_MCH
AV20
19,22,25,26,40,58
PLT_RST#
RSTIN#
0.10%
0.10%
N20
3,21
PM_THRMTRIP#
THERMTRIP#
G36
23,52
PM_DPRSLPVR
DPRSLPVR
R72
R72
SM_RCOMP_VOH
1K
1K
AM49
CFGRSVD
CFGRSVD
PM
PM
NC
NC
CL_CLK
CL_CLK0
23
1%
1%
C128
C128
C514
C514
AK50
CL_DATA
CL_DATA0
23
TP_MCH_NC1
R93
R93
0.01uF
0.01uF
2.2uF
2.2uF
BJ51
AT43
NC_1
CL_PWROK
MPWROK
23,47
TP_MCH_NC2
BK51
AN49
3.01k
3.01k
10%
10%
10%
10%
NC_2
CL_RST#
CL_RST#0
23
TP_MCH_NC3
MCH_CLVREF
402
402
BK50
AM50
NC_3
CL_VREF
TP_MCH_NC4
BL50
NC_4
TP_MCH_NC5
C71
C71
LVDS_IBG
BL49
NC_5
TP_MCH_NC6
0.1uF
0.1uF
R66
R66
BL3
NC_6
TP_MCH_NC7
BL2
10%
10%
392
392
SM_RCOMP_VOL
NC_7
TP_MCH_NC8
1%
1%
R77
R77
BK1
NC_8
2.37K
2.37K
TP_MCH_NC9
BJ1
H35
NC_9
SDVO_CTRL_CLK
SDVO_CTRLCLK
18
1%
1%
TP_MCH_NC10
R90
R90
C117
C117
C499
C499
E1
K36
NC_10
SDVO_CTRL_DATA
SDVO_CTRLDATA
18
1K
1K
TP_MCH_NC11
0.01uF
0.01uF
2.2uF
2.2uF
A5
G39
NC_11
CLK_REQ#
CLK_MCH_OE#
37
0.10%
0.10%
TP_MCH_NC12
C51
G40
10%
10%
10%
10%
MCH_ICH_SYNC#
23
NC_12
ICH_SYNC#
TP_MCH_NC13
402
402
B50
NC_13
TP_MCH_NC14
A50
NC_14
TP_MCH_NC15
MCH_TEST_R
A49
A37
NC_15
TEST_1
TP_MCH_NC16
BK2
R32
NC_16
TEST_2
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
R81
R81
10K
10K
+V1.8_GMCH
9,10,45
MCH CONFIG
A
A
MCH_CFG_12
STRAPS
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
MCH_CFG_13
R152
R152
PCI Express Graphics Lane
20
20
Title
Title
Title
1%
1%
Low = Reverse Lane
MCH_CFG_9
High = Normal operation (default)
XOR / ALLZ / Clock Un-gating
CRESTLINE (2 OF 6)
CRESTLINE (2 OF 6)
CRESTLINE (2 OF 6)
MCH_CFG_12
MCH_CFG_13
Configuration
SM_RCOMP
DMI Lane Reversal
0
0
Reserved
R121
R121
R113
R113
SM_RCOMP#
4.02K
4.02K
4.02K
4.02K
Low = Normal (default)
0
1
XOR Mode Enabled
1%
1%
1%
1%
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
MCH_CFG_19
High = Lanes Reversed
1
0
All-Z Mode Enabled
NO_STUFF
NO_STUFF
NO_STUFF
NO_STUFF
1
1
Clock Gating Enabled (default)
R153
R153
A
A
A
20
20
1%
1%
Date:
Date:
Date:
Sheet
Sheet
Sheet
7
7
7
of
of
of
64
64
64
5
4
3
2
1
MISC
MISC
GRAPHICS VIDME
GRAPHICS VIDME
DDR MUXINGCLKDMI
DDR MUXINGCLKDMI
1
2
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
5 4 3 2 1 13 M_A_DQ[63:0] 14 M_B_DQ[63:0] U17D U17D U17E U17E D M_A_DQ0
5
4
3
2
1
13 M_A_DQ[63:0]
14 M_B_DQ[63:0]
U17D
U17D
U17E
U17E
D
M_A_DQ0
M_B_DQ0
AR43
BB19
AP49
AY17
D
SA_DQ_0
SA_BS_0
M_A_BS0
13,15
SB_DQ_0
SB_BS_0
M_B_BS0
14,15
M_A_DQ1
M_B_DQ1
AW44
BK19
AR51
BG18
SA_DQ_1
SA_BS_1
M_A_BS1
13,15
SB_DQ_1
SB_BS_1
M_B_BS1
14,15
M_A_DQ2
M_B_DQ2
BA45
BF29
AW50
BG36
SA_DQ_2
SA_BS_2
M_A_BS2
13,15
SB_DQ_2
SB_BS_2
M_B_BS2
14,15
M_A_DQ3
M_B_DQ3
AY46
AW51
SA_DQ_3
M_A_CAS#
13,15
SB_DQ_3
M_B_CAS#
14,15
M_A_DQ4
M_B_DQ4
AR41
BL17
AN51
BE17
SA_DQ_4
SA_CAS#
SB_DQ_4
SB_CAS#
M_A_DQ5
M_B_DQ5
AR45
AN50
SA_DQ_5
M_A_DM[7:0]
13
SB_DQ_5
M_B_DM[7:0]
14
M_A_DQ6
M_A_DM0
M_B_DQ6
M_B_DM0
AT42
AT45
AV50
AR50
SA_DQ_6
SA_DM_0
SB_DQ_6
SB_DM_0
M_A_DQ7
M_A_DM1
M_B_DQ7
M_B_DM1
AW47
BD44
AV49
BD49
SA_DQ_7
SA_DM_1
SB_DQ_7
SB_DM_1
M_A_DQ8
M_A_DM2
M_B_DQ8
M_B_DM2
BB45
BD42
BA50
BK45
SA_DQ_8
SA_DM_2
SB_DQ_8
SB_DM_2
M_A_DQ9
M_A_DM3
M_B_DQ9
M_B_DM3
BF48
AW38
BB50
BL39
SA_DQ_9
SA_DM_3
SB_DQ_9
SB_DM_3
M_A_DQ10
M_A_DM4
M_B_DQ10
M_B_DM4
BG47
AW13
BA49
BH12
SA_DQ_10
SA_DM_4
SB_DQ_10
SB_DM_4
M_A_DQ11
M_A_DM5
M_B_DQ11
M_B_DM5
BJ45
BG8
BE50
BJ7
SA_DQ_11
SA_DM_5
SB_DQ_11
SB_DM_5
M_A_DQ12
M_A_DM6
M_B_DQ12
M_B_DM6
BB47
AY5
BA51
BF3
SA_DQ_12
SA_DM_6
SB_DQ_12
SB_DM_6
M_A_DQ13
M_A_DM7
M_B_DQ13
M_B_DM7
BG50
AN6
AY49
AW2
SA_DQ_13
SA_DM_7
SB_DQ_13
SB_DM_7
M_A_DQ14
M_B_DQ14
BH49
BF50
SA_DQ_14
M_A_DQS[7:0]
13
SB_DQ_14
M_B_DQS[7:0]
14
M_A_DQ15
M_A_DQS0
M_B_DQ15
M_B_DQS0
BE45
AT46
BF49
AT50
SA_DQ_15
SA_DQS_0
SB_DQ_15
SB_DQS_0
M_A_DQ16
M_A_DQS1
M_B_DQ16
M_B_DQS1
AW43
BE48
BJ50
BD50
SA_DQ_16
SA_DQS_1
SB_DQ_16
SB_DQS_1
M_A_DQ17
M_A_DQS2
M_B_DQ17
M_B_DQS2
BE44
BB43
BJ44
BK46
SA_DQ_17
SA_DQS_2
SB_DQ_17
SB_DQS_2
M_A_DQ18
M_A_DQS3
M_B_DQ18
M_B_DQS3
BG42
BC37
BJ43
BK39
SA_DQ_18
SA_DQS_3
SB_DQ_18
SB_DQS_3
M_A_DQ19
M_A_DQS4
M_B_DQ19
M_B_DQS4
BE40
BB16
BL43
BJ12
SA_DQ_19
SA_DQS_4
SB_DQ_19
SB_DQS_4
M_A_DQ20
M_A_DQS5
M_B_DQ20
M_B_DQS5
BF44
BH6
BK47
BL7
SA_DQ_20
SA_DQS_5
SB_DQ_20
SB_DQS_5
M_A_DQ21
M_A_DQS6
M_B_DQ21
M_B_DQS6
BH45
BB2
BK49
BE2
SA_DQ_21
SA_DQS_6
SB_DQ_21
SB_DQS_6
M_A_DQ22
M_A_DQS7
M_B_DQ22
M_B_DQS7
BG40
AP3
BK43
AV2
SA_DQ_22
SA_DQS_7
M_A_DQS#[7:0]
13
SB_DQ_22
SB_DQS_7
M_B_DQS#[7:0]
14
M_A_DQ23
M_A_DQS#0
M_B_DQ23
M_B_DQS#0
BF40
AT47
BK42
AU50
SA_DQ_23
SA_DQS#_0
SB_DQ_23
SB_DQS#_0
M_A_DQ24
M_A_DQS#1
M_B_DQ24
M_B_DQS#1
AR40
BD47
BJ41
BC50
SA_DQ_24
SA_DQS#_1
SB_DQ_24
SB_DQS#_1
M_A_DQ25
M_A_DQS#2
M_B_DQ25
M_B_DQS#2
AW40
BC41
BL41
BL45
SA_DQ_25
SA_DQS#_2
SB_DQ_25
SB_DQS#_2
M_A_DQ26
M_A_DQS#3
M_B_DQ26
M_B_DQS#3
AT39
BA37
BJ37
BK38
SA_DQ_26
SA_DQS#_3
SB_DQ_26
SB_DQS#_3
M_A_DQ27
M_A_DQS#4
M_B_DQ27
M_B_DQS#4
AW36
BA16
BJ36
BK12
SA_DQ_27
SA_DQS#_4
SB_DQ_27
SB_DQS#_4
M_A_DQ28
M_A_DQS#5
M_B_DQ28
M_B_DQS#5
AW41
BH7
BK41
BK7
SA_DQ_28
SA_DQS#_5
SB_DQ_28
SB_DQS#_5
M_A_DQ29
M_A_DQS#6
M_B_DQ29
M_B_DQS#6
AY41
BC1
BJ40
BF2
SA_DQ_29
SA_DQS#_6
SB_DQ_29
SB_DQS#_6
M_A_DQ30
M_A_DQS#7
M_B_DQ30
M_B_DQS#7
AV38
AP2
BL35
AV3
SA_DQ_30
SA_DQS#_7
SB_DQ_30
SB_DQS#_7
M_A_DQ31
M_B_DQ31
AT38
BK37
SA_DQ_31
M_A_A[14:0]
13,15
SB_DQ_31
M_B_A[14:0]
14,15
C
M_A_DQ32
M_A_A0
M_B_DQ32
M_B_A0
C
AV13
BJ19
BK13
BC18
SA_DQ_32
SA_MA_0
SB_DQ_32
SB_MA_0
M_A_DQ33
M_A_A1
M_B_DQ33
M_B_A1
AT13
BD20
BE11
BG28
SA_DQ_33
SA_MA_1
SB_DQ_33
SB_MA_1
M_A_DQ34
M_A_A2
M_B_DQ34
M_B_A2
AW11
BK27
BK11
BG25
SA_DQ_34
SA_MA_2
SB_DQ_34
SB_MA_2
M_A_DQ35
M_A_A3
M_B_DQ35
M_B_A3
AV11
BH28
BC11
AW17
SA_DQ_35
SA_MA_3
SB_DQ_35
SB_MA_3
M_A_DQ36
M_A_A4
M_B_DQ36
M_B_A4
AU15
BL24
BC13
BF25
SA_DQ_36
SA_MA_4
SB_DQ_36
SB_MA_4
M_A_DQ37
M_A_A5
M_B_DQ37
M_B_A5
AT11
BK28
BE12
BE25
SA_DQ_37
SA_MA_5
SB_DQ_37
SB_MA_5
M_A_DQ38
M_A_A6
M_B_DQ38
M_B_A6
BA13
BJ27
BC12
BA29
SA_DQ_38
SA_MA_6
SB_DQ_38
SB_MA_6
M_A_DQ39
M_A_A7
M_B_DQ39
M_B_A7
BA11
BJ25
BG12
BC28
SA_DQ_39
SA_MA_7
SB_DQ_39
SB_MA_7
M_A_DQ40
M_A_A8
M_B_DQ40
M_B_A8
BE10
BL28
BJ10
AY28
SA_DQ_40
SA_MA_8
SB_DQ_40
SB_MA_8
M_A_DQ41
M_A_A9
M_B_DQ41
M_B_A9
BD10
BA28
BL9
BD37
SA_DQ_41
SA_MA_9
SB_DQ_41
SB_MA_9
M_A_DQ42
M_A_A10
M_B_DQ42
M_B_A10
BD8
BC19
BK5
BG17
SA_DQ_42
SA_MA_10
SB_DQ_42
SB_MA_10
M_A_DQ43
M_A_A11
M_B_DQ43
M_B_A11
AY9
BE28
BL5
BE37
SA_DQ_43
SA_MA_11
SB_DQ_43
SB_MA_11
M_A_DQ44
M_A_A12
M_B_DQ44
M_B_A12
BG10
BG30
BK9
BA39
SA_DQ_44
SA_MA_12
SB_DQ_44
SB_MA_12
M_A_DQ45
M_A_A13
M_B_DQ45
M_B_A13
AW9
BJ16
BK10
BG13
SA_DQ_45
SA_MA_13
SB_DQ_45
SB_MA_13
M_A_DQ46
M_A_A14
M_B_DQ46
M_B_A14
BD7
BJ29
BJ8
BE24
SA_DQ_46
SA_MA_14
SB_DQ_46
SB_MA_14
M_A_DQ47
M_B_DQ47
BB9
BJ6
SA_DQ_47
SB_DQ_47
M_A_DQ48
M_B_DQ48
BB5
BE18
BF4
AV16
SA_DQ_48
SA_RAS#
M_A_RAS#
13,15
SB_DQ_48
SB_RAS#
M_B_RAS#
14,15
M_A_DQ49
TP_SA_RCVEN#
M_B_DQ49
TP_SB_RCVEN#
AY7
AY20
BH5
AY18
SA_DQ_49
SA_RCVEN#
SB_DQ_49
SB_RCVEN#
M_A_DQ50
M_B_DQ50
AT5
BG1
SA_DQ_50
SB_DQ_50
M_A_DQ51
M_B_DQ51
AT7
BA19
BC2
BC17
SA_DQ_51
SA_WE#
M_A_WE#
13,15
SB_DQ_51
SB_WE#
M_B_WE#
14,15
M_A_DQ52
M_B_DQ52
AY6
BK3
SA_DQ_52
SB_DQ_52
M_A_DQ53
M_B_DQ53
BB7
BE4
SA_DQ_53
SB_DQ_53
M_A_DQ54
M_B_DQ54
AR5
BD3
SA_DQ_54
SB_DQ_54
M_A_DQ55
M_B_DQ55
AR8
BJ2
SA_DQ_55
SB_DQ_55
M_A_DQ56
M_B_DQ56
AR9
BA3
SA_DQ_56
SB_DQ_56
M_A_DQ57
M_B_DQ57
AN3
BB3
SA_DQ_57
SB_DQ_57
M_A_DQ58
M_B_DQ58
AM8
AR1
SA_DQ_58
SB_DQ_58
M_A_DQ59
M_B_DQ59
AN10
AT3
SA_DQ_59
SB_DQ_59
M_A_DQ60
M_B_DQ60
AT9
AY2
SA_DQ_60
SB_DQ_60
M_A_DQ61
M_B_DQ61
AN9
AY3
SA_DQ_61
SB_DQ_61
M_A_DQ62
M_B_DQ62
AM9
AU2
SA_DQ_62
SB_DQ_62
M_A_DQ63
M_B_DQ63
AN11
AT2
B
SA_DQ_63
SB_DQ_63
B
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
Title
Title
Title
CRESTLINE (3 OF 6)
CRESTLINE (3 OF 6)
CRESTLINE (3 OF 6)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
Date:
Date:
Date:
Sheet
Sheet
Sheet
8
8
8
of
of
of
64
64
64
5
4
3
2
1
DDR
DDR
SYSTEM MEMORY A
SYSTEM MEMORY A
DDR SYSTEM MEMORY
DDR SYSTEM MEMORY
B
B
5 4 3 2 1 +V1.05S 3,4,6,10,20,21,24,45,48,54,56 +V3.3S 5,7,10,16 19,22 26,28,30,32 34,38,40,42,44,45,49,50,52,55
5
4
3
2
1
+V1.05S
3,4,6,10,20,21,24,45,48,54,56
+V3.3S
5,7,10,16 19,22 26,28,30,32 34,38,40,42,44,45,49,50,52,55 58
3,4,6,10,20,21,24,45,48,54,56
+V1.05S
3,4,6,10,20,21,24,45,48,54,56
+V1.05S
Q16
Q16
Customer
U17G
U17G
49,56 +VCC_GFXCORE
R64
R64
10
10
VCCGFOLLOW2
1
2
3
1
Recommended bulk
Cap
+
+
C60
C60
BAT54
BAT54
AT35
VCC_1
220uF
220uF
AT34
T17
10%
10%
VCC_2
VCC_AXG_NCTF_1
AH28
T18
VCC_3
VCC_AXG_NCTF_2
AC32
T19
VCC_5
VCC_AXG_NCTF_3
U17F
U17F
AC31
T21
VCC_4
VCC_AXG_NCTF_4
D
AK32
T22
D
VCC_6
VCC_AXG_NCTF_5
AJ31
T23
AB33
VCC_7
VCC_AXG_NCTF_6
VCC_NCTF_1
C402
C402
C482
C482
C2030
C2030
C2031
C2031
C474
C474
AJ28
T25
AB36
VCC_8
VCC_AXG_NCTF_7
VCC_NCTF_2
270uF
270uF
0.1uF
0.1uF
22uF
22uF
0.22uF
0.22uF
0.22uF
0.22uF
AH32
U15
AB37
VCC_9
VCC_AXG_NCTF_8
VCC_NCTF_3
10%
10%
AH31
U16
AC33
T27
VCC_10
VCC_AXG_NCTF_9
VCC_NCTF_4
VSS_NCTF_1
AH29
U17
AC35
T37
VCC_11
VCC_AXG_NCTF_10
VCC_NCTF_5
VSS_NCTF_2
AF32
U19
AC36
U24
VCC_12
VCC_AXG_NCTF_11
VCC_NCTF_6
VSS_NCTF_3
EDGE
CAVITY
U20
AD35
U28
VCC_AXG_NCTF_12
VCC_NCTF_7
VSS_NCTF_4
U21
AD36
V31
VCC_AXG_NCTF_13
VCC_NCTF_8
VSS_NCTF_5
U23
AF33
V35
VCC_AXG_NCTF_14
VCC_NCTF_9
VSS_NCTF_6
R30
U26
AF36
AA19
VCC_13
VCC_AXG_NCTF_15
VCC_NCTF_10
VSS_NCTF_7
V16
AH33
AB17
VCC_AXG_NCTF_16
VCC_NCTF_11
VSS_NCTF_8
V17
AH35
AB35
VCC_AXG_NCTF_17
VCC_NCTF_12
VSS_NCTF_9
V19
AH36
AD19
VCC_AXG_NCTF_18
VCC_NCTF_13
VSS_NCTF_10
V20
AH37
AD37
VCC_AXG_NCTF_19
VCC_NCTF_14
VSS_NCTF_11
V21
AJ33
AF17
VCC_AXG_NCTF_20
VCC_NCTF_15
VSS_NCTF_12
V23
AJ35
AF35
VCC_AXG_NCTF_21
VCC_NCTF_16
VSS_NCTF_13
+VCC_GFXCORE
49,56
V24
AK33
AK17
VCC_AXG_NCTF_22
VCC_NCTF_17
VSS_NCTF_14
POWER
POWER
Y15
AK35
AM17
VCC_AXG_NCTF_23
VCC_NCTF_18
VSS_NCTF_15
Y16
These caps are cavity capacitors
AK36
AM24
VCC_AXG_NCTF_24
VCC_NCTF_19
VSS_NCTF_16
+V1.8_GMCH
7,10,45
Y17
AK37
AP26
VCC_AXG_NCTF_25
VCC_NCTF_20
VSS_NCTF_17
AU32
Y19
AD33
AP28
VCC_SM_1
VCC_AXG_NCTF_26
VCC_NCTF_21
VSS_NCTF_18
C535
C535
C523
C523
AU33
Y20
AJ36
AR15
VCC_SM_2
VCC_AXG_NCTF_27
VCC_NCTF_22
VSS_NCTF_19
+ + C204
C204
+ +
C524
C524
C517
C517
C556
C556
C592
C592
0.1uF
0.1uF
0.1uF
0.1uF
AU35
Y21
AM35
AR19
VCC_SM_3
VCC_AXG_NCTF_28
VCC_NCTF_23
VSS_NCTF_20
330uF
330uF
C195
C195
0.47uF
0.47uF
1uF
1uF
10uF
10uF
22uF
22uF
10%
10%
10%
10%
AV33
Y23
3
3
AL33
AR28
VCC_SM_4
VCC_AXG_NCTF_29
VCC_NCTF_24
VSS_NCTF_21
330uF
330uF
AW33
Y24
AL35
VCC_SM_5
VCC_AXG_NCTF_30
VCC_NCTF_25
AW35
Y26
AA33
VCC_SM_6
VCC_AXG_NCTF_31
VCC_NCTF_26
AY35
Y28
AA35
VCC_SM_7
VCC_AXG_NCTF_32
VCC_NCTF_27
BA32
Y29
AA36
VCC_SM_8
VCC_AXG_NCTF_33
VCC_NCTF_28
BA33
AA16
AP35
VCC_SM_9
VCC_AXG_NCTF_34
VCC_NCTF_29
BA35
AA17
AP36
VCC_SM_10
VCC_AXG_NCTF_35
VCC_NCTF_30
BB33
AB16
AR35
VCC_SM_11
VCC_AXG_NCTF_36
VCC_NCTF_31
C
C
BC32
AB19
AR36
VCC_SM_12
VCC_AXG_NCTF_37
VCC_NCTF_32
BC33
AC16
Y32
VCC_SM_13
VCC_AXG_NCTF_38
VCC_NCTF_33
BC35
AC17
Y33
VCC_SM_14
VCC_AXG_NCTF_39
VCC_NCTF_34
POWER
POWER
BD32
AC19
Y35
VCC_SM_15
VCC_AXG_NCTF_40
VCC_NCTF_35
BD35
AD15
Y36
VCC_SM_16
VCC_AXG_NCTF_41
VCC_NCTF_36
BE32
AD16
Y37
A3
VCC_SM_17
VCC_AXG_NCTF_42
VCC_NCTF_37
VSS_SCB1
BE33
AD17
T30
B2
VCC_SM_18
VCC_AXG_NCTF_43
VCC_NCTF_38
VSS_SCB2
BE35
AF16
T34
C1
VCC_SM_19
VCC_AXG_NCTF_44
VCC_NCTF_39
VSS_SCB3
BF33
AF19
T35
BL1
VCC_SM_20
VCC_AXG_NCTF_45
VCC_NCTF_40
VSS_SCB4
BF34
AH15
U29
BL51
VCC_SM_21
VCC_AXG_NCTF_46
VCC_NCTF_41
VSS_SCB5
BG32
AH16
U31
A51
VCC_SM_22
VCC_AXG_NCTF_47
VCC_NCTF_42
VSS_SCB6
BG33
AH17
U32
VCC_SM_23
VCC_AXG_NCTF_48
VCC_NCTF_43
BG35
AH19
U33
VCC_SM_24
VCC_AXG_NCTF_49
VCC_NCTF_44
BH32
AJ16
U35
VCC_SM_25
VCC_AXG_NCTF_50
VCC_NCTF_45
BH34
AJ17
U36
VCC_SM_26
VCC_AXG_NCTF_51
VCC_NCTF_46
BH35
AJ19
V32
VCC_SM_27
VCC_AXG_NCTF_52
VCC_NCTF_47
BJ32
AK16
V33
VCC_SM_28
VCC_AXG_NCTF_53
VCC_NCTF_48
BJ33
AK19
V36
VCC_SM_29
VCC_AXG_NCTF_54
VCC_NCTF_49
48,56 +V1.05M
BJ34
AL16
V37
VCC_SM_30
VCC_AXG_NCTF_55
VCC_NCTF_50
BK32
AL17
VCC_SM_31
VCC_AXG_NCTF_56
BK33
AL19
AT33
VCC_SM_32
VCC_AXG_NCTF_57
VCC_AXM_1
BK34
AL20
AT31
VCC_SM_33
VCC_AXG_NCTF_58
VCC_AXM_2
BK35
AL21
AK29
+V1.05M48,56
VCC_SM_34
VCC_AXG_NCTF_59
VCC_AXM_3
BL33
AL23
AK24
VCC_SM_35
VCC_AXG_NCTF_60
VCC_AXM_4
AU30
AM15
AK23
VCC_SM_36
VCC_AXG_NCTF_61
VCC_AXM_5
AM16
AL24
AJ26
VCC_AXG_NCTF_62
VCC_AXM_NCTF_1
VCC_AXM_6
AM19
AL26
AJ23
VCC_AXG_NCTF_63
VCC_AXM_NCTF_2
VCC_AXM_7
+VCC_GFXCORE
49,56
C500
C500
C480
C480
C509
C509
AM20
C472
C472
AL28
VCC_AXG_NCTF_64
VCC_AXM_NCTF_3
C495
C495
C496
C496
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
AM21
22uF
22uF
AM26
VCC_AXG_NCTF_65
VCC_AXM_NCTF_4
0.22uF
0.22uF
0.22uF
0.22uF
R20
AM23
10%
10%
10%
10%
10%
10%
AM28
VCC_AXG_1
VCC_AXG_NCTF_66
VCC_AXM_NCTF_5
T14
AP15
AM29
VCC_AXG_2
VCC_AXG_NCTF_67
VCC_AXM_NCTF_6
W13
AP16
AM31
B
VCC_AXG_3
VCC_AXG_NCTF_68
VCC_AXM_NCTF_7
B
W14
AP17
AM32
VCC_AXG_4
VCC_AXG_NCTF_69
Edge
Cavity
VCC_AXM_NCTF_8
Y12
AP19
AM33
VCC_AXG_5
VCC_AXG_NCTF_70
VCC_AXM_NCTF_9
AA20
AP20
AP29
VCC_AXG_6
VCC_AXG_NCTF_71
VCC_AXM_NCTF_10
AA23
AP21
AP31
VCC_AXG_7
VCC_AXG_NCTF_72
VCC_AXM_NCTF_11
AA26
AP23
AP32
VCC_AXG_8
VCC_AXG_NCTF_73
VCC_AXM_NCTF_12
AA28
AP24
AP33
VCC_AXG_9
VCC_AXG_NCTF_74
VCC_AXM_NCTF_13
AB21
AR20
AL29
VCC_AXG_10
VCC_AXG_NCTF_75
VCC_AXM_NCTF_14
AB24
AR21
AL31
VCC_AXG_11
VCC_AXG_NCTF_76
VCC_AXM_NCTF_15
AB29
AR23
AL32
VCC_AXG_12
VCC_AXG_NCTF_77
VCC_AXM_NCTF_16
AC20
AR24
AR31
VCC_AXG_13
VCC_AXG_NCTF_78
VCC_AXM_NCTF_17
AC21
AR26
AR32
VCC_AXG_14
VCC_AXG_NCTF_79
VCC_AXM_NCTF_18
AC23
V26
AR33
VCC_AXG_15
VCC_AXG_NCTF_80
VCC_AXM_NCTF_19
AC24
V28
+V1.8 10,13,14,18,45,47,56
VCC_AXG_16
VCC_AXG_NCTF_81
+V1.8_GMCH
7,10,45
AC26
V29
VCC_AXG_17
VCC_AXG_NCTF_82
AC28
Y31
VCC_AXG_18
VCC_AXG_NCTF_83
R85
R85
0.002
0.002
AC29
VCC_AXG_19
1%
1%
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
AD20
VCC_AXG_20
AD23
VCC_AXG_21
VCC_SM_LF1_C
AD24
AW45
VCC_AXG_22
VCC_SM_LF1
VCC_SM_LF2_C
+ + C437
C437
C106
C106
C101
C101
C483
C483
AD28
BC39
VCC_AXG_23
VCC_SM_LF2
330uF
330uF
VCC_SM_LF3_C
22uF
22uF
22uF
22uF
0.1uF
0.1uF
AF21
BE39
VCC_AXG_24
VCC_SM_LF3
VCC_SM_LF4_C
10%
10%
AF26
BD17
VCC_AXG_25
VCC_SM_LF4
VCC_SM_LF5_C
AA31
BD4
VCC_AXG_26
VCC_SM_LF5
VCC_SM_LF6_C
AH20
AW8
VCC_AXG_27
VCC_SM_LF6
VCC_SM_LF7_C
AH21
AT6
VCC_AXG_28
VCC_SM_LF7
AH23
VCC_AXG_29
AH24
VCC_AXG_30
AH26
C541
C541
C538
C538
C554
C554
C536
C536
C470
C470
C2032
C2032
C454
C454
VCC_AXG_31
0.1uF
0.1uF
0.1uF
0.1uF
0.22uF
0.22uF
0.22uF
0.22uF
0.47uF
0.47uF
1uF
1uF
1uF
1uF
AD31
VCC_AXG_32
10%
10%
10%
10%
AJ20
VCC_AXG_33
AN14
VCC_AXG_34
A
A
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Oakmont Form Factor Reference Design
Intel Confidential
Intel Confidential
Intel Confidential
Title
Title
Title
CRESTLINE_1p0_OAKMONT
CRESTLINE_1p0_OAKMONT
CRESTLINE (4 OF 6)
CRESTLINE (4 OF 6)
CRESTLINE (4 OF 6)
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A
A
A
Date:
Date:
Date:
Sheet
Sheet
Sheet
9
9
9
of
of
of
64
64
64
5
4
3
2
1
12
VCC CORE
VCC CORE
VCC SMVCC
VCC SMVCC
GFX
GFX
VCC GFX NCTF
VCC GFX NCTF
VCC SM LF
VCC SM LF
12
12
VCC NCTF
VCC NCTF
VCC AXM NCTF
VCC AXM NCTF
VSS NCTF
VSS NCTF
VSS SCBVCC
VSS SCBVCC
AXM
AXM
5 4 3 2 1 +V1.25S 24,56,57 5,7,9,16 19,22 26,28,30,32 34,38,40,42,44,45,49,50,52,55 58 +V3.3S +V1.25S_DPLLA
5
4
3
2
1
+V1.25S
24,56,57
5,7,9,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
+V1.25S_DPLLA
NOTE
Place caps on this page close
to GMCH
10uH
10uH
+V3.3S
5,7,9,16 19,22 26,28,30,32 34,38,40,42,44,45,49,50,52,55 58
+V1.05S
3,4,6,9,20,21,24,45,48,54,56
L3
L3
C497
C497
1
2
10%
10%
0.1uF
0.1uF
C424
C424
C91
C91
10%
10%
U17H
U17H
Customer
470uF
470uF
0.1uF
0.1uF
Keep C112 near
+ + C208
C208
Recommended bulk
10%
10%
A33 and B33
J32
U13
VCCSYNC
VTT_1
220uF
220uF
Cap
R82
R82
C568
C568
C177
C177
C187
C187
U12
10%
10%
VTT_2
270uF
270uF
FB9
FB9
V3.3S_CRTDAC_FB
V3.3S_CRTDAC
C578
C578
4.7uF
4.7uF
C176
C176
2.2uF
2.2uF
1
3
A33
U11
VCCA_CRT_DAC_1
VTT_3
180ohm@100MHz
180ohm@100MHz
22nF
22nF
C110
C110
B33
U9
4.7uF
4.7uF
10%
10%
0.47uF
0.47uF
10%
10%
VCCA_CRT_DAC_2
VTT_4
+V1.25S_DPLLB
0.1uF
0.1uF
10%
10%
U8
VTT_5
10uH
10uH
10%
10%
+V3.3S_BGDAC_VCCA_TV
U7
VTT_6
L2
L2
1
2
A30
U5
VCCA_DAC_BG
VTT_7
D
U3
D
VTT_8
10%
10%
C65
C65
C86
C86
Keep C516 and FB11
B32
U2
VSSA_DAC_BG
VTT_9
470uF
470uF
0.1uF
0.1uF
5,7,9,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
close to source
U1
VTT_10
10%
10%
FB11
FB11
R102
R102
+V1.25S_DPLLA
T13
VTT_11
V3.3S_CRTDAC
BG_FB
1
3
+V1.25S_DPLLB
B49
T11
VCCA_DPLLA
VTT_12
22nF
22nF
T10
+V1.25M_HPLL
VTT_13
180ohm@100MHz
180ohm@100MHz
C516
C516
C126
C126
H49
T9
VCCA_DPLLB
VTT_14
+V1.25M
7,37,48,56,57
10uF
10uF
0.1uF
0.1uF
T7
VTT_15
+V1.25M_HPLL
10%
10%
AL2
T6
VCCA_HPLL
VTT_16
+V1.25M_MPLL
T5
VTT_17
FB12
FB12
+V1.8_TXLVDS
+V1.25M
7,37,48,56,57
AM2
T3
VCCA_MPLL
VTT_18
1
2
T2
VTT_19
R3
VTT_20
120ohm@100MHz
120ohm@100MHz
R594
R594
Placeholder
A41
R2
C174
C174
VCCA_LVDS
VTT_21
C184
C184
Place near A41
C96
C96
0
0
for 5.6nH
R1
0.1uF
0.1uF
VTT_22
inductor
22uF
22uF
1000pF
1000pF
B41
10%
10%
VSSA_LVDS
10%
10%
24,56,57
+V1.25S
+V1.25M_MPLL
VCC_AXD[1_6]
AT23
VCC_AXD_1
FB13
FB13
C519
C519
C525
C525
AU28
VCC_AXD_2
1.0uF
1.0uF
22uF
22uF
R134
R134
1
2
K50
AU24
VCCA_PEG_BG
VCC_AXD_3
C87
C87
NO_STUFF
NO_STUFF
Placeholder
0
0
AT29
VCC_AXD_4
402
120ohm@100MHz
R183
R183
402
120ohm@100MHz
5,7,9,16
19,22
26,28,30,32
34,38,40,42,44,45,49,50,52,55
58
+V3.3S
0.1uF
0.1uF
for 0.1uH
K49
AT25
0.5
0.5
VSSA_PEG_BG
VCC_AXD_5
inductor
C175
C175
10%
10%
+V1.25S_PEGPLL
AT30
1%
1%
VCC_AXD_6
0.1uF
0.1uF
+V1.25M_MPLL_R
10%
10%
U51
AR29
VCCA_PEG_PLL
VCC_AXD_NCTF
C186
C186
VCC_AXF[1_3]
22uF
22uF
C85
C85
+V1.25M_A_SM
24,56,57
+V1.25S
0.1uF
0.1uF
C130
C130
C134
C134
AW18
B23
VCCA_SM_1
VCC_AXF_1
10%
10%
1.0uF
1.0uF
10uF
10uF
AV19
VCCA_SM_2
POWER
POWER
B21
VCC_AXF_2
AU19
A21
VCCA_SM_3
VCC_AXF_3
402
402
+V1.8_SM_CK
NO_STUFF
NO_STUFF
AU18
VCCA_SM_4
7,9,45
+V1.8_GMCH
AU17
AJ50
C83
C83
VCCA_SM_5
VCC_DMI
C
+V1.8_SM_CK
0.1uF
0.1uF
C
1uH
1uH
10%
10%
AT22
VCCA_SM_7
L5
L5
7,37,48,56,57
+V1.25M
1
2
AT21
BK24
VCCA_SM_8
VCC_SM_CK_1
AT19
BK23
VCCA_SM_9
VCC_SM_CK_2
C133
C133
Placeholder
AT18
BJ24
C132
C132
VCCA_SM_10
VCC_SM_CK_3
R128
R128
1.00
1.00
+V1.8_SMCK_RC
22uF
22uF
R589
R589
for inductor
0.1uF
0.1uF
AT17
BJ23
VCCA_SM_11
VCC_SM_CK_4
1%
1%
0
0
10%
10%
AR17
VCCA_SM_NCTF_1
C137
C137
AR16
VCCA_SM_NCTF_2
10uF
10uF
+V1.8_TXLVDS
A43
VCC_TX_LVDS
TVO Supplies must be powered even if TV is
VCCA_SM_CK[1_2]
BC29
VCCA_SM_CK_1
not used.
+V3.3S_HV
C99
C99
Place near A43
BB29
VCCA_SM_CK_2
Seperate LDO must be used if TV is
C512
C512
C498
C498
C507
C507
C508
C508
+V3.3S_BGDAC_VCCA_TV
1000pF
1000pF
C40
enabled.(This design has TV disabled)
VCC_HV_1
180pF
180pF
180pF
180pF
0.1uF
0.1uF
22uF
22uF
10%
10%
C25
B40
VCCA_TVA_DAC_1
VCC_HV_2
5%
5%
5%
5%
10%
10%
B25
7
+VCC_PEG
VCCA_TVA_DAC_2
R602 to be
NO_STUFF
NO_STUFF
NO_STUFF
NO_STUFF
C27
VCCA_TVB_DAC_1
used if
B27
AD51
VCCA_TVB_DAC_2
VCC_PEG_1
3.9nH needs
+V1.25M_A_SM
B28
W50
to be
VCCA_TVC_DAC_1
VCC_PEG_2
4,18,24
26,48,56
+V1.5S
A28
W51
stuffed
VCCA_TVC_DAC_2
VCC_PEG_3
+V1.25M