Laptop Schematic Diagram 845 (Merom-Crestline Mobile Platform)

5 4 3 2 1
MEROM/CRESTLINE
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FORM FACTOR REFERENCE DESIGN REV 1.1
co
D D
Crestline Crestline
.
Fan IMVP VR Clocking VCCP VR
PWM
Merom/Penryn GFX VR
Header Pages 52-54 PG 37 PG 49 PG 48
s
PG 5 478 uFCPGA
DB200
ITP PG 38
it c
CPU
CRT
Thermal PG 3,4 PG 20
SYSTEM Discharge DDR VR
Sensor
SODIMM0
LVDS/ALS/BLI PG 16 PG 5 PG 56 PG 47
FSB Dual Channel
PG 17
SODIMM1
DDR2
a
VGA
Crestline SYSTEM VR
HDMI Pages 13-15
LVDS 1299 PG 46
PG 18
FCBGA
m
SDVO Pages
C Azalia HDMI SLEEP CONTROL C
6-11
e
Port Header Controller
PG 57
USB0 PG 19
PG 29
h
X4 DMI
Port Header C-LINK BATTERY CHARGER VR
interface
c
USB1
PG 29 SATA HDD
CardBus PG 51
PG 30 PG 33,34
-s
Sky Forest
SATA Dock SATA PORT 0 33 Mhz PCI
USB2
PG 26
PG 45
ICH8-M C-LINK
Minicard 1 MOBILE POWER
SATA PORT 2 PG 25 ON SEQUENCE
Port Header Dock PCIEx1 (LANE1) PG 55
676
p
USB3 PG 45
PG 29 BGA PCIEx1 (LANE2) Minicard 2
PG 25
PATA PCIEx1 (LANE3)
o
Port Header ODD
ODD PG 62 Pages 21-24 PCIEx1
PG 32 (LANE4)
t
B USB4 Interposer PG Sky Forrest B
HDR
PG 29 PCIEx1 (LANE5) 26 PGS 68-69
USB 2.0 AIC
Expresscard & IR
GLCI (LANE6)
p
MINICARD
DOCKING
USB5 Azalia
Dock PG 45
PG 25
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SPI
PG 45 Azalia
MINICARD RJ11 RJ45
Nineveh LAN LAN Switch
.
USB6 MDC PG 35 PG 36
PG 25 Page 27
LPC, 33MHz
I/O Xpander
PG 39
BLUETOOTH Nut Tree
Audio Nut Tree
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USB7 Page 28 HDR SPI SPI Dock
PG 41 Audio PG 61 PG 45
PG 58 TPM Flash Flash
PG 44 PG 36 PG 36
DOCKING
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USB8
PG 45
A
SIO SMC/KSC Touch Pad A
Sky Forest Serial Header PG 40 HDR Oakmont Form Factor Reference Design Intel Confidential
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USB9 PG 42 Title
PG 26 PG 31 Title Page
Size Document Number Rev

SCN KBD Touch Pad A
Keyboard HDR PG 31
Date: Sheet 1 of 64
5 4 3 2 1
5 4 3 2 1
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OAKMONT FORM FACTOR REFERENCE PLATFORM
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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
it cs
2
I C / SMB Addresses
Voltage Rails System Support
Device Refdes Binary Hex Bus *
POWER PLANE VOLTAGE ACTIVE IN DESCRIPTION Clock Generator U32 1101 001x D2 SMB_ICH_M3 Part Reference Feature/Function Strapping
+VBATA 9V-12.5V S0 to S5, M0 to M-off Battery Rail in Mobile Power Mode DB200 Clock Buffer U7 1101 110x DC SMB_ICH_M3
+VBAT 9V-12.5V S0 to S5, M0 to M-off Battery Rail in Mobile Power Mode SO-DIMM0 J8 1010 000x A0 SMB_ICH_M2 J6 ITP Connector
+V5A 5V S0 to S5, M0 to M-off SO-DIMM1 J9 1010 010x A4 SMB_ICH_M2 J19 Boot BIOS Strap
+V5 5V S0/M0, S3/M1, S3/M-off SO-DIMM0 Thermal Sensor J8 0011 000x 30 SMB_ICH_M2 J20 H8 Program Shunt header Default (1 2)
SO-DIMM1 Thermal Sensor J9 0011 010x 34 SMB_ICH_M2 H8 External Reflash Connector
a
+V5S 5V S0/M0 J21 Default (1 2)
+V3.3A 3.3V S0 to S5, M0 to M-off DDR Thermal Sensor U6 0100 110x 4C SMB_ICH_M2 J23 SIO Program Header
+V3.3M 3.3V S0 to S5, M0, M1 Board ID Port Expander U35 0011 000x 30 SMB_BS
+V3.3 3.3V S0/M0, S3/M1, S3/M-off Ambient Light Sensor J7 0111 001x 72 ALS
+V3.3S 3.3V S0/M0 CPU Thermal Sensor U19 0100 110x 4C SMB_THRM
+V1.5S 1.5V S0/M0 IMVP6 Amb. Temp. Sensor U5 1001 101x 9A SMB_THRM
+V1.8 1.8V S0/M0, (S3 to S5)/M1, S3/M-off DDR core Battery J4 0001 011x 16 SMB_BS
+V0.9 0.9V S0/M0, (S3 to S5)/M1, S3/M-off DDR command & control pull up. H8 U60 TBD TBD SMB_ME
+V1.25M 1.25V S0/M0, S3/M1, S3/M-off TPM U59 0100 1110 4E LPC
m
+V1.25S 1.25V S0/M0 5-CH-I2C HUB U63 0011 xxxx 3x SMB_ICH
Minicard 1 J39 N/A N/A SMB_ICH_A1
+V1.05S
+V1.05M
1.05V
1.05V
S0/M0
S0/M0, S3/M1, S3/M-off
GMCH, ICH core, and FSB rail
Minicard 2 J32 N/A N/A SMB_ICH_A1
Interposer Add-In-Cards
+VCC_CORE 0.700V-1.77V S0/M0 CPU core rail Express Card J2000 N/A N/A SMB_ICH_A1 REF DEZ Feature Support Bus Supported Power Requirements
C +VCC_GFXCORE 0.7V-1.25V S0/M1 GMCH Graphics core rail C
e
Sky Forest CR2000 LED_NETDETECT N/A
CR2001 LED_PWR-GD/TURBO N/A +V5S
Page 63 & 64 CR2002 LED_S3 N/A
J2000 EXPRESSCARD 54MM CONNECTOR PCIEx1 (LANE3)
+V3.3S
USB (PORT 2) +V3.3A
h
J2001 SPEAKER HEADER AUDIO FROM CODEC (Azalia) +V1.5S
Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. J2002 60-Pin Plug N/A
The rest come out of EC. SW2000 NETDETECT SWITCH N/A
SW2001 LID SWITCH N/A
U2007 IRDA IR (LPC)
c
CR3000 LED_WWAN N/A
Nut Tree CR3001 LED_WLAN N/A Power supplied
CR3002 LED_BLUE TOOTH N/A
Page 61 CR3003 LED_Caps-lock N/A
by LED driving
SOT-23 SOT23-5 Net Naming Conventions signals
1 1 5 CR3004 LED_Num-lock N/A
s
Suffix CR3005 LED_HDD Activity N/A
# = Active Low Signal CR3006 LED_S3 N/A
3 As seen from top 2 CR3007 LED_Battery (Full/Low) N/A
-
Prefix CR3008 LED_PWR-GD/TURBO N/A
H = Host MIC3000 Microphone AUDIO FROM CODEC (Azalia)
2 3 4 M = DDR Memory SW3000 POWER_SWITCH SYSTEM_GROUND
TP = Test Point (does not connect anywhere else) SW3001 RF_KILL_SWITCH SYSTEM_GROUND
p
ODD 50-PIN DVD RECEPTACLE (Short)
J4000 Connects to Oakmont PB IDE +V5S
Interposer
Page 62 50-PIN DVD RECEPTACLE (Long)
J4001 Connects to ODD IDE
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B B
Power States
Wake Events
SIGNAL
p
SLP SLP SLP S4 SLP +V*A +V*M +V* +V*S Clocks
S3# S4# S5# STATE# M# Wake Events State Supported
STATE RI# from serial port S3
PME# from Cardbus S3
S0 (Full ON) /M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON Mini-card, Express-card wake event S3
la
Wake on LAN S3/M1
LID switch attached to SMC S3
S3 (Suspend to RAM) / M1 LOW HIGH OFF ON USB S3
HIGH HIGH HIGH ON ON ON HDA wake on ring S3
SmLink for AOLII S3
.
OFF Hot Key from Scan matrix keyboard S3
S4 (Suspend To Disk) /M1 LOW HIGH ON OFF ON
HIGH HIGH LOW ON (DDR ON) PWRBTN# S3
Netdetect S3, S4, S5 / M1
S5 (Soft OFF) /M1 LOW HIGH HIGH ON ON ON OFF ON
LOW LOW
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S3 (Suspend to RAM) / M-Off LOW HIGH HIGH HIGH OFF ON OFF OFF
LOW ON
S4 (Suspend To Disk) /M-Off LOW OFF OFF OFF OFF

LOW HIGH LOW LOW ON
S5 (Soft OFF) /M-Off LOW OFF OFF OFF OFF
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LOW LOW LOW LOW ON
A Oakmont Form Factor Reference Design Intel Confidential A
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Title
NOTES

A
Date: Sheet 2 of 64
5 4 3 2 1
5 4 3 2 1
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4,6,9,10,20,21,24,45,48,54,56 +V1.05S
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6 H_A#[35:3]
U22A
H_A#3 J4 H1 R613
A[3]# ADS# H_ADS# 6 56
H_A#4 L5 E2
A[4]# BNR# H_BNR# 6
ADDR GROUP 0
H_A#5 L4 G5
c
A[5]# BPRI# H_BPRI# 6
H_A#6 K5
H_A#7 A[6]#
M3 H5 H_DEFER# 6
D H_A#8 N2
A[7]# DEFER#
F21 D
.
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 6
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ# 6
H_A#12 P2
CONTROL
H_A#13 A[12]# IERR#
L2 D20
s
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# 21
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# 6
6 H_ADSTB#0 M1 ADSTB[0]# H_CPURST# 6,20
C1
it c
6 H_REQ#[4:0] RESET# H_RS#[2:0] 6
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 6
H_REQ#4 L1 REQ[4]#
6 H_A#[35:3] HIT# G6 H_HIT# 6
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 6
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4 ITP_BPM#0 20
H_A#20 W6 AD3
A[20]# BPM[1]# ITP_BPM#1 20
a
ADDR GROUP 1
XDP/ITP SIGNALS
H_A#21 U4 AD1
A[21]# BPM[2]# ITP_BPM#2 20
H_A#22 Y5 AC4
A[22]# BPM[3]# ITP_BPM#3 20
H_A#23 U1 AC2
A[23]# PRDY# ITP_BPM#4 20
H_A#24 R4 AC1 ITP_BPM#5 20
H_A#25 A[24]# PREQ#
T5 A[25]# TCK AC5 ITP_TCK 20
H_A#26 T3 AA6
A[26]# TDI ITP_TDI 20
H_A#27 W2 AB3 +V1.05S 4,6,9,10,20,21,24,45,48,54,56
A[27]# TDO ITP_TDO 20
H_A#28 W5 AB5
A[28]# TMS ITP_TMS 20
H_A#29
m
Y4 A[29]# TRST# AB6 ITP_TRST# 20
H_A#30 U2 C20
A[30]# DBR# ITP_DBRESET# 20,55
H_A#31 V4 R612
A[31]# 6 H_D#[63:0] H_D#[63:0] 6
H_A#32 W3 75 U22B
H_A#33 A[32]# H_D#0 H_D#32
AA4 A[33]# THERMAL E22 D[0]# D[32]# Y22
H_A#34 AB2 H_D#1 F24 AB24 H_D#33
e
C H_A#35 A[34]# H_D#2 D[1]# D[33]# H_D#34 C
AA3 A[35]# PROCHOT# D21 H_PROCHOT# 52 E26 D[2]# D[34]# V24
V1 A24 H_D#3 G22 V26 H_D#35
6 H_ADSTB#1 ADSTB[1]# THERMDA H_THERMDA 5 D[3]# D[35]#
DATA GRP 0
B25 H_D#4 F23 V23 H_D#36
THERMDC H_THERMDC 5 D[4]# D[36]#
A6 PM_THRMTRIP# should connect H_D#5 G25 T22 H_D#37
21 H_A20M# A20M# D[5]# D[37]#
ICH
A5 C7 to ICH8 and GMCH without H_D#6 E25 U25 H_D#38

21 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 7,21 D[6]# D[38]#
H_D#7 H_D#39
h
21 H_IGNNE# C4 IGNNE# T-ing (No stub) E23 D[7]# D[39]# U23
H_D#8 K24 Y25 H_D#40
D[8]# D[40]#
DATA GRP 2
D5 H_D#9 G24 W22 H_D#41
21 H_STPCLK# STPCLK# D[9]# D[41]#
C6 H CLK H_D#10 J24 Y23 H_D#42
21 H_INTR LINT0 D[10]# D[42]#
B4 A22 H_D#11 J23 W24 H_D#43
21 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 37 D[11]# D[43]#
H_D#12 H_D#44
c
21 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 37 H22 D[12]# D[44]# W25
H_D#13 F26 AA23 H_D#45
TP_CPU_RSVD01 M4 H_D#14 D[13]# D[45]# H_D#46
RSVD[01] K22 D[14]# D[46]# AA24
TP_CPU_RSVD02 N5 H_D#15 H23 AB25 H_D#47
TP_CPU_RSVD03 T2 RSVD[02] D[15]# D[47]#
RSVD[03] 6 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 6
TP_CPU_RSVD04 V3
s
RSVD[04] 6 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 6
RESERVED
TP_CPU_RSVD05 B2 H25 U22

RSVD[05] 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
TP_CPU_RSVD06 C3
RSVD[06] 6 H_D#[63:0] H_D#[63:0] 6
TP_CPU_RSVD07 D2
-
TP_CPU_RSVD08 D22 RSVD[07] H_D#16 H_D#48
RSVD[08] N22 D[16]# D[48]# AE24
TP_CPU_RSVD09 D3 H_D#17 K25 AD24 H_D#49
TP_CPU_RSVD10 F6 RSVD[09] H_D#18 D[17]# D[49]# H_D#50
RSVD[10] P26 D[18]# D[50]# AA21
H_D#19 R23 AB22 H_D#51
H_D#20 D[19]# D[51]# H_D#52
L23 D[20]# D[52]# AB21
DATA GRP 1
p
H_D#21 M24 AC26 H_D#53
Merom Ball-out Rev 1a_Oakmont H_D#22 D[21]# D[53]# H_D#54
L22 D[22]# D[54]# AD20
H_D#23 M23 AE22 H_D#55 Layout note:
H_D#24 D[23]# D[55]# H_D#56 Comp0,2 connect with Zo=27.4ohm (14
P25 D[24]# D[56]# AF23
Layout Note: H_D#25 P23 AC25 H_D#57 mils width on SL, 18 mils width on
H_D#26 D[25]# D[57]# H_D#58 MS), make trace length shorter than
1. Leave Escape routing for TP_CPU_RSVD[01:06] Signals for future functionality. P22 AE21
o
D[26]# D[58]#
DATA GRP 3
H_D#27 T24 AD21 H_D#59 0.5".
2. Route TP_CPU_RSVD[07:10] signals to TP via and place gnd via w/in 100mils. D[27]# D[59]# Comp1,3 connect with Zo=55ohm, make
4,6,9,10,20,21,24,45,48,54,56 +V1.05S H_D#28 R24 AC22 H_D#60
H_D#29 D[28]# D[60]# H_D#61 trace length shorter than 0.5".
L25 AD23
t
H_D#30 D[29]# D[61]# H_D#62
T25 D[30]# D[62]# AF22
H_D#31 N25 AC23 H_D#63
B R610 D[31]# D[63]# B
6 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 6
1K
1% 6 H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 6
6 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 6
p
Layout note: Zo=55 ohm, H_GTLREF AD26 R26 COMP0 R604 27.4 1%
CPU_TEST01 GTLREF COMP[0] COMP1 R605 54.9 1%
0.5" max for GTLREF. C23 TEST1 MISC COMP[1] U26
CPU_TEST02 D25 AA1 COMP2 R521 27.4 1%
R609 TP_CPU_TEST03 C24 TEST2 COMP[2] COMP3 R519 54.9 1%
TEST3 COMP[3] Y1
2K CPU_TEST4 AF26
la
1% TP_CPU_TEST05 AF1 TEST4
TEST5 DPRSTP# E5 H_DPRSTP# 7,21,52
TP_CPU_TEST06 A26 B5
TEST6 DPSLP# H_DPSLP# 21
1K
1K
1%
1%
10%
C550 0.1uF
DPWR# D24 H_DPWR# 6
NO_STUFF
B22 BSEL[0] PWRGOOD D6 H_PWRGD 21
7,37 MCH_BSEL0
NO_STUFF
NO_STUFF
B23 D7
.
7,37 MCH_BSEL1 BSEL[1] SLP# H_CPUSLP# 6
C21 BSEL[2] PSI# AE6 PSI# 52
7,37 MCH_BSEL2
R623
R611
Merom Ball-out Rev 1a_Oakmont
w
Place C552 close to the CPU_TEST4 pin.
Make sure CPU_TEST4 routing is reference
to GND and away from other noisy signals.
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A A
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Oakmont Form Factor Reference Design Intel Confidential
Title
Merom (1 of 2)

Custom
Date: Sheet 3 of 64
5 4 3 2 1
5 4 3 2 1
53,54,56 +VCC_CORE
A7
U22C
53,54,56
AB20
+VCC_CORE
o m
c
VCC[001] VCC[068]
A9 VCC[002] VCC[069] AB7
A10 AC7
D A12
VCC[003] VCC[070]
AC9 D
.
VCC[004] VCC[071]
A13 VCC[005] VCC[072] AC12
A15 VCC[006] VCC[073] AC13
A17 VCC[007] VCC[074] AC15
A18 VCC[008] VCC[075] AC17
A20 AC18
s
VCC[009] VCC[076]
B7 VCC[010] VCC[077] AD7
B9 VCC[011] VCC[078] AD9
B10 AD10 U22D
VCC[012] VCC[079]
B12 VCC[013] VCC[080] AD12 A4 VSS[001] VSS[082] P6
B14 AD14 A8 P21
it c
VCC[014] VCC[081] VSS[002] VSS[083]
B15 VCC[015] VCC[082] AD15 A11 VSS[003] VSS[084] P24
B17 VCC[016] VCC[083] AD17 A14 VSS[004] VSS[085] R2
B18 VCC[017] VCC[084] AD18 A16 VSS[005] VSS[086] R5
B20 VCC[018] VCC[085] AE9 A19 VSS[006] VSS[087] R22
C9 VCC[019] VCC[086] AE10 A23 VSS[007] VSS[088] R25
C10 VCC[020] VCC[087] AE12 AF2 VSS[008] VSS[089] T1
C12 VCC[021] VCC[088] AE13 B6 VSS[009] VSS[090] T4
C17 VCC[024] VCC[091] AE18 B13 VSS[012] VSS[093] U3
a
C18 VCC[025] VCC[092] AE20 B16 VSS[013] VSS[094] U6
D9 VCC[026] VCC[093] AF9 B19 VSS[014] VSS[095] U21
D10 VCC[027] VCC[094] AF10 B21 VSS[015] VSS[096] U24
D12 VCC[028] VCC[095] AF12 B24 VSS[016] VSS[097] V2
D14 VCC[029] VCC[096] AF14 C5 VSS[017] VSS[098] V5
D18 AF18 +V1.05S 3,6,9,10,20,21,24,45,48,54,56 C14 W1
VCC[032] VCC[099] VSS[020] VSS[101]
m
E7 VCC[033] VCC[100] AF20 C16 VSS[021] VSS[102] W4
E9 VCC[034] C19 VSS[022] VSS[103] W23
E10 VCC[035] VCCP[01] G21 C2 VSS[023] VSS[104] W26
E12 VCC[036] VCCP[02] V6 C22 VSS[024] VSS[105] Y3
1
E13 J6 Customer + C382 C542 C25 Y6
VCC[037] VCCP[03] Recommended 220uF 270uF VSS[025] VSS[106]
E15 K6 D1 Y21
e
C VCC[038] VCCP[04] bulk Cap 10% VSS[026] VSS[107] C
E17 M6 D4 Y24
2
VCC[039] VCCP[05] VSS[027] VSS[108]
E18 VCC[040] VCCP[06] J21 D8 VSS[028] VSS[109] AA2
E20 VCC[041] VCCP[07] K21 D11 VSS[029] VSS[110] AA5
F7 VCC[042] VCCP[08] M21 D13 VSS[030] VSS[111] AA8
F9 VCC[043] VCCP[09] N21 D16 VSS[031] VSS[112] AA11
h
F10 VCC[044] VCCP[10] N6 D19 VSS[032] VSS[113] AA14
F12 VCC[045] VCCP[11] R21 D23 VSS[033] VSS[114] AA16
F14 VCC[046] VCCP[12] R6 D26 VSS[034] VSS[115] AA19
F15 VCC[047] VCCP[13] T21 E3 VSS[035] VSS[116] AA22
F17 T6 10,18,24..26,48,56 +V1.5S E6 AA25
VCC[048] VCCP[14] VSS[036] VSS[117]
c
F18 VCC[049] VCCP[15] V21 E8 VSS[037] VSS[118] AB1
F20 VCC[050] VCCP[16] W21 E11 VSS[038] VSS[119] AB4
AA7 VCC[051] E14 VSS[039] VSS[120] AB8
AA9 VCC[052] VCCA[01] B26 E16 VSS[040] VSS[121] AB11
AA10 VCC[053] VCCA[02] C26 E19 VSS[041] VSS[122] AB13
53,54,56 +VCC_CORE C151 LAYOUT NOTE: PLACE C551
s
AA12 VCC[054] E21 VSS[042] VSS[123] AB16
AA13 AD6 C549 10uF NEAR PIN B26 E24 AB19
VCC[055] VID[0] H_VID0 52 0.01uF VSS[043] VSS[124]
AA15 VCC[056] VID[1] AF5 H_VID1 52 F5 VSS[044] VSS[125] AB23
AA17 AE5 10% F8 AB26
-
VCC[057] VID[2] H_VID2 52 VSS[045] VSS[126]
AA18 VCC[058] VID[3] AF4 H_VID3 52 F11 VSS[046] VSS[127] AC3
AA20 VCC[059] VID[4] AE3 H_VID4 52 F13 VSS[047] VSS[128] AC6
AB9 VCC[060] VID[5] AF3 H_VID5 52 F16 VSS[048] VSS[129] AC8
AC10 AE2 R524 F19 AC11
VCC[061] VID[6] H_VID6 52 100 VSS[049] VSS[130]
AB10 VCC[062] 1% F2 VSS[050] VSS[131] AC14
p
AB12 VCC[063] F22 VSS[051] VSS[132] AC16
AB14 AF7 Layout Note: F25 AC19
VCC[064] VCCSENSE VCCSENSE 52 Route VCCSENSE and VSSSENSE traces at VSS[052] VSS[133]
AB15 VCC[065] G4 VSS[053] VSS[134] AC21
AB17 27.4 Ohms with 50 mil spacing. G1 AC24
VCC[066] Place PU and PD within 1 inch of CPU. VSS[054] VSS[135]
AB18 VCC[067] VSSSENSE AE7 VSSSENSE 52 G23 VSS[055] VSS[136] AD2
G26 AD5
o
Merom Ball-out Rev 1a_Oakmont R525 VSS[056] VSS[137]
H3 VSS[057] VSS[138] AD8
100 H6 AD11
1% VSS[058] VSS[139]
H21 AD13
t
VSS[059] VSS[140]
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B J5 AD22 B
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
p
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 AE19
la
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 AF8
.
VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
AF25
w
VSS[163]
Merom Ball-out Rev 1a_Oakmont
w
A A
w
Title
Merom (2 of 2)

Custom
Date: Sheet 4 of 64
5 4 3 2 1
5 4 3 2 1
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
m
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
CPU Thermal Sensor
Layout Note: R116 R109
U19: Place at 10K 10K
Route H_THERMDA and C520
SouthEast corner of
H_THERMDC on same layer 0.1uF CPU, near
o
w/ 10 mil trace & 10 mil R596 H_THERMDA/C pins
spacing. Route away from 10K
noise sources with ground U29
guard tracks on each side. 1 VDD SCLK 8 SMB_THRM_CLK 42 Note: No-Stuff R141 for normal operation.
c
R103 499 ADT_THERM_DXP 2 7
3 H_THERMDA D+ SDATA SMB_THRM_DATA 42
D 1% C521 D
.
1000pF ADT_THERM_DXN 3 6 THRM_ALERT# R10525 0
D- ALRT#/THM2# PM_THRM# 23,42
R122 499 5% NO_STUFF
3 H_THERMDC 1% ADT_THM# 4 THM# GND 5
ADT7461A-TEMP MON
System thermal monitoring
it cs
a
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
m
C354 PLACE PULLUPS BY DEVICE
R484 0.1uF
Q95: Place below fan U5: Place north of
10K Q1: Place near
at west edge of board IMVP on primary side RHE at extreme
C SMB_THRM_CLK 42 North edge of C
e
3 7481_D1P R41 0 U7
SMB_THRM_DATA 42 board
1 VDD SCLK 10
1 C357 7481_D1P_R 2 9 3
7481_D1N_R D1+ SDATA 7481_THRM2#
1000pF 3 D1- ALRT#/THM2# 8
Q68 10% 4 7 7481_D2P C48 1 Q1
THM# D2+
h
2 2N3904 7481_D1N R42 0 7481_THRM# 5 6 7481_D2N 1000pF 2N3904
GND D2- 10%
ADT7481ARMZ-1 TEMP MON 2
c
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
R496
s
10K
-
R482 0
NO_STUFF
R483 0
p
PM_THRM# 23,42
NO_STUFF
t o
B B
CPU Fan Power Control
7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
p
16..18,24,26,28,30..32,34,49,50,52,53,56,57 +V5S
la
C136 C131
0.1uF 4.7uF
12
10
11
1
.
10% 10% EU2
V+ R591
8 _ 2 1.07k
TF
EN VOUT_OPAMP 1%
OPA567 OUT
R593 15K OPA567_POSIN 9
42 CPU_PWM_FAN + ISIF 3
1% HS
w
C533 V-
CPU_TACHO_FAN 42
1uF
10% 3
4
5
13
6
7
R603
1.74K Q70
OPA567_NEGIN
1% BAT54
OPA567_ISIN_R
w
1
3
2
1
2
1
3
2
1
2
1
A A
J12 J11 Oakmont Form Factor Reference Design Intel Confidential
w
CONN3_HDR CONN2_HDR
Title
R607
20K
R599
3.32K
CPU Thermal Sensor & Fan
1%

A
Date: Sheet 5 of 64
5 4 3 2 1
5 4 3 2 1
o m
U17A
H_A#[35:3] 3
J13 H_A#3
3 H_D#[63:0] H_A#_3
H_D#0 E2 B11 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
c
G2 H_D#_1 H_A#_5 C11
H_D#2 G7 M11 H_A#6
H_D#_2 H_A#_6
D H_D#3 M6 H_D#_3 H_A#_7 C15 H_A#7 D
.
H_D#4 H7 F16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H3 H_D#_5 H_A#_9 L13
H_D#6 G4 G17 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F3 H_D#_7 H_A#_11 C14
+V1.05S 3,4,9,10,20,21,24,45,48,54,56 H_D#8 N8 K16 H_A#12
s
H_D#9 H_D#_8 H_A#_12 H_A#13
H2 H_D#_9 H_A#_13 B13
H_D#10 M10 L16 H_A#14
H_D#11 H_D#_10 H_A#_14 H_A#15
N12 H_D#_11 H_A#_15 J17
R173 H_D#12 N9 B14 H_A#16
221 H_D#_12 H_A#_16
it c
H_D#13 H5 K19 H_A#17
1% H_SWING H_D#14 H_D#_13 H_A#_17 H_A#18
P13 H_D#_14 H_A#_18 P15
H_D#15 K9 R17 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
M2 H_D#_16 H_A#_20 B16
H_D#17 W10 H20 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 H_D#_18 H_A#_22 L19
H_D#19 V4 D17 H_A#23
R10526 H_D#20 H_D#_19 H_A#_23 H_A#24
M3 H_D#_20 H_A#_24 M17
100 C167 H_D#21 J1 N16 H_A#25
1% 0.1uF H_D#22 H_D#_21 H_A#_25 H_A#26
N5 H_D#_22 H_A#_26 J19
a
H_D#23 N3 B18 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
W6 H_D#_24 H_A#_28 E19
H_D#25 W9 B17 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N2 H_D#_26 H_A#_30 B15
H_D#27 Y7 E17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
Y9 H_D#_28 H_A#_32 C18
H_D#29 P4 A19 H_A#33
H_RCOMP H_D#30 H_D#_29 H_A#_33 H_A#34
W3 B19
m
H_D#31 H_D#_30 H_A#_34 H_A#35
N1 H_D#_31 H_A#_35 N19
H_D#32 AD12
R177 H_D#33 H_D#_32
AE3 G12
HOST
24.9 H_D#_33 H_ADS# H_ADS# 3
H_D#34 AD9 H17
1% H_D#_34 H_ADSTB#_0 H_ADSTB#0 3
C H_D#35 AC9 H_D#_35 H_ADSTB#_1 G20 H_ADSTB#1 3
C
e
H_D#36 AC7 C8
H_D#_36 H_BNR# H_BNR# 3
H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# 3
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BREQ# 3
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# 3
H_D#40 AB2 C10
H_D#_40 H_DBSY# H_DBSY# 3
h
H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK 37
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 37
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# 3
H_D#44 AC6 K7
H_D#_44 H_DRDY# H_DRDY# 3
+V1.05S 3,4,9,10,20,21,24,45,48,54,56 H_D#45 AE2 E4
c
H_D#_45 H_HIT# H_HIT# 3
H_D#46 AC5 C6
H_D#_46 H_HITM# H_HITM# 3
R175 54.9 H_SCOMP H_D#47 AG3 G10
1% H_D#48 H_D#_47 H_LOCK# H_LOCK# 3
AJ9 H_D#_48 H_TRDY# B7 H_TRDY# 3
H_D#49 AH8
H_D#50 H_D#_49
-s
AJ14 H_D#_50
R176 54.9 H_SCOMP# H_D#51 AE9
1% H_D#52 H_D#_51
AE11 H_D#_52
H_D#53 AH12 K5
H_D#_53 H_DINV#_0 H_DINV#0 3
H_D#54 AJ5 L2
H_D#55 AH5 AD13
H_D#56 AJ6 AE13
H_D#57 AE7
H_D#58 H_D#_57
AJ7 M7
p
H_D#_58 H_DSTBN#_0 H_DSTBN#0 3
H_D#59 AJ2 K3
H_D#60 AE5 AD2
H_D#61 AJ3 AH11
H_D#62 AH2
H_D#63 H_D#_62
AH13 L7
o
H_D#_63 H_DSTBP#_0 H_DSTBP#0 3
H_DSTBP#_1 K2 H_DSTBP#1 3
H_DSTBP#_2 AC2 H_DSTBP#2 3
t
H_SWING B3 AJ10
B H_SWING H_DSTBP#_3 H_DSTBP#3 3 B
Note: H_CPURST# H_RCOMP C2 H_RCOMP H_REQ#[4:0] 3
M14 H_REQ#0
has T topology H_SCOMP W1
H_REQ#_0
E13 H_REQ#1
H_SCOMP# H_SCOMP H_REQ#_1 H_REQ#2
W2 H_SCOMP# H_REQ#_2 A11
H_REQ#3
p
H_REQ#_3 H13
B6 B12 H_REQ#4
3,20 H_CPURST# H_CPURST# H_REQ#_4
3 H_CPUSLP# E5 H_CPUSLP# H_RS#[2:0] 3
E12 H_RS#0
H_RS#_0 H_RS#1
H_RS#_1 D7
3,4,9,10,20,21,24,45,48,54,56 +V1.05S D8 H_RS#2
la
H_RS#_2
B9 H_AVREF
A9 H_DVREF
R154
1K CRESTLINE_1p0_OAKMONT
1%
.
H_VREF
R146 C149
2K 0.1uF
w
1% 10%
w
A A
w
Title
CRESTLINE (1 OF 6)

A
Date: Sheet 6 of 64
5 4 3 2 1
5 4 3 2 1
U17B 5,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S R84 10K CLK_MCH_OE#
1%
TP_MCH_RSVD1 P36 R71 10K PM_EXTTS#0
TP_MCH_RSVD2 RSVD1 1%
P37 AV29
m
RSVD2 SM_CK_0 M_CLK_DDR0 13
TP_MCH_RSVD3 R35 BB23 R83 10K PM_EXTTS#1
TP_MCH_RSVD4 N35 BA25 1%
RSVD4 SM_CK_3 M_CLK_DDR3 14 10 +VCC_PEG
TP_MCH_RSVD5 AR12 AV23 U17C
TP_MCH_RSVD6 AR13
TP_MCH_RSVD7 RSVD6
AM12 AW30 M_CLK_DDR#0 13 J40
o
TP_MCH_RSVD8 RSVD7 SM_CK#_0 17 L_BKLT_CTRL L_BKLT_CTRL PEG_COMP R70 24.9
AN13 RSVD8 SM_CK#_1 BA23 M_CLK_DDR#1 13 H39 L_BKLT_EN PEG_COMPI N43
TP_MCH_RSVD9 17 L_BKLT_EN 1%
J12 RSVD9 SM_CK#_3 AW25 M_CLK_DDR#3 14 E39 L_CTRL_CLK PEG_COMPO M43
17 L_CTRL_CLK
RSVD
TP_MCH_RSVD10 AR37 AW23 E40
RSVD10 SM_CK#_4 M_CLK_DDR#4 14 17 L_CTRL_DATA L_CTRL_DATA
TP_MCH_RSVD11 AM36 C37
RSVD11 17 LVDS_DDC_CLK L_DDC_CLK
TP_MCH_RSVD12 TP_PEG_RX#0
c
AL36 RSVD12 SM_CKE_0 BE29 M_CKE0 13,15 17 LVDS_DDC_DATA D35 L_DDC_DATA PEG_RX#_0 J51
TP_MCH_RSVD13 AM37 AY32 K40 L51
RSVD13 SM_CKE_1 M_CKE1 13,15 17 LVDS_VDD_EN L_VDD_EN PEG_RX#_1 SDVOB_INTN 18
D TP_MCH_RSVD14 D20 RSVD14 SM_CKE_3 BD39 M_CKE3 14,15 PEG_RX#_2 N47 TP_PEG_RX#2 D
.
BG37 LVDS_IBG L41 T45 TP_PEG_RX#3
SM_CKE_4 M_CKE4 14,15 LVDS_IBG PEG_RX#_3
TP_LVDS_VBG L43 T50 TP_PEG_RX#4
LVDS_VBG PEG_RX#_4 TP_PEG_RX#5
SM_CS#_0 BG20 M_CS#0 13,15 N41 LVDS_VREFH PEG_RX#_5 U40
BK16 N40 Y44 TP_PEG_RX#6
SM_CS#_1 M_CS#1 13,15 LVDS_VREFL PEG_RX#_6
BG16 D46 Y40 TP_PEG_RX#7
s
SM_CS#_2 M_CS#2 14,15 17 LVDSA_CLK# LVDSA_CLK# PEG_RX#_7
TP_MCH_RSVD20 H10 BE13 C45 AB51 TP_PEG_RX#8
RSVD20 SM_CS#_3 M_CS#3 14,15 17 LVDSA_CLK LVDSA_CLK PEG_RX#_8
TP_MCH_RSVD21 TP_PEG_RX#9
MUXING
B51 RSVD21 17 LVDSB_CLK# D44 LVDSB_CLK# PEG_RX#_9 W49
TP_MCH_RSVD22 BJ20 BH18 E42 AD44 TP_PEG_RX#10
RSVD22 SM_ODT_0 M_ODT0 13,15 17 LVDSB_CLK LVDSB_CLK PEG_RX#_10
LVDS
TP_MCH_RSVD23 BK22 BJ15 AD40 TP_PEG_RX#11
RSVD23 SM_ODT_1 M_ODT1 13,15 PEG_RX#_11
it c
TP_MCH_RSVD24 BF19 BJ14 G51 AG46 TP_PEG_RX#12
RSVD24 SM_ODT_2 M_ODT2 14,15 17 LVDSA_DATA#0 LVDSA_DATA#_0 PEG_RX#_12
TP_MCH_RSVD25 BH20 BE16 E51 AH49 TP_PEG_RX#13
RSVD25 SM_ODT_3 M_ODT3 14,15 17 LVDSA_DATA#1 LVDSA_DATA#_1 PEG_RX#_13
TP_MCH_RSVD26 BK18 F49 AG45 TP_PEG_RX#14
RSVD26 17 LVDSA_DATA#2 LVDSA_DATA#_2 PEG_RX#_14
GRAPHICS
TP_MCH_RSVD27 BJ18 BL15 SM_RCOMP C48 AG41 TP_PEG_RX#15
RSVD27 SM_RCOMP 17 LVDSA_DATA#3 LVDSA_DATA#_3 PEG_RX#_15
TP_MCH_RSVD28 BF23 BK14 SM_RCOMP#
TP_MCH_RSVD29 RSVD28 SM_RCOMP# TP_PEG_RX0
BG23 RSVD29 17 LVDSA_DATA0 G50 LVDSA_DATA_0 PEG_RX_0 J50
TP_MCH_RSVD30 BC23 BK31 SM_RCOMP_VOH E50 L50
RSVD30 SM_RCOMP_VOH 17 LVDSA_DATA1 LVDSA_DATA_1 PEG_RX_1 SDVOB_INTP 18
TP_MCH_RSVD31 BL31 SM_RCOMP_VOL TP_PEG_RX2
DDR
BD24 RSVD31 SM_RCOMP_VOL 17 LVDSA_DATA2 F48 LVDSA_DATA_2 PEG_RX_2 M47
D47 U44 TP_PEG_RX3
17 LVDSA_DATA3 LVDSA_DATA_3 PEG_RX_3
AR49 T49 TP_PEG_RX4
SM_VREF_0 M_VREF_MCH 13,14,47 PEG_RX_4
a
TP_MCH_RSVD34 BH39 AW4 G44 T41 TP_PEG_RX5
RSVD34 SM_VREF_1 17 LVDSB_DATA#0 LVDSB_DATA#_0 PEG_RX_5
TP_MCH_RSVD35 AW20 B47 W45 TP_PEG_RX6
RSVD35 17 LVDSB_DATA#1 LVDSB_DATA#_1 PEG_RX_6
TP_MCH_RSVD36 BK20 B45 W41 TP_PEG_RX7
RSVD36 17 LVDSB_DATA#2 LVDSB_DATA#_2 PEG_RX_7
AB50 TP_PEG_RX8
PEG_RX_8 TP_PEG_RX9
DPLL_REF_CLK B42 DREFCLK 37 PEG_RX_9 Y48
TP_MCH_RSVD39 B44 C42 E44 AC45 TP_PEG_RX10
RSVD39 DPLL_REF_CLK# DREFCLK# 37 17 LVDSB_DATA0 LVDSB_DATA_0 PEG_RX_10
TP_MCH_RSVD40 C44 H48 A47 AC41 TP_PEG_RX11
RSVD40 DPLL_REF_SSCLK DREFSSCLK 37 17 LVDSB_DATA1 LVDSB_DATA_1 PEG_RX_11
TP_MCH_RSVD41 TP_PEG_RX12
PCI-EXPRESS
A35 H47 A45 AH47
m
RSVD41 DPLL_REF_SSCLK# DREFSSCLK# 37 17 LVDSB_DATA2 LVDSB_DATA_2 PEG_RX_12
TP_MCH_RSVD42 B37 AG49 TP_PEG_RX13
TP_MCH_RSVD43 RSVD42 PEG_RX_13 TP_PEG_RX14
B36 K44 AH45
CLK
RSVD43 PEG_CLK CLK_PCIE_3GPLL 37 PEG_RX_14
TP_MCH_RSVD44 B34 K45 AG42 TP_PEG_RX15
RSVD44 PEG_CLK# CLK_PCIE_3GPLL# 37 PEG_RX_15
TP_MCH_RSVD45 C34 RSVD45
C +V3.3S 5,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 R124 150 1% TVA_DAC E27 TVA_DAC PEG_TX#_0 N45 SDVOB_RN 18
C
e
R119 150 1% TVB_DAC G27 U39
DMI_TXN[3:0] 22 TVB_DAC PEG_TX#_1 SDVOB_GN 18
AN47 DMI_TXN0 R111 150 1% TVC_DAC K27 U47
Don’t need to strap CFG[4:3]. DMI_RXN_0 TVC_DAC PEG_TX#_2 SDVOB_BN 18
TV
AJ38 DMI_TXN1 N51
BIOS will read SPD and DMI_RXN_1 PEG_TX#_3 SDVOB_CLKN 18
AN42 DMI_TXN2 F27 R50 TP_PEG_TX#4
determine DDR frequency. DMI_RXN_2 DMI_TXN3 TVA_RTN PEG_TX#_4 TP_PEG_TX#5
DMI_RXN_3 AN46 J27 TVB_RTN PEG_TX#_5 T42
h
L27 Y43 TP_PEG_TX#6
DMI_TXP0 DMI_TXP[3:0] 22 TVC_RTN PEG_TX#_6 TP_PEG_TX#7
3,37 MCH_BSEL0 DMI_RXP_0 AM47 PEG_TX#_7 W46
P27 AJ39 DMI_TXP1 TP_TV_DCONSEL_0 M35 W38 TP_PEG_TX#8
3,37 MCH_BSEL1 CFG_0 DMI_RXP_1 TV_DCONSEL_0 PEG_TX#_8
N27 AN41 DMI_TXP2 TP_TV_DCONSEL_1 P33 AD39 TP_PEG_TX#9
3,37 MCH_BSEL2 CFG_1 DMI_RXP_2 TV_DCONSEL_1 PEG_TX#_9
N24 AN45 DMI_TXP3 AC46 TP_PEG_TX#10
c
TP_MCH_CFG_3 CFG_2 DMI_RXP_3 PEG_TX#_10 TP_PEG_TX#11
C21 CFG_3 DMI_RXN[3:0] 22 PEG_TX#_11 AC49
TP_MCH_CFG_4 C23 AJ46 DMI_RXN0 AC42 TP_PEG_TX#12
R129 4.02K TP_MCH_CFG_5 CFG_4 DMI_TXN_0 PEG_TX#_12
F23 CFG_5 DMI_TXN_1 AJ41 DMI_RXN1 PEG_TX#_13 AH39 TP_PEG_TX#13
NO STUFF 1% TP_MCH_CFG_6 N23 AM40 DMI_RXN2 AE49 TP_PEG_TX#14
TP_MCH_CFG_7 CFG_6 DMI_TXN_2 PEG_TX#_14
AM44 DMI_RXN3 TP_PEG_TX#15
s
G23 CFG_7 DMI_TXN_3 PEG_TX#_15 AH44
TP_MCH_CFG_8
DMI
J20 CFG_8 DMI_RXP[3:0] 22

CFG
MCH_CFG_9 C20 AJ47 DMI_RXP0 H32 M45

CFG_9 DMI_TXP_0 16 CRT_BLUE CRT_BLUE PEG_TX_0 SDVOB_RP 18
TP_MCH_CFG_10 AJ42 DMI_RXP1
-
R24 CFG_10 DMI_TXP_1 G32 CRT_BLUE# PEG_TX_1 T38 SDVOB_GP 18
TP_MCH_CFG_11 L23 AM39 DMI_RXP2 K29 T46
CFG_11 DMI_TXP_2 16 CRT_GREEN CRT_GREEN PEG_TX_2 SDVOB_BP 18
MCH_CFG_12 J23 AM43 DMI_RXP3 J29 N50
CFG_12 DMI_TXP_3 CRT_GREEN# PEG_TX_3 SDVOB_CLKP 18
MCH_CFG_13 E23 F29 R51 TP_PEG_TX4
CFG_13 16 CRT_RED CRT_RED PEG_TX_4
VGA
TP_MCH_CFG_14 E20 R89 150 1% E29 U43 TP_PEG_TX5
TP_MCH_CFG_15 CFG_14 R94 150 1% CRT_RED# PEG_TX_5 TP_PEG_TX6
K23 W42
p
R95 TP_MCH_CFG_16 CFG_15 R91 150 1% PEG_TX_6 TP_PEG_TX7
M20 CFG_16 PEG_TX_7 Y47
4.02K
GRAPHICS VID
TP_MCH_CFG_17 M24 K33 Y39 TP_PEG_TX8

1% CFG_17 16 CRT_DDC_CLK CRT_DDC_CLK PEG_TX_8
NO_STUFF TP_MCH_CFG_18 L32 G35 AC38 TP_PEG_TX9
CFG_18 16 CRT_DDC_DATA CRT_DDC_DATA PEG_TX_9
MCH_CFG_19 N33 HSYNC F33 AD47 TP_PEG_TX10
TP_MCH_CFG_20 CFG_19 R88 30.1 1% CRTIREF C32 CRT_HSYNC PEG_TX_10 TP_PEG_TX11
L35 AC50
o
CFG_20 16 CRT_HSYNC CRT_TVO_IREF PEG_TX_11
R87 30.1 1% VSYNC E33 AD43 TP_PEG_TX12
16 CRT_VSYNC CRT_VSYNC PEG_TX_12
AG39 TP_PEG_TX13
PEG_TX_13
t
E35 AE50 TP_PEG_TX14
B GFX_VID_0 DFGT_VID_0 49 PEG_TX_14 B
2
G41 A39 AH43 TP_PEG_TX15
23 PM_BMBUSY# PM_BM_BUSY# GFX_VID_1 DFGT_VID_1 49 PEG_TX_15
L39 C38 +V1.8_GMCH 9,10,45 R588
3,21,52 H_DPRSTP# PM_DPRSTP# GFX_VID_2 DFGT_VID_2 49
L36 B39 1.30K
13,15 PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3 DFGT_VID_3 49
PM
J36 E36 0.5% CRESTLINE_1p0_OAKMONT

14,15 PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN DFGT_VR_EN 49
10,37,48,56,57 +V1.25M R99
p
23,52 DELAY_VR_PWRGOOD AW49
1
R10527 100 RST_IN#_MCH PWROK 1K
19,22,25,26,40,58 PLT_RST# AV20 RSTIN# 0.10%
N20 THERMTRIP#
3,21 PM_THRMTRIP#
23,52 PM_DPRSLPVR G36 DPRSLPVR R72 SM_RCOMP_VOH
AM49 1K
la
CL_CLK CL_CLK0 23 1%
AK50 C128 C514
CL_DATA CL_DATA0 23
TP_MCH_NC1 BJ51 AT43 R93 0.01uF 2.2uF
ME
TP_MCH_NC2 NC_1 CL_PWROK MPWROK 23,47 3.01k 10% 10%

BK51 NC_2 CL_RST# AN49 CL_RST#0 23
TP_MCH_NC3 BK50 AM50 MCH_CLVREF 402
NC_3 CL_VREF
.
TP_MCH_NC4 BL50
TP_MCH_NC5 NC_4 C71 LVDS_IBG
BL49 NC_5
TP_MCH_NC6 BL3 0.1uF R66
TP_MCH_NC7 NC_6 10% 392 SM_RCOMP_VOL
BL2 NC_7
NC
TP_MCH_NC8 BK1 1% R77

TP_MCH_NC9 NC_8 2.37K
BJ1 NC_9 SDVO_CTRL_CLK H35 SDVO_CTRLCLK 18 1%
MISC
TP_MCH_NC10 E1 K36 R90 C117 C499

SDVO_CTRLDATA 18
w
TP_MCH_NC11 NC_10 SDVO_CTRL_DATA 1K 0.01uF 2.2uF
A5 NC_11 CLK_REQ# G39 CLK_MCH_OE# 37 0.10%
TP_MCH_NC12 C51 G40 MCH_ICH_SYNC# 23 10% 10%
TP_MCH_NC13 NC_12 ICH_SYNC# 402
B50 NC_13
TP_MCH_NC14 A50
TP_MCH_NC15 NC_14 MCH_TEST_R
A49 NC_15 TEST_1 A37
TP_MCH_NC16 BK2 R32
NC_16 TEST_2
w
CRESTLINE_1p0_OAKMONT
R81
10K +V1.8_GMCH 9,10,45
A MCH CONFIG A
MCH_CFG_12
STRAPS Oakmont Form Factor Reference Design Intel Confidential
w
MCH_CFG_13 R152
20
PCI Express Graphics Lane
Low = Reverse Lane 1% Title
MCH_CFG_9 High = Normal operation (default) XOR / ALLZ / Clock Un-gating
MCH_CFG_12 MCH_CFG_13 Configuration
CRESTLINE (2 OF 6)
SM_RCOMP
DMI Lane Reversal 0 0 Reserved R121 R113 SM_RCOMP#
Low = Normal (default) 0 1 XOR Mode Enabled 4.02K 4.02K
MCH_CFG_19 High = Lanes Reversed 1 0 All-Z Mode Enabled 1%
NO_STUFF
1%
NO_STUFF
1 1 Clock Gating Enabled (default) R153
20 A
1%
Date: Sheet 7 of 64
5 4 3 2 1
5 4 3 2 1
o m
c
13 M_A_DQ[63:0] 14 M_B_DQ[63:0]
U17D U17E
D M_A_DQ0 AR43 SA_DQ_0 SA_BS_0 BB19 M_A_BS0 13,15
M_B_DQ0 AP49 SB_DQ_0 SB_BS_0 AY17 M_B_BS0 14,15 D
.
M_A_DQ1 AW44 BK19 M_B_DQ1 AR51 BG18
SA_DQ_1 SA_BS_1 M_A_BS1 13,15 SB_DQ_1 SB_BS_1 M_B_BS1 14,15
M_A_DQ2 BA45 BF29 M_B_DQ2 AW50 BG36
SA_DQ_2 SA_BS_2 M_A_BS2 13,15 SB_DQ_2 SB_BS_2 M_B_BS2 14,15
M_A_DQ3 AY46 M_B_DQ3 AW51
SA_DQ_3 M_A_CAS# 13,15 SB_DQ_3 M_B_CAS# 14,15
M_A_DQ4 AR41 BL17 M_B_DQ4 AN51 BE17
M_A_DQ5 SA_DQ_4 SA_CAS# M_B_DQ5 SB_DQ_4 SB_CAS#
AR45 AN50
s
SA_DQ_5 M_A_DM[7:0] 13 SB_DQ_5 M_B_DM[7:0] 14
M_A_DQ6 AT42 AT45 M_A_DM0 M_B_DQ6 AV50 AR50 M_B_DM0
M_A_DQ7 SA_DQ_6 SA_DM_0 M_A_DM1 M_B_DQ7 SB_DQ_6 SB_DM_0 M_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
M_A_DQ8 BB45 BD42 M_A_DM2 M_B_DQ8 BA50 BK45 M_B_DM2
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
it c
M_A_DQ10 BG47 AW13 M_A_DM4 M_B_DQ10 BA49 BH12 M_B_DM4
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
M_A_DQ12 BB47 AY5 M_A_DM6 M_B_DQ12 BA51 BF3 M_B_DM6
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
M_A_DQ14 BH49 M_B_DQ14 BF50
SA_DQ_14 M_A_DQS[7:0] 13 SB_DQ_14 M_B_DQS[7:0] 14
A
M_A_DQ15 M_A_DQS0 M_B_DQ15 M_B_DQS0
B
BE45 SA_DQ_15 SA_DQS_0 AT46 BF49 SB_DQ_15 SB_DQS_0 AT50
M_A_DQ16 AW43 BE48 M_A_DQS1 M_B_DQ16 BJ50 BD50 M_B_DQS1
M_A_DQ17 SA_DQ_16 SA_DQS_1 M_A_DQS2 M_B_DQ17 SB_DQ_16 SB_DQS_1 M_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
M_A_DQ18 BG42 BC37 M_A_DQS3 M_B_DQ18 BJ43 BK39 M_B_DQS3
BE40 BB16 BL43 BJ12
MEMORY
SA_DQ_19 SA_DQS_4 SB_DQ_19 SB_DQS_4
MEMORY
M_A_DQ20 BF44 BH6 M_A_DQS5 M_B_DQ20 BK47 BL7 M_B_DQS5
BH45 SA_DQ_21 SA_DQS_6 BB2 BK49 SB_DQ_21 SB_DQS_6 BE2
M_A_DQ22 BG40 AP3 M_A_DQS7 M_B_DQ22 BK43 AV2 M_B_DQS7
SA_DQ_22 SA_DQS_7 M_A_DQS#[7:0] 13 SB_DQ_22 SB_DQS_7 M_B_DQS#[7:0] 14
M_A_DQ23 BF40 AT47 M_A_DQS#0 M_B_DQ23 BK42 AU50 M_B_DQS#0
M_A_DQ24 SA_DQ_23 SA_DQS#_0 M_A_DQS#1 M_B_DQ24 SB_DQ_23 SB_DQS#_0 M_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
M_A_DQ25 AW40 BC41 M_A_DQS#2 M_B_DQ25 BL41 BL45 M_B_DQS#2
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
M_A_DQ27 AW36 BA16 M_A_DQS#4 M_B_DQ27 BJ36 BK12 M_B_DQS#4
m
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
M_A_DQ29 AY41 BC1 M_A_DQS#6 M_B_DQ29 BJ40 BF2 M_B_DQS#6
AV38 SA_DQ_30 SA_DQS#_7 AP2 BL35 SB_DQ_30 SB_DQS#_7 AV3
M_A_DQ31 AT38 M_B_DQ31 BK37
SA_DQ_31 M_A_A[14:0] 13,15 SB_DQ_31 M_B_A[14:0] 14,15
C M_A_DQ32 M_A_A0 M_B_DQ32 M_B_A0 C
SYSTEM
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM
M_A_DQ33 AT13 BD20 M_A_A1 M_B_DQ33 BE11 BG28 M_B_A1
M_A_DQ34 SA_DQ_33 SA_MA_1 M_A_A2 M_B_DQ34 SB_DQ_33 SB_MA_1 M_B_A2
AW11 SA_DQ_34 SA_MA_2 BK27 BK11 SB_DQ_34 SB_MA_2 BG25
M_A_DQ35 AV11 BH28 M_A_A3 M_B_DQ35 BC11 AW17 M_B_A3
AU15 SA_DQ_36 SA_MA_4 BL24 BC13 SB_DQ_36 SB_MA_4 BF25
M_A_DQ37 AT11 BK28 M_A_A5 M_B_DQ37 BE12 BE25 M_B_A5
SA_DQ_37 SA_MA_5 SB_DQ_37 SB_MA_5
h
M_A_DQ38 BA13 BJ27 M_A_A6 M_B_DQ38 BC12 BA29 M_B_A6
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
M_A_DQ40 BE10 BL28 M_A_A8 M_B_DQ40 BJ10 AY28 M_B_A8
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
M_A_DQ42 BD8 BC19 M_A_A10 M_B_DQ42 BK5 BG17 M_B_A10
c
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
M_A_DQ44 BG10 BG30 M_A_A12 M_B_DQ44 BK9 BA39 M_B_A12
DDR
M_A_DQ45 AW9 BJ16 M_A_A13 M_B_DQ45 BK10 BG13 M_B_A13

DDR
M_A_DQ46 BD7 BJ29 M_A_A14 M_B_DQ46 BJ8 BE24 M_B_A14
M_A_DQ47 SA_DQ_46 SA_MA_14 M_B_DQ47 SB_DQ_46 SB_MA_14
s
BB9 SA_DQ_47 BJ6 SB_DQ_47
M_A_DQ48 BB5 BE18 M_B_DQ48 BF4 AV16
SA_DQ_48 SA_RAS# M_A_RAS# 13,15 SB_DQ_48 SB_RAS# M_B_RAS# 14,15
M_A_DQ49 AY7 AY20 TP_SA_RCVEN# M_B_DQ49 BH5 AY18 TP_SB_RCVEN#
M_A_DQ50 SA_DQ_49 SA_RCVEN# M_B_DQ50 SB_DQ_49 SB_RCVEN#
-
AT5 SA_DQ_50 BG1 SB_DQ_50
M_A_DQ51 AT7 BA19 M_B_DQ51 BC2 BC17
SA_DQ_51 SA_WE# M_A_WE# 13,15 SB_DQ_51 SB_WE# M_B_WE# 14,15
M_A_DQ52 AY6 M_B_DQ52 BK3
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52
BB7 SA_DQ_53 BE4 SB_DQ_53
M_A_DQ54 AR5 M_B_DQ54 BD3
AR8 BJ2
p
AR9 SA_DQ_56 BA3 SB_DQ_56
M_A_DQ57 AN3 M_B_DQ57 BB3
AM8 SA_DQ_58 AR1 SB_DQ_58
M_A_DQ59 AN10 M_B_DQ59 AT3
AT9 AY2
o
AN9 SA_DQ_61 AY3 SB_DQ_61
M_A_DQ62 AM9 M_B_DQ62 AU2
SA_DQ_62 SB_DQ_62
t
M_A_DQ63 AN11 M_B_DQ63 AT2
B SA_DQ_63 SB_DQ_63 B
CRESTLINE_1p0_OAKMONT CRESTLINE_1p0_OAKMONT
la p
w .
w
A A
w
Title
CRESTLINE (3 OF 6)

A
Date: Sheet 8 of 64
5 4 3 2 1
5 4 3 2 1
+V1.05S 3,4,6,10,20,21,24,45,48,54,56 +V3.3S 5,7,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
m
3,4,6,10,20,21,24,45,48,54,56 +V1.05S
3,4,6,10,20,21,24,45,48,54,56 +V1.05S
Q16
Customer U17G 49,56 +VCC_GFXCORE R64 1 2 10 VCCGFOLLOW2 3 1
o
Recommended bulk
Cap 1 + C60 AT35 VCC_1
BAT54
220uF AT34 T17
10% VCC_2 VCC_AXG_NCTF_1
AH28 T18
2
VCC_3 VCC_AXG_NCTF_2
c
AC32 VCC_5 VCC_AXG_NCTF_3 T19
AC31 T21 U17F
VCC_4 VCC_AXG_NCTF_4
D AK32 VCC_6 VCC_AXG_NCTF_5 T22 D
.
AJ31 VCC_7 VCC_AXG_NCTF_6 T23 AB33 VCC_NCTF_1
AJ28 T25 C402 C482 C2030 C2031 C474 AB36
VCC_8 VCC_AXG_NCTF_7 270uF 0.1uF 22uF 0.22uF 0.22uF VCC_NCTF_2
AH32 U15 AB37
VCC CORE
VCC_9 VCC_AXG_NCTF_8 10% VCC_NCTF_3
AH31 VCC_10 VCC_AXG_NCTF_9 U16 AC33 VCC_NCTF_4 VSS_NCTF_1 T27
AH29 U17 AC35 T37
s
VCC_11 VCC_AXG_NCTF_10 VCC_NCTF_5 VSS_NCTF_2
AF32 VCC_12 VCC_AXG_NCTF_11 U19 AC36 VCC_NCTF_6 VSS_NCTF_3 U24
U20 EDGE CAVITY AD35 U28
VCC_AXG_NCTF_12 VCC_NCTF_7 VSS_NCTF_4
VCC_AXG_NCTF_13 U21 AD36 VCC_NCTF_8 VSS_NCTF_5 V31
VCC_AXG_NCTF_14 U23 AF33 VCC_NCTF_9 VSS_NCTF_6 V35
it c
R30 VCC_13 VCC_AXG_NCTF_15 U26 AF36 VCC_NCTF_10 VSS_NCTF_7 AA19
V16 AH33 AB17
VSS NCTF
VCC_AXG_NCTF_17 V17 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35
VCC_AXG_NCTF_18 V19 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19
VCC_AXG_NCTF_19 V20 AH37 VCC_NCTF_14 VSS_NCTF_11 AD37
VCC_AXG_NCTF_20 V21 AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17
VCC_AXG_NCTF_21 V23 AJ35 VCC_NCTF_16 VSS_NCTF_13 AF35
V24 +VCC_GFXCORE 49,56 AK33 AK17
Y15 AK35 AM17
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24 Y16
These caps are cavity capacitors AK36
VCC_NCTF_18
VCC_NCTF_19
VSS_NCTF_15
VSS_NCTF_16 AM24
a
+V1.8_GMCH 7,10,45 Y17 AK37 AP26
AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19 AD33 VCC_NCTF_21 VSS_NCTF_18 AP28
AU33 Y20 C535 C523 AJ36 AR15
VCC NCTF
VCC_SM_2 VCC_AXG_NCTF_27 VCC_NCTF_22 VSS_NCTF_19
1
AU35 Y21 + C204 + C524 C517 C556 C592 0.1uF 0.1uF AM35 AR19
VCC_SM_3 VCC_AXG_NCTF_28 330uF C195 0.47uF 1uF 10uF 22uF 10% 10% VCC_NCTF_23 VSS_NCTF_20
AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23 3 3 AL33 VCC_NCTF_24 VSS_NCTF_21 AR28
AW33 Y24 330uF AL35
2
VCC_SM_5 VCC_AXG_NCTF_30 VCC_NCTF_25
AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26 AA33 VCC_NCTF_26
AY35 Y28 AA35
m
BA32 VCC_SM_8 VCC_AXG_NCTF_33 Y29 AA36 VCC_NCTF_28
BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16 AP35 VCC_NCTF_29
BA35 VCC_SM_10 VCC_AXG_NCTF_35 AA17 AP36 VCC_NCTF_30
BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16 AR35 VCC_NCTF_31
C BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19 AR36 VCC_NCTF_32
C
e
BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16 Y32 VCC_NCTF_33
BC35 AC17 Y33
POWER
VCC SM

BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19 Y35 VCC_NCTF_35
BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15 Y36 VCC_NCTF_36
BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16 Y37 VCC_NCTF_37 VSS_SCB1 A3
h
BE33 AD17 T30 B2
VSS SCB
VCC GFX NCTF
VCC_SM_18 VCC_AXG_NCTF_43 VCC_NCTF_38 VSS_SCB2

BE35 VCC_SM_19 VCC_AXG_NCTF_44 AF16 T34 VCC_NCTF_39 VSS_SCB3 C1
BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19 T35 VCC_NCTF_40 VSS_SCB4 BL1
BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15 U29 VCC_NCTF_41 VSS_SCB5 BL51
BG32 AH16 U31 A51
c
VCC_SM_22 VCC_AXG_NCTF_47 VCC_NCTF_42 VSS_SCB6
BG33 VCC_SM_23 VCC_AXG_NCTF_48 AH17 U32 VCC_NCTF_43
BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19 U33 VCC_NCTF_44
BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16 U35 VCC_NCTF_45
BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17 U36 VCC_NCTF_46
s
BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19 V32 VCC_NCTF_47
BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16 V33 VCC_NCTF_48
BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19 V36 VCC_NCTF_49 48,56 +V1.05M
-
BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16 V37 VCC_NCTF_50
BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17
BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19 VCC_AXM_1 AT33
BK34 AL20 AT31
VCC AXM
VCC_SM_33 VCC_AXG_NCTF_58 VCC_AXM_2
BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21 +V1.05M48,56 VCC_AXM_3 AK29
BL33 AL23 AK24
p
VCC_SM_35 VCC_AXG_NCTF_60 VCC_AXM_4
AU30 VCC_SM_36 VCC_AXG_NCTF_61 AM15 VCC_AXM_5 AK23
VCC_AXG_NCTF_62 AM16 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26
VCC_AXG_NCTF_63 AM19 AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23
+VCC_GFXCORE 49,56 AM20 C472 C500 C480 C509 AL28
VCC_AXG_NCTF_64 C495 C496 0.1uF 0.1uF 0.1uF VCC_AXM_NCTF_3
AM21 22uF AM26
VCC AXM NCTF

VCC_AXG_NCTF_65 0.22uF 0.22uF 10% 10% 10% VCC_AXM_NCTF_4
R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23 AM28 VCC_AXM_NCTF_5
T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15 AM29 VCC_AXM_NCTF_6
t
W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16 AM31 VCC_AXM_NCTF_7
B W14 AP17 AM32 B
VCC_AXG_4 VCC_AXG_NCTF_69 Edge Cavity VCC_AXM_NCTF_8
Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19 AM33 VCC_AXM_NCTF_9
AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20 AP29 VCC_AXM_NCTF_10
p
AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20 AL29 VCC_AXM_NCTF_14
AC20 AR24 AR31
la
VCC GFX
VCC_AXG_13 VCC_AXG_NCTF_78 VCC_AXM_NCTF_17

AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26 AR32 VCC_AXM_NCTF_18
AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26 AR33 VCC_AXM_NCTF_19
AC24 V28 +V1.8 10,13,14,18,45,47,56
VCC_AXG_16 VCC_AXG_NCTF_81 +V1.8_GMCH 7,10,45
AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
.
AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
AC29 R85 0.002
VCC_AXG_19 1% CRESTLINE_1p0_OAKMONT
AD20 VCC_AXG_20
AD23 VCC_AXG_21
AD24 AW45 VCC_SM_LF1_C
VCC_AXG_22 VCC_SM_LF1 VCC_SM_LF2_C + C437 C106 C101 C483
AD28 BC39
VCC SM LF
VCC_AXG_23 VCC_SM_LF2 VCC_SM_LF3_C 330uF 22uF 22uF 0.1uF

AF21 BE39
w
VCC_AXG_24 VCC_SM_LF3 VCC_SM_LF4_C 10%
AF26 VCC_AXG_25 VCC_SM_LF4 BD17
AA31 BD4 VCC_SM_LF5_C
VCC_AXG_26 VCC_SM_LF5 VCC_SM_LF6_C
AH20 VCC_AXG_27 VCC_SM_LF6 AW8
AH21 AT6 VCC_SM_LF7_C
VCC_AXG_28 VCC_SM_LF7
AH23 VCC_AXG_29
AH24 VCC_AXG_30
AH26 C541 C538 C554 C536 C470 C2032 C454
w
VCC_AXG_31 0.1uF 0.1uF 0.22uF 0.22uF 0.47uF 1uF 1uF
AD31 VCC_AXG_32
AJ20 10% 10%
VCC_AXG_33
AN14 VCC_AXG_34
A A
w
Title
CRESTLINE_1p0_OAKMONT CRESTLINE (4 OF 6)

A
Date: Sheet 9 of 64
5 4 3 2 1
5 4 3 2 1
+V1.25S 24,56,57 5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
NOTE
+V1.25S_DPLLA Place caps on this page close
10uH +V3.3S 5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 to GMCH +V1.05S 3,4,6,9,20,21,24,45,48,54,56
m
L3 1 2 C497
10% 0.1uF
1
C424 C91 10% U17H
Customer 470uF 0.1uF Keep C112 near
1
+ C208 Recommended bulk 10% A33 and B33 J32 U13
o
220uF Cap R82 VCCSYNC VTT_1 C568 C177 C187
10% VTT_2 U12
FB9 V3.3S_CRTDAC_FB 1 3 V3.3S_CRTDAC A33 U11 C578 4.7uF C176 2.2uF 270uF
2
180ohm@100MHz 22nF C110 VCCA_CRT_DAC_1 VTT_3 4.7uF 10% 0.47uF 10%

B33 VCCA_CRT_DAC_2 VTT_4 U9
+V1.25S_DPLLB 0.1uF U8 10%
CRT
2
10uH 10% +V3.3S_BGDAC_VCCA_TV VTT_5
c
VTT_6 U7
L2 1 2 A30 U5
VCCA_DAC_BG VTT_7
D VTT_8 U3 D
.
10% C65 C86 Keep C516 and FB11 B32 U2
470uF 0.1uF 5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S close to source VSSA_DAC_BG VTT_9
VTT_10 U1
10% FB11 R102 +V1.25S_DPLLA T13
VTT
2
V3.3S_CRTDAC__BG_FB VTT_11
1 3 +V1.25S_DPLLB B49 VCCA_DPLLA VTT_12 T11
22nF T10
s
180ohm@100MHz C516 C126 +V1.25M_HPLL VTT_13
H49 T9
2
+V1.25M 7,37,48,56,57 10uF 0.1uF VCCA_DPLLB VTT_14
T7
PLL
+V1.25M_HPLL 10% VTT_15
AL2 VCCA_HPLL VTT_16 T6
+V1.25M_MPLL T5
VTT_17
it c
FB12 +V1.8_TXLVDS AM2 T3 +V1.25M 7,37,48,56,57
VCCA_MPLL VTT_18
1 2 VTT_19 T2
R3
A LVDS
120ohm@100MHz VTT_20 R594 Placeholder
C174 A41 VCCA_LVDS VTT_21 R2
C184 Place near A41 C96 R1 0 for 5.6nH
22uF 0.1uF 1000pF VTT_22 inductor
10% B41 VSSA_LVDS
10% 24,56,57 +V1.25S
+V1.25M_MPLL AT23 VCC_AXD[1_6]
FB13 VCC_AXD_1 C519 C525
VCC_AXD_2 AU28
1
1 2 K50 AU24 1.0uF 22uF R134
AXD
VCCA_PEG_BG VCC_AXD_3
a
C87 AT29 NO_STUFF Placeholder 0
120ohm@100MHz R183 5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 0.1uF VCC_AXD_4 402 for 0.1uH
K49 AT25
A PEG
0.5 C175 10% +V1.25S_PEGPLL VSSA_PEG_BG VCC_AXD_5 inductor
1% VCC_AXD_6 AT30
0.1uF
2
+V1.25M_MPLL_R 10% U51 AR29
C186 VCCA_PEG_PLL VCC_AXD_NCTF VCC_AXF[1_3]
22uF C85 +V1.25M_A_SM 24,56,57 +V1.25S
0.1uF AW18 B23 C130 C134
m
10% VCCA_SM_1 VCC_AXF_1 1.0uF 10uF
AV19 B21
POWER
AXF
VCCA_SM_2 VCC_AXF_2
AU19 VCCA_SM_3 VCC_AXF_3 A21
+V1.8_SM_CK AU18 402 NO_STUFF
7,9,45 +V1.8_GMCH VCCA_SM_4 C83
AU17 VCCA_SM_5 VCC_DMI AJ50
C +V1.8_SM_CK 0.1uF C
A SM
e
1uH AT22 10%
L5 7,37,48,56,57 +V1.25M VCCA_SM_7
1 2 AT21 BK24
SM CK
VCCA_SM_8 VCC_SM_CK_1
AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C133 Placeholder AT18 BJ24 C132
R128 1.00 +V1.8_SMCK_RC 22uF R589 for inductor VCCA_SM_10 VCC_SM_CK_3 0.1uF
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
h
1% 0 AR17 10%
C137 VCCA_SM_NCTF_1
AR16 VCCA_SM_NCTF_2
10uF +V1.8_TXLVDS
A43
A CK
TVO Supplies must be powered even if TV is VCCA_SM_CK[1_2] VCC_TX_LVDS
BC29
c
not used. VCCA_SM_CK_1 +V3.3S_HV C99 Place near A43
BB29 VCCA_SM_CK_2
Seperate LDO must be used if TV is C512 C498 C507 C508 +V3.3S_BGDAC_VCCA_TV C40 1000pF
enabled.(This design has TV disabled) 180pF 180pF 0.1uF 22uF VCC_HV_1 10%
C25 B40
HV
5% 5% 10% VCCA_TVA_DAC_1 VCC_HV_2 7 +VCC_PEG
B25 VCCA_TVA_DAC_2
R602 to be NO_STUFF NO_STUFF
-s
C27 VCCA_TVB_DAC_1
used if B27 AD51
TV
+V1.25M_A_SM 3.9nH needs VCCA_TVB_DAC_2 VCC_PEG_1
B28 W50
PEG
to be 4,18,24..26,48,56 +V1.5S VCCA_TVC_DAC_1 VCC_PEG_2
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
stuffed +V1.25M 7,37,48,56,57
VCC_PEG_4 V49
R86 V50
D TV/CRT
R601 0 VCCD_CRTDAC VCC_PEG_5
1 3 M32 VCCD_CRT
22nF L29 7 +VCC_PEG
VCCD_TVDAC
1
C526 C142 C537 + C527 C112 AH50
DMI
2
1.0uF 4.7uF 22uF C548 22uF 0.1uF VCCDQ_CRT VCC_RXR_DMI_1

N28 VCCD_QDAC VCC_RXR_DMI_2 AH51
10% 100uF NO_STUFF 10% +V1.25M 7,37,48,56,57
2
402 AN2
+V1.25S_PEGPLL VCCD_HPLL MCH_VTTLF1
A7
VTTLF
VTTLF1 MCH_VTTLF2
U48 F2
o
C170 VCCD_PEG_PLL VTTLF2 MCH_VTTLF3
PLACE ON VTTLF3 AH1
0.1uF +V1.8 9,13,14,18,45,47,56 J41
LVDS
THE EDGE VCCD_LVDS_1
t
10% C88 H42
B +V1.5S 4,18,24..26,48,56 0.1uF C468 VCCD_LVDS_2 C178 C555 C152 B
R92 10% 1.0uF 0.47uF 0.47uF 0.47uF
FB10 +V1.5S_VCCDQ_CRT_FB 1 3
22nF 402 CRESTLINE_1p0_OAKMONT
24,56,57 +V1.25S 180ohm@100MHz C119
p
2
+V1.25S_PEGPLL 0.1uF
10%
FB29 220ohm_at_100MHz +VCC_PEG 7
91nH +V1.05S 3,4,6,9,20,21,24,45,48,54,56
L18
la
1
R69 1.00 +V1.25S_PEGPLL_RC C401 + C64
1% C67 10uF 220uF
10uF 10%
2
.
3,4,6,9,20,21,24,45,48,54,56 +V1.05S
1
Q19 9,13,14,18,45,47,56 +V1.8
BAT54 +V1.8_TXLVDS
w
1uH
V1_05S_SD L19 1 2
3
1
1
+ C94
R78 220uF
10 10%
2
5,7,9,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
w
+V3.3S_HV
2
R80 0
A C100 Oakmont Form Factor Reference Design Intel Confidential A
0.1uF
Title
w
10%
CRESTLINE (5 OF 6)

A
Date: Sheet 10 of 64
5 4 3 2 1
5 4 3 2 1
U17I
m
A13 VSS_1 VSS_100 AW24
A15 AW29 U17J
VSS_2 VSS_101
A17 VSS_3 VSS_102 AW32 C46 VSS_199 VSS_287 W11
A24 VSS_4 VSS_103 AW5 C50 VSS_200 VSS_288 W39
o
AA21 VSS_5 VSS_104 AW7 C7 VSS_201 VSS_289 W43
AA24 VSS_6 VSS_105 AY10 D13 VSS_202 VSS_290 W47
AA29 VSS_7 VSS_106 AY24 D24 VSS_203 VSS_291 W5
AB20 VSS_8 VSS_107 AY37 D3 VSS_204 VSS_292 W7
c
AB23 VSS_9 VSS_108 AY42 D32 VSS_205 VSS_293 Y13
D AB28 AY45 D45 Y41 D
.
VSS_11 VSS_110 VSS_207 VSS_295
AC10 VSS_13 VSS_112 AY50 E10 VSS_209 VSS_297 Y49
AC13 VSS_14 VSS_113 B10 E16 VSS_210 VSS_298 Y5
s
AC43 VSS_17 VSS_116 B29 E32 VSS_213 VSS_301 P29
AC47 VSS_18 VSS_117 B30 E47 VSS_214 VSS_302 T29
AD1 VSS_19 VSS_118 B35 F19 VSS_215 VSS_303 T31
it c
AD21 VSS_20 VSS_119 B38 F36 VSS_216 VSS_304 T33
AD26 VSS_21 VSS_120 B43 F4 VSS_217 VSS_305 R28
AD29 VSS_22 VSS_121 B46 F40 VSS_218
AD3 VSS_23 VSS_122 B5 F50 VSS_219
AD41 VSS_24 VSS_123 B8 G1 VSS_220
AD45 VSS_25 VSS_124 BA1 G13 VSS_221 VSS_306 AA32
AD49 VSS_26 VSS_125 BA17 G16 VSS_222 VSS_307 AB32
AD5 VSS_27 VSS_126 BA18 G19 VSS_223 VSS_308 AD32
AD50 VSS_28 VSS_127 BA2 G24 VSS_224 VSS_309 AF28
a
AD8 VSS_29 VSS_128 BA24 G28 VSS_225 VSS_310 AF29
AE10 VSS_30 VSS_129 BB12 G29 VSS_226 VSS_311 AT27
AE14 VSS_31 VSS_130 BB25 G33 VSS_227 VSS_312 AV25
AE6 VSS_32 VSS_131 BB40 G42 VSS_228 VSS_313 H50
AF20 BB44 G45
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G48
G8
VSS_229
VSS_230
VSS_231
m
AF31 VSS_36 VSS_135 BC16 H24 VSS_232
AG2 VSS_37 VSS_136 BC24 H28 VSS_233
AG38 VSS_38 VSS_137 BC25 H4 VSS_234
AG43 VSS_39 VSS_138 BC36 H45 VSS_235
C AG47 BC40 J11 C
VSS_40 VSS_139 VSS_236
e
AG50 VSS_41 VSS_140 BC51 J16 VSS_237
AH3 VSS_42 VSS_141 BD13 J2 VSS_238
AH41 VSS_44 VSS_143 BD28 J28 VSS_240
AH7 BD45 J33
VSS
h
AJ11 VSS_47 VSS_146 BD5 J39 VSS_243
AJ13 VSS_48 VSS_147 BE1
AJ21 VSS_49 VSS_148 BE19 K12 VSS_245
c
AJ24 VSS_50 VSS_149 BE23 K47 VSS_246
AJ29 VSS_51 VSS_150 BE30 K8 VSS_247
AJ32 VSS_52 VSS_151 BE42 L1 VSS_248
AJ43 VSS_53 VSS_152 BE51 L17 VSS_249
s
AJ45 VSS_54 VSS_153 BE8 L20 VSS_250
AJ49 VSS_55 VSS_154 BF12 L24 VSS_251
AK20 VSS_56 VSS_155 BF16 L28 VSS_252
-
AK21 VSS_57 VSS_156 BF36 L3 VSS_253
AK26 VSS_58 VSS_157 BG19 L33 VSS_254
AK28 VSS_59 VSS_158 BG2 L49 VSS_255
AK31 VSS_60 VSS_159 BG24 M28 VSS_256
AK51 BG29 M42
p
AL1 VSS_62 VSS_161 BG39 M46 VSS_258
AM11 VSS_63 VSS_162 BG48 M49 VSS_259
AM13 VSS_64 VSS_163 BG5 M5 VSS_260
AM3 VSS_65 VSS_164 BG51 M50 VSS_261
o
AM4 VSS_66 VSS_165 BH17 M9 VSS_262
AM41 VSS_67 VSS_166 BH30 N11 VSS_263
AM45 BH44 N14
t
B AN1 VSS_69 VSS_168 BH46 N17 VSS_265
B
AN38 VSS_70 VSS_169 BH8 N29 VSS_266
AN39 VSS_71 VSS_170 BJ11 N32 VSS_267
AN43 VSS_72 VSS_171 BJ13 N36 VSS_268
AN5 BJ38 N39
p
AN7 VSS_74 VSS_173 BJ4 N44 VSS_270
AP4 VSS_75 VSS_174 BJ42 N49 VSS_271
AP48 VSS_76 VSS_175 BJ46 N7 VSS_272
AP50 VSS_77 VSS_176 BK15 P19 VSS_273
la
AR11 VSS_78 VSS_177 BK17 P2 VSS_274
AR44 VSS_81 VSS_180 BK36 P50 VSS_277
AR47 BK40 R49
.
AR7 VSS_83 VSS_182 BK44 T39 VSS_279
AT10 VSS_84 VSS_183 BK6 T43 VSS_280
AT14 VSS_85 VSS_184 BK8 T47 VSS_281
AT41 VSS_86 VSS_185 BL11 U41 VSS_282
AT49 VSS_87 VSS_186 BL13 U45 VSS_283
AU1 BL19 U50
w
AU23 VSS_89 VSS_188 BL22 V2 VSS_285
AU29 VSS_90 VSS_189 BL37 V3 VSS_286
AU3 VSS_91 VSS_190 BL47
AU36 VSS_92 VSS_191 C12
AU49 C16 CRESTLINE_1p0_OAKMONT
VSS_93 VSS_192
AU51 C19
w
VSS_94 VSS_193
AV39 VSS_95 VSS_194 C28
AV48 VSS_96 VSS_195 C29
AW1 VSS_97 VSS_196 C33
A AW12 VSS_98 VSS_197 C36 A
AW16 VSS_99 VSS_198 C41
w
CRESTLINE_1p0_OAKMONT Title
CRESTLINE (6 OF 6)

A
5 4 3 2 1
5 4 3 2 1
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D D
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Title
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A
5 4 3 2 1
5 4 3 2 1
EXTTS#0 & EXTTS#1 connection options table
m
Dimms EXTTS# options Stuffing Options
Stuff: R64
9,10,14,18,45,47,56 +V1.8 To EXTTS#0 (Default) No-stuff: R59
o
Stuff: R59, R63
Dimm-0 To EXTTS#1 No-stuff: R64
R459
10K
1%
To EXTTS#0 & EXTTS#1 Stuff: R64, R59, R63
c
D 7,14,47 M_VREF_MCH Stuff: R64, R59 D
.
To EXTTS#0 (Default) No-stuff: R63
R460 Dimm-1 Stuff: R63
10K To EXTTS#1 No-stuff: R59
1%
s
M_A_DQ[63:0] 8 To EXTTS#0 & EXTTS#1 Stuff: R64, R59, R63
J8A CON200_DDR2-SODIMM-REV
8,15 M_A_A[14:0] M_A_A0 M_A_DQ0
102 A0 DQ0 5
it c
M_A_A1 101 M_A_DQ1
M_A_A2 A1 DQ1 7 M_A_DQ2
100 A2 DQ2 17
M_A_A3 99 M_A_DQ3
98 A4 DQ4 4
M_A_A5 97 M_A_DQ5 14,15,23,24,35,36,42,45,50,56,57 +V3.3M +V1.8 9,10,14,18,45,47,56
94 A6 DQ6 14
M_A_A7 92 M_A_DQ7 J8B CON200_DDR2-SODIMM-REV
93 A8 DQ8 23
M_A_A9 91 M_A_DQ9
M_A_A10 A9 DQ9 25 M_A_DQ10
112 VDD1 VSS16 18
105 A10/AP DQ10 35 111 VDD2 VSS17 24
a
M_A_A11 90 M_A_DQ11
M_A_A12 A11 DQ11 37 M_A_DQ12
117 VDD3 VSS18 41
89 A12 DQ12 20 96 VDD4 VSS19 53
M_A_A13 116 M_A_DQ13
M_A_A14 A13 DQ13 22 M_A_DQ14
95 VDD5 VSS20 42
86 A14 DQ14 36 118 VDD6 VSS21 54
84 M_A_DQ15
A15 DQ15 38 M_A_DQ16
81 VDD7 VSS22 59
8,15 M_A_BS2 85 A16_BA2 DQ16 43 82 VDD8 VSS23 65
M_A_DQ17
DQ17 45 M_A_DQ18 C147 C144
87 VDD9 VSS24 60
107 DQ18 55 103 66
m
8,15 M_A_BS0 BA0 VDD10 VSS25
106 M_A_DQ19 0.1uF 2.2uF
8,15 M_A_BS1 BA1 DQ19 57 M_A_DQ20 10% 10%
88 VDD11 VSS26 127
7,15 M_CS#0 110 S0# DQ20 44 104 VDD12 VSS27 139
115 M_A_DQ21
7,15 M_CS#1 S1# DQ21 46 M_A_DQ22 VSS28 128
7 M_CLK_DDR0 30 CK0 DQ22 56 199 VDDSPD VSS29 145
C 7 M_CLK_DDR#0 32 CK0# DQ23 58
M_A_DQ23
VSS30 165 C
e
164 M_A_DQ24
7 M_CLK_DDR1 CK1 DQ24 61 M_A_DQ25
14 PM_EXTTS#0-1 83 NC1 VSS31 171
7 M_CLK_DDR#1 166 CK1# DQ25 63 120 NC2 VSS32 172
79 M_A_DQ26 R61 0
7,15 M_CKE0 CKE0 DQ26 73 M_A_DQ27
7,15 PM_EXTTS#0 50 NC3 VSS33 177
7,15 M_CKE1 80 CKE1 DQ27 75 69 NC4 VSS34 187
113 M_A_DQ28
8,15 M_A_CAS# CAS# DQ28 62 163 NCTEST VSS35 178
h
108 M_A_DQ29
8,15 M_A_RAS# RAS# DQ29 64 M_A_DQ30 VSS36 190
8,15 M_A_WE# 109 WE# DQ30 74 7,14,47 M_VREF_MCH 1 VREF VSS37 9
Note: SO-DIMM0 SPD Address is A0 Hex SA0_DIM0 198 M_A_DQ31
SA1_DIM0 SA0 DQ31 76 M_A_DQ32 C339 C340 VSS38 21
SO-DIMM0 TS Address is 30 Hex 200 SA1 DQ32 123 201 GND0 VSS39 33
197 M_A_DQ33 0.1uF 2.2uF
DQ33 125 202 155
c
14,15,23 SMB_CLK_M2 SCL GND1 VSS40
10K
10K
195 M_A_DQ34 10% 10%

14,15,23 SMB_DATA_M2 SDA DQ34 135 M_A_DQ35 VSS41 34
DQ35 137 M_A_DQ36 VSS42 132
7,15 M_ODT0 114 ODT0 DQ36 124 47 VSS1 VSS43 144
119 M_A_DQ37
7,15 M_ODT1 ODT1 DQ37 126 M_A_DQ38
133 VSS2 VSS44 156
-s
8 M_A_DM[7:0] DQ38 134 +V1.8 9,10,14,18,45,47,56
183 VSS3 VSS45 168
R151
R160
M_A_DM0 10 M_A_DQ39
M_A_DM1 DM0 DQ39 136 M_A_DQ40
77 VSS4 VSS46 2
26 DM1 DQ40 141 12 VSS5 VSS47 3
M_A_DM2 52 M_A_DQ41
48 VSS6 VSS48 15
67 DM3 DQ42 151 184 VSS7 VSS49 27
M_A_DM4 130 M_A_DQ43 C441 C429 C107 C93
M_A_DM5 DM4 DQ43 153 M_A_DQ44 0.1uF 0.1uF 0.1uF 0.1uF
78 VSS8 VSS50 39
147 DM5 DQ44 140 71 VSS9 VSS51 149
M_A_DM6 170 M_A_DQ45 10% 10% 10% 10%
72 VSS10 VSS52 161
185 DQ46 152 121 28
p
DM7 M_A_DQ47 VSS11 VSS53
8 M_A_DQS[7:0]
M_A_DQS0 DQ47 154 M_A_DQ48
122 VSS12 VSS54 40
13 DQS0 DQ48 157 196 VSS13 VSS55 138
M_A_DQS1 31 M_A_DQ49
M_A_DQS2 DQS1 DQ49 159 M_A_DQ50
193 VSS14 VSS56 150
51 DQS2 DQ50 173 8 VSS15 VSS57 162
M_A_DQS3 70 M_A_DQ51 Layout Note: Place these Caps near So-Dimm0.
DQ51 175
o
M_A_DQS4 DQS3 M_A_DQ52
131 DQS4 DQ52 158
DQS5 DQ53 160
t
B M_A_DQS7 DQS6 DQ54 174 M_A_DQ55 B
8 M_A_DQS#[7:0] 188 DQS7 DQ55 176
M_A_DQS#0 11 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 179 M_A_DQ57
29 DQS#1 DQ57 181
p
68 DQS#3 DQ59 191
146 DQS#5 DQ61 182
186 DQS#7 DQ63 194
la
Layout Note: Place these Caps near So-Dimm0.
9,10,14,18,45,47,56 +V1.8
.
C515 C97 C89 C103 C458 C459
330uF 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
10% 10% 10% 10% 10%
ww Oakmont Form Factor Reference Design Intel Confidential

A
w
Title
DDR SODIMM 0

A
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
M_B_DQ[63:0] 8
J9A CON200_DDR2-SODIMM-STAN
8,15 M_B_A[14:0] M_B_A0 M_B_DQ0
102 A0 DQ0 5
M_B_A1 101 M_B_DQ1
M_B_A2 A1 DQ1 7 M_B_DQ2
100 A2 DQ2 17
it c
M_B_A3 99 M_B_DQ3 13,15,23,24,35,36,42,45,50,56,57 +V3.3M
98 A4 DQ4 4
M_B_A5 97 M_B_DQ5
M_B_A6 A5 DQ5 6 M_B_DQ6 9,10,13,18,45,47,56 +V1.8 J9B CON200_DDR2-SODIMM-STAN
94 A6 DQ6 14
M_B_A7 92 M_B_DQ7
93 A8 DQ8 23 112 VDD1 VSS16 18
M_B_A9 91 M_B_DQ9
M_B_A10 A9 DQ9 25 M_B_DQ10
111 VDD2 VSS17 24
105 A10/AP DQ10 35 117 VDD3 VSS18 41
M_B_A11 90 M_B_DQ11
M_B_A12 A11 DQ11 37 M_B_DQ12
96 VDD4 VSS19 53
89 A12 DQ12 20 95 VDD5 VSS20 42
a
M_B_A13 116 M_B_DQ13
M_B_A14 A13 DQ13 22 M_B_DQ14
118 VDD6 VSS21 54
86 A14 DQ14 36 81 VDD7 VSS22 59
84 M_B_DQ15
A15 DQ15 38 M_B_DQ16
82 VDD8 VSS23 65
8,15 M_B_BS2 85 A16_BA2 DQ16 43 87 VDD9 VSS24 60
M_B_DQ17
DQ17 45 M_B_DQ18
103 VDD10 VSS25 66
8,15 M_B_BS0 107 BA0 DQ18 55 88 VDD11 VSS26 127
106 M_B_DQ19
8,15 M_B_BS1 BA1 DQ19 57 M_B_DQ20
104 VDD12 VSS27 139
110 DQ20 44 128
m
7,15 M_CS#2 S0# VSS28
13,15,23,24,35,36,42,45,50,56,57 +V3.3M 115 M_B_DQ21
7,15 M_CS#3 S1# DQ21 46 M_B_DQ22
199 VDDSPD VSS29 145
7 M_CLK_DDR3 30 CK0 DQ22 56 VSS30 165
32 M_B_DQ23 C171 C758
7 M_CLK_DDR#3 CK0# DQ23 58 M_B_DQ24 0.1uF 2.2uF
83 NC1 VSS31 171
7 M_CLK_DDR4 164 CK1 DQ24 61 120 NC2 VSS32 172
C R158
7 M_CLK_DDR#4 166 CK1# DQ25 63
M_B_DQ25
13 PM_EXTTS#0-1
R58 0 PM_EXTTS#0-1_R 10% 10% 50 NC3 VSS33 177 C
e
10K 79 M_B_DQ26
7,15 M_CKE3 CKE0 DQ26 73 M_B_DQ27
69 NC4 VSS34 187
7,15 M_CKE4 80 CKE1 DQ27 75 163 NCTEST VSS35 178
113 M_B_DQ28 R60 0
8,15 M_B_CAS# CAS# DQ28 62 M_B_DQ29
7,15 PM_EXTTS#1
NO_STUFF VSS36 190
8,15 M_B_RAS# 108 RAS# DQ29 64 7,13,47 M_VREF_MCH 1 VREF VSS37 9
109 M_B_DQ30
8,15 M_B_WE# WE# DQ30 74 VSS38 21
h
SA0_DIM1 198 M_B_DQ31 C338 C2033
SA1_DIM1 SA0 DQ31 76 M_B_DQ32 0.1uF 2.2uF
201 GND0 VSS39 33
200 SA1 DQ32 123 202 GND1 VSS40 155
197 M_B_DQ33 10% 10%
13,15,23 SMB_CLK_M2 SCL DQ33 125 M_B_DQ34 VSS41 34
13,15,23 SMB_DATA_M2 195 SDA DQ34 135 VSS42 132
Note: SO-DIMM1 SPD Address is A4 Hex M_B_DQ35 +V1.8 9,10,13,18,45,47,56
DQ35 137 47 144
c
M_B_DQ36 VSS1 VSS43
SO-DIMM1 TS Address is 34 Hex 7,15 M_ODT2 114 ODT0 DQ36 124 133 VSS2 VSS44 156
119 M_B_DQ37
7,15 M_ODT3 ODT1 DQ37 126 M_B_DQ38
183 VSS3 VSS45 168
8 M_B_DM[7:0]
M_B_DM0 DQ38 134 M_B_DQ39 C433 C447 C104 C95
77 VSS4 VSS46 2
10 DM0 DQ39 136 12 VSS5 VSS47 3
R157 M_B_DM1 M_B_DQ40 0.1uF 0.1uF 0.1uF 0.1uF
-s
26 DM1 DQ40 141 48 VSS6 VSS48 15
10K M_B_DM2 52 M_B_DQ41 10% 10% 10% 10%
M_B_DM3 DM2 DQ41 143 M_B_DQ42
184 VSS7 VSS49 27
67 DM3 DQ42 151 78 VSS8 VSS50 39
M_B_DM4 130 M_B_DQ43
71 VSS9 VSS51 149
147 DM5 DQ44 140 72 VSS10 VSS52 161
M_B_DM6 170 M_B_DQ45
121 VSS11 VSS53 28
185 DM7 DQ46 152 122 VSS12 VSS54 40
M_B_DQ47
8 M_B_DQS[7:0]
M_B_DQS0 DQ47 154 M_B_DQ48
196 VSS13 VSS55 138
13 DQ48 157 Layout Note: Place these Caps near So-Dimm1. 193 150
p
M_B_DQS1 DQS0 M_B_DQ49 VSS14 VSS56
31 DQS1 DQ49 159 8 VSS15 VSS57 162
M_B_DQS2 51 M_B_DQ50
M_B_DQS3 DQS2 DQ50 173 M_B_DQ51
70 DQS3 DQ51 175
M_B_DQS4 131 M_B_DQ52 +V1.8 9,10,13,18,45,47,56
M_B_DQS5 DQS4 DQ52 158 M_B_DQ53
148 DQ53 160
o
M_B_DQS6 DQS5 M_B_DQ54
169 DQS6 DQ54 174
M_B_DQS7 188 M_B_DQ55
8 M_B_DQS#[7:0] DQS7 DQ55 176
t
M_B_DQS#0 11 M_B_DQ56
B M_B_DQS#1 DQS#0 DQ56 179 M_B_DQ57 B
29 DQS#1 DQ57 181
M_B_DQS#2 49 M_B_DQ58 C109 C461 C462 C92 C98 C471
M_B_DQS#3 DQS#2 DQ58 189 M_B_DQ59 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 330uF
68 DQS#3 DQ59 191
M_B_DQS#4 129 M_B_DQ60 10% 10% 10% 10% 10%
M_B_DQS#5 DQS#4 DQ60 180 M_B_DQ61
p
146 DQS#5 DQ61 182
M_B_DQS#6 167 M_B_DQ62
M_B_DQS#7 DQS#6 DQ62 192 M_B_DQ63
186 DQS#7 DQ63 194
la
Layout Note: Place these Caps near So-Dimm1.
.
SO-DIMM 1 is placed farther from
the GMCH than SO-DIMM 0

A
w
Title
DDR2 SODIMM 1

A
5 4 3 2 1
5 4 3 2 1
DDR2 Thermal Sensor So-Dimm 0 & 1
o m
Layout Note: +V3.3M 13,14,23,24,35,36,42,45,50,56,57
Place Q17
under SO-DIMM0
U8
c
3 1 VDD SCLK 8 SMB_CLK_M2 13,14,23
D Q15 D
.
2N3904 1 DDR_THERM2 2 7 +V0.9 47,56
D+ SDATA SMB_DATA_M2 13,14,23
DDR_THERM1 3 6 PM_EXTTS#0_D R52 0
2 D- ALERT# PM_EXTTS#0 7,13
R545 56
M_CKE0 7,13
R51 0 PM_EXTTS#1_D 4 5 R535 56
s
7,14 PM_EXTTS#1 THERM# GND M_CKE1 7,13
R540 56
M_CKE3 7,14
ADM1032AR R539 56
M_CKE4 7,14
Layout Note: R580 56
M_ODT0 7,13
it c
Place U6 R587 56
M_ODT1 7,13
under SO-DIMM1 R579 56
M_ODT2 7,14
R586 56
M_ODT3 7,14
R573 56
M_A_BS0 8,13
R568 56
M_A_BS1 8,13
R549 56
M_A_BS2 8,13
R577 56
M_A_WE# 8,13
R581 56
M_A_CAS# 8,13
a
R572 56
M_A_RAS# 8,13
R570 56
M_B_BS0 8,14
R567 56
M_B_BS1 8,14
R541 56
M_B_BS2 8,14
Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9
+V0.9 47,56 R574 56
M_B_WE# 8,14
R578 56
m
M_B_CAS# 8,14
R571 56
M_B_RAS# 8,14
R576 56
M_CS#0 7,13
R585 56
M_CS#1 7,13
C C452 C434 C2034 C440 C432 C455 C473 C469 C444 C467 C475 C477 C450 R575 56
M_CS#2 7,14
C
e
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R582 56
M_CS#3 7,14
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
M_A_A[14:0] 8,13
R563 56 M_A_A0
R564 56 M_A_A1
h
R559 56 M_A_A2
C435 C490 C489 C2035 C445 C431 C2036 C485 C484 C465 C466 C443 C476 R560 56 M_A_A3
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R534 56 M_A_A4
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% R556 56 M_A_A5
R555 56 M_A_A6
c
R533 56 M_A_A7
R547 56 M_A_A8
R548 56 M_A_A9
R569 56 M_A_A10
R551 56 M_A_A11
s
R546 56 M_A_A12
R584 56 M_A_A13
R10528 56 M_A_A14
-
M_B_A[14:0] 8,14
R562 56 M_B_A0
R561 56 M_B_A1
R558 56 M_B_A2
R557 56 M_B_A3
p
R554 56 M_B_A4
R553 56 M_B_A5
R538 56 M_B_A6
R537 56 M_B_A7
R544 56 M_B_A8
o
R543 56 M_B_A9
R566 56 M_B_A10
t
R536 56 M_B_A11
B R542 56 M_B_A12 B
R583 56 M_B_A13
R104 56 M_B_A14
la p
w .
w
A A
w
Title
DDR2 TERMINATION AND THERMAL SENSOR

A
5 4 3 2 1
5 4 3 2 1
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
C333
m
0.1uF
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
7
VP
o
CR3009 ESD DIODE ARRAY
CRT_L2_RED
c
1 I/O1 I/O6 8
R457 CRT_L2_BLUE 2 6 CRT_Q_VSYNC
10K I/O2 I/O5
D 5%
CRT_L2_GREEN 4 I/O3 I/O4 5 CRT_Q_HSYNC D
.
42 DOCK_CRT_EN#
VN
s
3
it c
a
5,17,18,24,26,28,30..32,34,49,50,52,53,56,57 +V5S
+V3.3S 5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
m
C371 C388 C389 C387 RT1
U10 0.1uF 0.1uF 0.1uF 0.1uF +1 2
C 12 1 C
+V5S_L_DAC_FB
42 DOCK_CRT_EN# SEL VDD1
e
VDD2 4 1 1.1A
7 CRT_RED 2 Y_A VDD3 9
5 19 Q52
7 CRT_GREEN Y_B VDD4
6 BAT54
7 CRT_BLUE Y_C
7 CRT_VSYNC 8 Y_D I_A0 24 CRT_RED_DOCK 45
h
7 CRT_HSYNC 11 Y_E I_B0 22 CRT_GRN_DOCK 45 3
I_C0 18 CRT_BLUE_DOCK 45
3 17 +V5S_CRT_DDC FB26
GND1 I_D0 CRT_VSYNC_DOCK 45
7 14 50OHM
+V5S_L_DAC
GND2 I_E0 CRT_HSYNC_DOCK 45
10
c
GND3 CRT_Q_RED R429 R427
20 GND4 I_A1 23
21 CRT_Q_GREEN 2.2K 2.2K
I_B1 CRT_Q_BLUE
I_C1 16
15 CRT_Q_VSYNC
I_D1 CRT_Q_HSYNC
-s
I_E1 13
CRT_DDC_DATA_ISO
PI3V512QE
CRT_DDC_CLK_ISO
p
CRT_Q_RED FB23 CRT_L_RED FB1
47ohm@100MHz 47ohm@100MHz
C316 C2 C3
R426 10pF 22pF 10pF
150 5% 5% 5% J2
o
1% GND1 6
CRT_L2_RED RED 1 11 NC2
t
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S GND2 7
B CRT_L2_GREEN GRN 2 12 DATA B
CRT_Q_GREEN FB24 CRT_L_GREEN FB2 GND3 8
47ohm@100MHz 47ohm@100MHz CRT_L2_BLUE BLU 3 13 HSYNC
R428 C9 C5 C317 VCC 9
C336 150 10pF 22pF 10pF NC1 14 VSYNC
+V5S_L_DAC
1% 4
0.1uF 5% 5% 5% GND4 10
GND5 5 15 CLK
5
Q53 GND_SHLD
G1
G2
CRT_Q_BLUE FB25 CRT_L_BLUE FB3 .
la
DOCK_CRT_EN# 2 4 CRT_EN# 47ohm@100MHz 47ohm@100MHz
R430 C14 C16 C320
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S +V5S 5,17,18,24,26,28,30..32,34,49,50,52,53,56,57 150 10pF 22pF 10pF
1% 5% 5%
INVERTER 5%
3
.
R446
2.2K
Q144 CRT_Q_VSYNC
1
BSS138 U71 C335

1 8 0.1uF
w
OE1# VCC
7 CRT_DDC_DATA 2 3 CRT_DDC_DATA_Q 2 7 10% CRT_Q_HSYNC
2
1A OE2# CRT_DDC_DATA_ISO
45 CRT_DDC_DATA_DOCK 3 1B 2B 6
4 5 C318 C321
GND 2A 33pF 33pF
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 74CBT3306 5% 5%
1
w
+V5S 5,17,18,24,26,28,30..32,34,49,50,52,53,56,57
R19
2.2K Q145
A A
1
BSS138 U4 C23
1 OE1# VCC 8 0.1uF Oakmont Form Factor Reference Design Intel Confidential
w
2 3 CRT_DDC_CLK_Q 2 7 10%
7 CRT_DDC_CLK
2
1A OE2#
45 CRT_DDC_CLK_DOCK 3
4
1B 2B 6
5
CRT_DDC_CLK_ISO Title
GND 2A
5,7,9,10,17..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S CRT
74CBT3306
1

A
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
5,16,18,24,26,28,30..32,34,49,50,52,53,56,57 +V5S
5,7,9,10,16,18,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
a
49,52,53,55,56 +VBAT
5,16,18,24,26,28,30..32,34,49,50,52,53,56,57 +V5S
C355
0.1uF
m
C346
0.1uF R468
1
U6 10K R467 C374
LVDS Panel Backlight 10K 0.1uF
40 L_BKLTSEL0# 1 OE1# VCC 8
C BIOS Note: Disable both 7 L_BKLT_CTRL 2 7 L_BKLTSEL1# 40
10% C
2
1A OE2#
e
BKLTSEL lines before 3 6 U73
1B 2B
4 5 L_CTRL_DATA 7 40 L_BKLTSEL1# 1 5
enabling one. GMCH_PWM Support GND 2A OE# VCC C375
74CBT3306 7 L_CTRL_CLK 2 0.1uF J7
GM_Data_D Support A
1 VDD_BLI
h
GM_CLK_D Support 3 4 2
GND Y VSS_BLI
3 VSS_DBC
74CBTLV1G125 4
DBL_CLK VDD_DBC
5 DBL_CLK
L_BRIGHTNESS 6
c
DBL_DATA
7 L_BKLT_EN 7 ENA_BL
5,7,9,10,16,18,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S R497 100K 8 NC1
9 VDD_ALS
10 VSS_ALS
-s
42 ALS_CLK 11 ALS_CLK
42 ALS_DATA 12 ALS_DATA
42 KBC_PROG_TX# 13 ALS_INTR
C379 14
R499 R500 0.1uF NC2
15 VSS_VDL
2.2K 2.2K L_VDD_VDL 16 VDD_VDL1
17 VDD_VDL2
18 VDD_VCL
19
p
RSVD
7 LVDS_DDC_CLK 20 VCL_CLK
7 LVDS_DDC_DATA 21 VCL_DATA
7 LVDSA_DATA#0 22 A0M
7 LVDSA_DATA0 23 A0P
24
o
VSS_SHIELD1
t
27 VSS_SHIELD2
B 7 LVDSA_DATA#2 28 B
A2M
30 VSS_SHIELD3
p
5,7,9,10,16,18,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 33 VSS_SHIELD4
34
SI2307DS
7 LVDSA_CLK# VDL_CLKAM
7 LVDSA_CLK 35 VDL_CLKAP
36 VSS
C381 37
la
7 LVDSB_DATA#0 B0M
2 3 L_VDD_VDL Adaptive 0.1uF C380 7 LVDSB_DATA0 38
10% 0.1uF B0P
39
C366 Q65 C364 C376 Clocking NO_STUFF 10% 40
VSS_SHIELD5
7 LVDSB_DATA#1 B1M
R493 1000pF 22UF 0.1uF NO_STUFF 7 LVDSB_DATA1 41
1M B1P
.
10% 42
1
VSS_SHIELD6
7 LVDSB_DATA#2 43 B2M
R492 100K L_VDDEN_D# 44
7 LVDSB_DATA2 B2P
L_VDDEN#
45 VSS_SHIELD7
TP_LVDS_RSVD_B3M 46
TP_LVDS_RSVD_B3P B3M
47 B3P
48
w
VSS_SHIELD8
7 LVDSB_CLK# 49 VDL_CLKBM
7 LVDSB_CLK 50 VDL_CLKBP
3
Q64 LVDS,CONN50
BSS138 Adaptive C378 C377
1 0.1uF 0.1uF
7 LVDS_VDD_EN Clocking 10% 10%
w
NO_STUFF NO_STUFF
2
R494
A 100K A
w
Title
LVDS

A
5 4 3 2 1
5 4 3 2 1
9,10,13,14,45,47,56 +V1.8 +V2.5S_3.3S_HDMI

+V1.8S_HDMI
5,16,17,24,26,28,30..32,34,49,50,52,53,56,57 +V5S
m
8 Q3001 HDMI_TX2P
7 3 IRF7822 C37
3.92k
3.92k
6 2 R33 300 HDMI_RC_TX2 0.1uF
1%
1%
5 1 Place R33 & C37 1" from U12 10%
o
+V2.5S_3.3S_HDMI +V3.3S 5,7,9,10,16,17,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 HDMI_TX2N HDMI_DDC_CLK_DOCK R498 2.2K
HDMI_DDC_DATA_DOCK R510 2.2K
R57
R10529
DDC_CLK_HDMI_ISO R503 2.2K
57 VBATA_SLEEP
HDMI_TX1P DDC_DATA_HDMI_ISO R511 2.2K
R879 0 C38 SDVO_CTRLCLK
c
R34 300 HDMI_RC_TX1 0.1uF SDVO_CTRLDATA
D Place R34 & C38 1" from U12 10% D
.
475
NO_STUFF1%
For 2.5 volt for
the SDVO GM Bus HDMI_TX1N
NO_STUFF R879 and
STUFF R877 and
R877
HDMI_TX0P
878. C39 J5
s
R35 300 HDMI_RC_TX0 0.1uF HDMI_TX2P_Q 1
Place R35 & C39 1" from U12 10% 1
2 2
HDMI_TX2N_Q 3
HDMI_TX0N HDMI_TX1P_Q 3
4 4
NO_STUFF 1%
1.5K
it c
5 5
C788 C789 HDMI_TX1N_Q 6
0.1uF 1.0uF C40 HDMI_TXCP HDMI_TX0P_Q 6
7 7
10% R36 300 HDMI_RC_CLK 0.1uF 8 8
R878
Place R36 & C40 1" from U12 10% HDMI_TX0N_Q 9
HDMI_TXCP_Q 9
10 10
11 11
HDMI_TXCN 5,16,17,24,26,28,30..32,34,49,50,52,53,56,57 +V5S HDMI_TXCN_Q 12
TP_HDMI_REMOTE 12
13 13
14 14
a
HDMI_EXT_SWG_R R495 392 R463 0 DDC_CLK_HDMI_ISO 15
1% DDC_DATA_HDMI_ISO 15
16 16 GND1 20
U15 +VCC_HDMI
29
28
26
25
23
22
20
19
31
17 17 GND2 21
+V5S_HDMI_FUSED 18 22
HDMI_HTPLG_Q 18 GND3
39 19 23
EXT_SWING
TX2+
TX2-
TX1+
TX1-
TX0+
TX0-
TXC+
TXC-
HTPLG HDMI_HTPLG_uCTRL 19 19 GND4
65 THM
C59 0.1uF HDMI_SDIP 9 HDMI
7 SDVOB_INTP VCC0
46 15 R38
m
C61 0.1uF HDMI_SDIN SDI+ VCC1 15K
7 SDVOB_INTN 47 SDI- VCC2 48
C74 0.1uF 38 1%
7 SDVOB_RP VCC3
HDMI_SDRP 51
C75 0.1uF HDMI_SDRN SDR+
7 SDVOB_RN 52 SDR- GND1 5
C 7 SDVOB_GP
C76 0.1uF
GND2 10 +AVCC_HDMI C
e
HDMI_SDGP 54
C77 0.1uF HDMI_SDGN SDG+
55
7 SDVOB_GN
7 SDVOB_BP
C78 0.1uF SDG- SiI 1390 AVCC0
AVCC1
21
27
+V1.8S_HDMI +V3.3S 5,7,9,10,16,17,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
HDMI_SDBP 57 HDMI CONTROLLER
C79 0.1uF HDMI_SDBN SDB+ FB5
7 SDVOB_BN 58 SDB- AGND1 18
h
C80 0.1uF 24 60ohm@100MHz FB30
7 SDVOB_CLKP AGND2
HDMI_SDCP 60 30 C50 C404 C400 60ohm@100MHz
C81 0.1uF HDMI_SDCN SDC+ AGND3 0.1uF 10uF 10uF
7 SDVOB_CLKN 61 SDC-
34 OTPVCC 10%
R67 1K HDMI_EXT_RES_R OTPVCC OVCC
49 64
c
1% EXT_RES OVCC
1 17 PVCC1_FB FB27
22,42,44,45 BUF_PLT_RST# RESET# PVCC1
7 16 C360 C359 C358 60ohm@100MHz
7 SDVO_CTRLCLK SDSCL PGND1
6 1000pF 0.1uF 1uF
7 SDVO_CTRLDATA SDSDA PVCC2_FB 10% 10%
s
PVCC2 32
+V3.3S 5,7,9,10,16,17,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 R508 1K HDMI_A1_R 8 33
1% A1 PGND2 +SVCC_HDMI
DDC_DATA_HDMI C345 C350 C31 C25
-
12 SDADCC SVCC0 50
DDC_CLK_HDMI 11 56 FB4 0.1uF 0.1uF 0.1uF 0.1uF
SCLDDC SVCC1 C41 C42 C36 60ohm@100MHz
13
44 SPDIF/SDI/SD2/R3
C53 SDAROM 1000pF 0.1uF 1uF

14 41
LSDA/ASEL0/R1
LSCL/ASEL1/R2
0.1uF U2008 SCLROM GND3 10% 10%

45
35 SD1/RST#/R8
GND4
43 WS/SYNC/R4
36 SD0/SDO/R7
10% 1 8 40 53
42 MCLK/BCLK
p
A0 VCC TEST SGND1
2 7 59
LINT#/R0
A1 WP SGND2
SCK/LA2
HDMI_SCLROM_U SPVCC_FB FB6
13
18
20
30
40
42
3 A2 SCL 6 SPVCC 62
5
8
4 5 HDMI_SDAROM_U C407 C411 60ohm@100MHz U72
GND SDA 1000pF C73 10uF
63
Vdd1
Vdd2
Vdd3
Vdd4
Vdd5
Vdd6
Vdd7
Vdd8
AT24C02-2.7_TSSOP SPGND +V3.3S 5,7,9,10,16,17,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
HDA_BIT_CLK_HDMI
10% 100pF
o
HDA_SDOUT_HDMI
HDA_SDIN2_HDMI
HDA_SYNC_HDMI
HDA_RST#_HDMI
37
4
3
2
+V1.8S_HDMI +VCC_HDMI 38
C0P-A HDMI_TXCP_DOCK 45
OUT A (SEL LOW)

C0N-A 37 HDMI_TXCN_DOCK 45
B FB8 36 B
HDMI_SCK/LA2_R
HDMI_LINT#_R C1P-A HDMI_TX0P_DOCK 45

60ohm@100MHz HDMI_TXCP 2 35
C0P C1N-A HDMI_TX0N_DOCK 45
C436 C62 C54 C55 C393 C418 C372 C417 C373 HDMI_TXCN 3 29
PI3HDMI412A-HDMISW
C0N C2P-A HDMI_TX1P_DOCK 45
10uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 100pF R62 HDMI_TX0P 6 28
22 C1P C2N-A HDMI_TX1N_DOCK 45
INPUT
10% 10% 10% 10% 10% 10% 10% HDMI_TX0N
p
7 C1N C3P-A 27 HDMI_TX2P_DOCK 45
HDMI_TX1P 11 26
C2P C3N-A HDMI_TX2N_DOCK 45
HDMI_TX1N 12
HDMI_TX2P C2N
15 C3P
+V3.3S 5,7,9,10,16,17,19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 HDMI_TX2N 16 34 HDMI_TXCP_Q
C3N C0P-B
OUT B (SEL HIGH)

+AVCC_HDMI 33 HDMI_TXCN_Q
la
HDMI_LINT# 19 C0N-B
1K
33
33
33
33
33
32 HDMI_TX0P_Q
FB28 HDMI_LSDA 19 C1P-B HDMI_TX0N_Q
HDMI_LSCL 19 C1N-B 31
60ohm@100MHz 25 HDMI_TX1P_Q
C392 C363 C361 C362 C2P-B HDMI_TX1N_Q
42 DOCK_HDMI_EN# 9 SEL C2N-B 24
.
R53
R46
R47
R55
R10530
10uF 1000pF 0.1uF 1000pF C370 23 HDMI_TX2P_Q

C3P-B
R59
10% 10% 10% 100pF 22 HDMI_TX2N_Q

C3N-B
4,10,24..26,48,56 +V1.5S
Vss0
Vss1
Vss2
Vss3
Vss4
Vss5
Vss6
Vss7
Vss8
Vss9
21
21,27,28,45
21,27,28
HDA_SDOUT
HDA_RST#
21,27,28,45
21,27,28,45
HDA_BIT_CLK
HDA_SYNC
HDA_SDIN2
+V1.8S_HDMI
43
1
4
10
14
17
19
21
39
41
w
+SVCC_HDMI C26 C24 C351 C34
+V3.3S 0.1uF 0.1uF 0.1uF 0.1uF
FB7
60ohm@100MHz +V5S
C414 C406 C408 C409
10uF 1000pF 0.1uF 1000pF C423 C386 C405 C394 C399
10% 10% 10% 100pF R518 R509 U13 0.1uF 0.1uF 0.1uF 0.1uF
w
2.2K 2.2K DOCK_HDMI_EN# 12 1
SEL VDD1
VDD2 4
DDC_CLK_HDMI 2 9
DDC_DATA_HDMI Y_A VDD3
5 19
A Y_B VDD4 A
19 HDMI_HTPLG
R68 1K HDMI_HTPLG_R
6
8
Y_C
Y_D I_A0 24 HDMI_DDC_CLK_DOCK 45
w
11 Y_E I_B0 22 HDMI_DDC_DATA_DOCK 45
3
I_C0 18
17
Title
GND1 I_D0 HDMI_HTPLG_DOCK 45
7 GND2 I_E0 14 HDMI
10 GND3
20 GND4 I_A1 23 DDC_CLK_HDMI_ISO 19
21
I_B1
16
DDC_DATA_HDMI_ISO 19 Size Document Number Rev
I_C1 HDMI_HTPLG_Q
I_D1 15
13
A
I_E1
PI3V512QE Date: Sheet 18 of 64

5 4 3 2 1
5 4 3 2 1
m
C115 10pF HDMI_X1_XTAL
5%
3
o
Y1 5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
32MHZ
1
c
C114 10pF HDMI_X2_XTAL
D 5% D
.
5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
C412 C446
0.1uF 10uF
s
10%
C413
0.1uF U20
it c
10% 38
VDD
5
Q18 15 27
XTAL1 ALE/PROG#
14 XTAL2
2 4 HDMI_CTRL_RST 4 29
7,22,25,26,40,58 PLT_RST# RST EA#
37 P0.0/AD0 P3.0/RxD 5
INVERTER 36 7
5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 3 P0.1/AD1 P3.1/TxD
35 P0.2/AD2 P3.2/INT0# 8
34 P0.3/AD3 P3.3/INT1# 9 HDMI_LINT# 18
a
5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 33 10
R529 P0.4/AD4 P3.4/T0
32 P0.5/AD5 P3.5/T1 11
4.7K 31 P0.6/AD6 P3.6/WR# 12
R532 30 13
Q67 1K P0.7/AD7 P3.7/RD#
1% TP_SST_P2.0
40 P1.0/T2 P2.0/A8 18
3 2 HDMI_CTRL_P1.1_R 41 19 TP_SST_P2.1
18 HDMI_HTPLG P1.1/T2_EX P2.1/A9
BSS138 42 20
m
18 HDMI_HTPLG_uCTRL P1.2/ECI P2.2/A10
43 P1.3/CEX0 P2.3/A11 21
,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S DDC_CLK_HDMI_ISO_SST 44 22
DDC_DATA_HDMI_ISO_SST P1.4/SS#/CEX1 P2.4/A12
1 23
1
P1.5 P2.5/A13
2 P1.6 P2.6/A14 24
C 18 HDMI_LSCL C
3 P1.7 P2.7/A15 25
e
5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 18 HDMI_LSDA
P4.0 17
26 PSEN# P4.1 28
1 P4.3/INT2# 6
16 VSS/GND P4.2/INT3# 39
h
3 2 SST89V54RD2-33-C-TQJE1390
18 DDC_CLK_HDMI_ISO
c
Q17
BSS138
.
5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
s
1
-
18 DDC_DATA_HDMI_ISO 3 2
p
Q66
BSS138
.
t o
B B
5,7,9,10,16..18,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
la p
.
R565 R550 R530 R527 R531
4.7K 4.7K 4.7K 2.2K 2.2K
w
HDMI_LINT#
HDMI_LSDA
HDMI_LSCL
DDC_CLK_HDMI_ISO_SST
DDC_DATA_HDMI_ISO_SST
w
Title
w
HDMI CONTROLLER

A
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
3,4,6,9,10,21,24,45,48,54,56 +V1.05S
it c
a
21..26,29,39..42,44..48,50,51,55..58 +V3.3A
3,4,6,9,10,21,24,45,48,54,56 +V1.05S
m
Place Place R27 R26
close R24 R523 close to 54.9 54.9 Place close
1%
C to ITP 39.2_1% 150
1%
CPU 1% to ITP C
e
Place R202
close to R205
J6
h
1 27 C349 R462
3 ITP_TDI TDI VTT0 150
2 28 0.1uF
3 ITP_TMS TMS VTT1 1%
5 26 10%
3 ITP_TCK TCK VTAP
3 ITP_TDO 7 TDO
3
c
3 ITP_TRST# TRST#
R22 100 ITP_RST_R# 12 25
3,6 H_CPURST# RESET# DBR# ITP_DBRESET# 3,55
1% 24
DBA# 3,4,6,9,10,21,24,45,48,54,56 +V1.05S
11 FBO
Place to
s
eliminate stub on 8 23
H_CPURST# 37 CLK_ITP# BCLKN BPM0# ITP_BPM#0 3
9 21 R502
37 CLK_ITP BCLKP BPM1# ITP_BPM#1 3 54.9 Place close
-
BPM2# 19 ITP_BPM#2 3 1%
10 17 to CPU
GND0 BPM3# ITP_BPM#3 3
14 GND1 BPM4# 15 ITP_BPM#4 3
16 GND2 BPM5# 13 ITP_BPM#5 3
18 GND3
20 4
p
GND4 NC1
22 GND5 NC2 6
ITP700-FLEXCON
t o
B B
p
Place
Place close R520 R25 close to
to CPU 680 27.4 ITP
1%
. la
A

A
w
Title
ITP

A
5 4 3 2 1
5 4 3 2 1
+V3.3A 20,22..26,29,39..42,44..48,50,51,55..58
+V3.3A_RTC 24
Q46
1 3
m
C284
BAT54 1uF
Place near accessible
o
Q101 location on top. C713 10pF
BAT_D 1 3 R789 20K
1
R408 BAT54 C708 Y6 R811
32.7680KHZ
1uF
0
1K 10M
c
R410
D 1M D
NO_STUFF
.
4
BAT
R249
C714 10pF U40A
LPC_AD[3:0] 40,42,44
1
RTC_X1 AG25 E5 LPC_AD0

RTC_X2 RTCX1 FWH0/LAD0 LPC_AD1
AF24 F5
s
RTCX2 FWH1/LAD1 LPC_AD2
FWH2/LAD2 G8
BT1 RTC_RST# AF23 F6 LPC_AD3
Battery_Holder RTCRST# FWH3/LAD3
SM_INTRUDER# AD22 C4
RTC
LPC
INTRUDER# FWH4/LFRAME# LPC_FRAME# 40,42,44
it c
ICH_INTVRMEN AF25 G9
2
LAN100_SLP INTVRMEN LDRQ0# ICH_DRQ#0 40

AD21 LAN100_SLP LDRQ1#/GPIO23 E6 ICH_DRQ#1 40
+V1.05S 3,4,6,9,10,20,24,45,48,54,56
35 GLAN_CLK B24 GLAN_CLK A20GATE AF13 H_A20GATE 42
A20M# AG26 H_A20M# 3
35 LAN_RSTSYNC D22 LAN_RSTSYNC
AF26 R813
DPRSTP# H_DPRSTP# 3,7,52 56
35 LAN_RXD0 C21 LAN_RXD0 DPSLP# AE26 H_DPSLP# 3
B21
LAN / GLAN
35 LAN_RXD1 LAN_RXD1
a
35 LAN_RXD2 C22 LAN_RXD2 FERR# AD24 H_FERR# 3
+V1.5S_PCIE_ICH 22,24
35 LAN_TXD0 D21 LAN_TXD0 CPUPWRGD/GPIO49 AG29 H_PWRGD 3
35 LAN_TXD1 E20 LAN_TXD1
35 LAN_TXD2 C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# 3
3,4,6,9,10,20,24,45,48,54,56 +V1.05S
R819 AH21 AE24
CPU
24.9 36 ENRGY_DET_GPIO13 GLAN_DOCK#/GPIO13 INIT# H_INIT# 3
AC20 H_INTR 3
m
1% INTR
D25 GLAN_COMPI RCIN# AH14 H_RCIN# 23,42
GLAN_COMP C25 GLAN_COMPO
NMI AD23 H_NMI 3
AJ16 AG28 R392
18,27,28,45 HDA_BIT_CLK HDA_BIT_CLK SMI# H_SMI# 3
C 18,27,28,45 HDA_SYNC AJ15 HDA_SYNC
56 C
e
STPCLK# AA24 H_STPCLK# 3
18,27,28 HDA_RST# AE14 HDA_RST#
AE27 H_THERMTRIP_R R798 24.9
THRMTRIP# 1% PM_THRMTRIP# 3,7
28 HDA_SDIN0 AJ17 HDA_SDIN0
AH17 AA23 TP_ICH_AA23
IHDA
27 HDA_SDIN1 HDA_SDIN1 TP8
h
18 HDA_SDIN2 AH15 HDA_SDIN2 IDE_PDD[15:0] 32
AD13 V1 IDE_PDD0
45 HDA_SDIN3 HDA_SDIN3 DD0
U2 IDE_PDD1
DD1 IDE_PDD2
18,27,28,45 HDA_SDOUT AE13 HDA_SDOUT DD2 V3
T1 IDE_PDD3
c
DD3 IDE_PDD4
45 HDA_DOCK_EN# AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
AG14 T5 IDE_PDD5
45 HDA_DOCK_RST# HDA_DOCK_RST#/GPIO34 DD5
AB2 IDE_PDD6
DD6 IDE_PDD7
58 SATA_LED# AF10 SATALED# DD7 T6
IDE_PDD8
-s
DD8 T3
C280 3900pF SATA_RXN0_C AF6 R2 IDE_PDD9
30 SATA_RXN0 SATA0RXN DD9
C281 3900pF SATA_RXP0_C AF5 T4 IDE_PDD10
30 SATA_RXP0 SATA0RXP DD10
C279 3900pF SATA_TXN0_C AH5 V6 IDE_PDD11
30 SATA_TXN0 SATA0TXN DD11
C278 3900pF SATA_TXP0_C AH6 V5 IDE_PDD12
30 SATA_TXP0 SATA0TXP DD12
U1 IDE_PDD13
R407 10K 1% SATA_RXN1 DD13 IDE_PDD14
AG3 V2
IDE
R401 10K 1% SATA_RXP1 SATA1RXN DD14 IDE_PDD15
AG4 SATA1RXP DD15 U6
TP_SATA_TXN1 AJ4
p
SATA1TXN IDE_PDA[2:0] 32
TP_SATA_TXP1 AJ3 AA4 IDE_PDA0
SATA
SATA1TXP DA0 IDE_PDA1
DA1 AA1
C286 3900pF SATA_RXN2_C AF2 AB3 IDE_PDA2
45 SATA_RXN2 SATA2RXN DA2
C287 3900pF SATA_RXP2_C AF1
45 SATA_RXP2 SATA2RXP
C289 3900pF SATA_TXN2_C AE4 Y6
o
45 SATA_TXN2 SATA2TXN DCS1# IDE_PDCS1# 32
C290 3900pF SATA_TXP2_C AE3 Y5
45 SATA_TXP2 SATA2TXP DCS3# IDE_PDCS3# 32
t
37 CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 IDE_PDIOR# 32
B 37 CLK_PCIE_SATA AC6 W3 IDE_PDIOW# 32
B
SATA_CLKP DIOW#
DDACK# Y2 IDE_PDDACK# 32
SATA_RBIAS_PN AG1 Y3
SATARBIAS# IDEIRQ INT_IRQ14 32
AG2 SATARBIAS IORDY Y1 IDE_PDIORDY 32
W5 +V3.3A_RTC 24
p
DDREQ IDE_PDDREQ 32
R409 ICH8M REV 1.0_OAKMONT
24.9
1%
R814
la
332K
1%
LAN100_SLP
.
+V3.3A 20,22..26,29,39..42,44..48,50,51,55..58
+V3.3A_RTC 24
w
R812
R394 332K
10K 1%
1%
ICH_INTVRMEN
w
ENRGY_DET_GPIO13 R804 0 DOCK_LAN_EN# 23,36,42
A A
NO_STUFF Oakmont Form Factor Reference Design Intel Confidential
w
Title
ICH8-M (1 of 4)

A
5 4 3 2 1
5 4 3 2 1
Layout note:
m
1. PCIE AC coupling caps need to be within
250 mils of the driver.
2. Place the strapping resistors/capacitors
without any stub
o
U40D
25 PCIE_RXN1 P27 PERN1 DMI0RXN V27 DMI_RXN0 7
25 PCIE_RXP1 P26 PERP1 DMI0RXP V26 DMI_RXP0 7
c
C294 0.1uF 10% PCIE_TXN1_C N29 U29 DMI_TXN0 7
Direct Media Interface

D 25 PCIE_TXN1 C295 0.1uF 10% PCIE_TXP1_C PETN1 DMI0TXN D
N28 PETP1 DMI0TXP U28 DMI_TXP0 7
25 PCIE_TXP1
.
25 PCIE_RXN2 M27 PERN2 DMI1RXN Y27
DMI_RXN1 7
25 PCIE_RXP2 M26 PERP2 DMI1RXP Y26 DMI_RXP1 7
C296 0.1uF 10% PCIE_TXN2_C L29 W29
25 PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 7
C297 0.1uF 10% PCIE_TXP2_C L28 W28
25 PCIE_TXP2 PETP2 DMI1TXP DMI_TXP1 7
s
K27 AB26
PCI-Express
26 PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 7
26 PCIE_RXP3 K26 PERP3 DMI2RXP AB25 DMI_RXP2 7
C741 0.1uF 10% PCIE_TXN3_C J29 AA29
26 PCIE_TXN3 PETN3 DMI2TXN DMI_TXN2 7
C743 0.1uF 10% PCIE_TXP3_C J28 AA28
26 PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 7
it c
45 PCIE_RXN4_DOCK H27 PERN4 DMI3RXN AD27
DMI_RXN3 7 +V1.5S_PCIE_ICH 21,24
45 PCIE_RXP4_DOCK H26 PERP4 DMI3RXP AD26 DMI_RXP3 7
C298 0.1uF 10% PCIE_TXN4_C G29 AC29
45 PCIE_TXN4_DOCK PETN4 DMI3TXN DMI_TXN3 7
C299 0.1uF 10% PCIE_TXP4_C G28 AC28
45 PCIE_TXP4_DOCK PETP4 DMI3TXP DMI_TXP3 7
45 PCIE_RXN5_DOCK F27 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# 37

F26 T25 R815
45 PCIE_RXP5_DOCK PERP5 DMI_CLKP CLK_PCIE_ICH 37 24.9 Place within 500
C745 0.1uF 10% PCIE_TXN5_C E29
45 PCIE_TXN5_DOCK C748 0.1uF 10% PCIE_TXP5_C PETN5 1% mils of ICH
E28 Y23
a
45 PCIE_TXP5_DOCK PETP5 DMI_ZCOMP DMI_IRCOMP_R
DMI_IRCOMP Y24
35 GLAN_RXN D27 PERN6/GLAN_RXN
35 GLAN_RXP D26 PERP6/GLAN_RXP USBP0N G3 USB_PN0 29
C749 0.1uF 10% PCIE_TXN6_C C29 G2
35 GLAN_TXN PETN6/GLAN_TXN USBP0P USB_PP0 29
C751 0.1uF 10% PCIE_TXP6_C C28 H5
35 GLAN_TXP PETP6/GLAN_TXP USBP1N USB_PN1 29
USBP1P H4 USB_PP1 29
R835 15 1% SPI_CLK_R C23 H2
36 SPI_CLK SPI_CLK USBP2N USB_PN2 26
R836 15 1% SPI_CS#0_R B23 H1
m
36 SPI_CS#0 SPI_CS0# USBP2P USB_PP2 26
R834 15 1% SPI_CS#1_R E22 J3
36 SPI_CS#1 SPI_CS1# USBP3N USB_PN3 29
J2 20,21,23..26,29,39..42,44..48,50,51,55..58 +V3.3A
SPI
USBP3P USB_PP3 29
36 SPI_SI D23 SPI_MOSI USBP4N K5 USB_PN4 29
C 36 SPI_SO F21 SPI_MISO USBP4P K4 USB_PP4 29 C
K2 USB_OC#0 R787 10K
e
USBP5N USB_PN5 25
AJ19 K1 USB_OC#1 R784 10K
29 USB_OC#0 OC0# USBP5P USB_PP5 25
AG16 L3 USB_OC#2 R783 10K
29 USB_OC#1 OC1#/GPIO40 USBP6N USB_PN6 25
USB_OC#2 AG15 L2 USB_OC#3 R378 10K
AE15
OC2#/GPIO41 USB USBP6P
M5
USB_PP6 25
USB_OC#4 R379 10K
29 USB_OC#3 OC3#/GPIO42 USBP7N USB_PN7 41
AF15 M4 USB_OC#5 R785 10K
29 USB_OC#4 USB_PP7 41
h
USB_OC#5 OC4#/GPIO43 USBP7P USB_OC#6 R781 10K
AG17 OC5#/GPIO29 USBP8N M2 USB_PN8 45
USB_OC#6 AD12 M1 USB_OC#7 R377 10K
OC6#/GPIO30 USBP8P USB_PP8 45
USB_OC#7 AJ18 N3 USB_OC#8 R782 10K
OC7#/GPIO31 USBP9N USB_PN9 26
AD14 N2 USB_OC#9 R786 10K
45 USB_OC#8 OC8# USBP9P USB_PP9 26
USB_OC#9 AH18
c
5,7,9,10,16..19,23..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S OC9#
USBRBIAS# F2
F3 USB_RBIAS_PN
USBRBIAS
C273 ICH8M REV 1.0_OAKMONT
s
0.1uF R820
5
U102 Place within 500 22.6

1 PLT_RST# mils of ICH 1%
-
18,42,44,45 BUF_PLT_RST# 4
2
R366 74AHC1G08
3
100K
Buffer to reduce
p
loading on
PLT_RST#
o
U40B
ICH8-M Pullups
33 PCI_AD[31:0]
t
PCI_AD0 D20 A4
B AD0 REQ0# PCI_REQ#0 33 B
PCI_AD1
PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ#1
PCI_GNT#0 33
5,7,9,10,16..19,23..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
PCI_AD3 AD2 REQ1#/GPIO50 TP_ICH_GNT1#
A20 AD3 GNT1#/GPIO51 C18
PCI_AD4 D17 B19 PCI_REQ#2 PCI_FRAME# R831 8.2K
AD4 REQ2#/GPIO52
p
PCI_AD5 A21 F18 TP_ICH_GNT2# PCI_IRDY# R844 8.2K
PCI_AD6 AD5 GNT2#/GPIO53 PCI_REQ#3 PCI_TRDY# R845 8.2K
A19 AD6 REQ3#/GPIO54 A11
PCI_AD7 C19 C10 TP_ICH_GNT3# PCI_STOP# R840 8.2K Place J19 at an easy to
PCI_AD8 AD7 GNT3#/GPIO55 PCI_SERR# R827 8.2K
A18 AD8 access location.
PCI_AD9 B16 C17 PCI_DEVSEL# R839 8.2K
AD9 C/BE0# PCI_CBE#0 33
PCI_AD10 PCI_PERR# R843 8.2K
la
A12 AD10 C/BE1# E15 PCI_CBE#1 33
PCI_AD11 E16 F16 PCI_LOCK# R823 8.2K J19
PCI_AD12 A14 E17 PCI_REQ#0 R822 8.2K PCI_GNT#0 1 2 PCI_GNT#0_R R224 1K
PCI_AD13 G16 PCI_REQ#1 R838 8.2K
PCI_AD14 AD13 PCI_REQ#2 R832 8.2K 1X2_2MM
A15 AD14 IRDY# C8 PCI_IRDY# 33 .
.
PCI_AD15 B6 D9 PCI_REQ#3 R828 8.2K Boot BIOS Strap
AD15 PAR PCI_PAR 33 PCI_GNT#0 SPI_CS#0 Boot BIOS Location
PCI_AD16 C11 G6
AD16 PCIRST# PCI_RST# 33,42
PCI_AD17 A9 D16 INT_PIRQA# R825 8.2K 0 X SPI
AD17 DEVSEL# PCI_DEVSEL# 33 1 0 PCI
PCI_AD18 D11 A7 INT_PIRQB# R841 8.2K
AD18 PERR# PCI_PERR# 33 1 1 LPC
PCI_AD19 B12 B7 INT_PIRQC# R842 8.2K
AD19 PLOCK# PCI_LOCK# 33
PCI_AD20 C12 F10 INT_PIRQD# R826 8.2K
AD20 SERR# PCI_SERR# 33
PCI_AD21 D10 C16 INT_PIRQE# R824 8.2K
w
AD21 STOP# PCI_STOP# 33
PCI_AD22 C7 C9 INT_PIRQF# R829 8.2K
AD22 TRDY# PCI_TRDY# 33
PCI_AD23 F13 A17 INT_PIRQG# R830 8.2K
AD23 FRAME# PCI_FRAME# 33
PCI_AD24 E11 PLT_RST# INT_PIRQH# R821 8.2K
PCI_AD25 AD24
E13 AD25 PLTRST# AG24 PLT_RST# 7,19,25,26,40,58
PCI_AD26 E12 B10
AD26 PCICLK CLK_PCIF_ICH 37
PCI_AD27 D8 G7
AD27 PME# PCI_PME# 33
PCI_AD28
w
A6 AD28
PCI_AD29 E8
PCI_AD30 AD29
D6 AD30
PCI_AD31 A3 AD31
A
Interrupt I/F Oakmont Form Factor Reference Design Intel Confidential A
F9 F8 INT_PIRQE#
33 INT_PIRQA# PIRQA# PIRQE#/GPIO2
w
INT_PIRQB#
INT_PIRQC#
B5
C5
PIRQB# PIRQF#/GPIO3 G11
F12
INT_PIRQF#
INT_PIRQG#
Title
PIRQC# PIRQG#/GPIO4
INT_PIRQD# A10 PIRQD# PIRQH#/GPIO5 B3 INT_PIRQH# ICH8-M (2 of 4)
ICH8M REV 1.0_OAKMONT
A
5 4 3 2 1
5 4 3 2 1
U40C 5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S

SMB_CLK AJ26 AJ12 SATA0GP R800 100
SMB_DATA SMBCLK SATA0GP/GPIO21 SATA1GP R398 100
AD19 SMBDATA SATA1GP/GPIO19 AJ10
AG21 AF11 SATA2GP R384 100
SATA
SMB
GPIO
25 CL_RST#1 LINKALERT# SATA2GP/GPIO36
AC17 AG11 SATA3GP R397 100
42 SMB_CLK_ME SMLINK0 SATA3GP/GPIO37 IDE_RST 32
13..15,24,35,36,42,45,50,56,57 +V3.3M AE19 No Reboot Strap
42 SMB_DATA_ME SMLINK1 Low = Default
AG9 R779
CLK14 CLK_REF_ICH 37 ACZ_SPKR High = No 1K
AF17 G5
Clocks
40 PM_RI# RI# CLK48 CLK_USB48 37 Reboot NO_STUFF
10K
o
F4 D3 TP_SUS_CL
40,42,44 PM_SUS_STAT# SUS_STAT#/LPCPD# SUSCLK
NO_STUFF
55 PM_SYSRST# AD15 SYS_RESET#
For CX entry/exit AG23 SLP_S3#_R R396 100
support stuff R383 and SLP_S3# PM_SLP_S3# 42,45,48,56..58
AG12 AF21 SLP_S4#_R R801 100 HDA_SPKR
no stuff R777. 7 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# PM_SLP_S4# 47,56
R773
c
AD18 TP_SLP_S5#
D SMB_ALERT# SLP_S5# D
AG22 SMBALERT#/GPIO11
AH27 PM_S4_STATE# 42,45,56,57
.
S4_STATE#/GPIO26
37 PM_STPPCI# AE20 STP_PCI#/GPIO15
R383 0 PM_STPCPU#_R AG18 AE23 PM_ICH_PWROK
37 PM_STPCPU# STP_CPU#/GPIO25 PWROK
.
Power MGT
AH11 AJ14 PM_DPRSLPVR_R R400 100
GPIO
33,40,42,44 PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR 7,52
SYS
25,26,45 PCIE_WAKE# AE17 WAKE# BATLOW# AE21 PM_BATLOW# 42
33,40,42,44 INT_SERIRQ AF12 SERIRQ
5,42 PM_THRM# AC13 THRM# PWRBTN# C2 PM_PWRBTN# 42
it c
+V3.3S 5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 VR_PWRGD_CLKEN AJ20 AH20 +V3.3M 13..15,24,35,36,42,45,50,56,57
VRMPWRGD LAN_RST# PM_LAN_ENABLE 35,42
TP_ICH_AJ22 AJ22 AG27 PM_RSMRST#_R R796 100
TP7 RSMRST# PM_RSMRST# 42
AJ8 E1 R415
40,42,45 SMC_EXTSMI# TACH1/GPIO1 CK_PWRGD CLK_PWRGD 37 3.24K
C275 BIOS_REC AJ9
0.1uF TACH2/GPIO6 1%
42 SMC_RUNTIME_SCI# AH9 TACH3/GPIO7 CLPWROK E3 MPWROK 7,47
10% 5 AE16
42 SMC_WAKE_SCI# GPIO8
Q97 ICH_GPIO12 AC19 AJ25
GPIO12 SLP_M# PM_SLP_M# 42,45,48,56,57
ICH_GPIO17 AG8
a
TACH0/GPIO17
1
2 4 TP_FWHTBL AH12 F23
52 VR_PWRGD_CLKEN# GPIO18 CL_CLK0 CL_CLK0 7
TP_ICH_GPIO20 AE11 AE18 C306 R413
GPIO
CL_CLK1 25
Controller Link
TP_FWHWP GPIO20 CL_CLK1 0.1uF 453_1%
AG10 SCLOCK/GPIO22
100K
INVERTER ICH_GPIO27 AH25 F22 10%

3 QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 7
TP_SATA_PWR_EN#1 AD16 AF19 CL_DATA1 25
2
QRT_STATE1/GPIO28 CL_DATA1
37 CLK_SATA_OE# AG13 SATACLKREQ#/GPIO35
AF9 D24 CL_VREF0_ICH
32 IDE_PATADET SLOAD/GPIO38 CL_VREF0
ICH_GPIO39 AJ11 AH23 CL_VREF1_ICH
m
SDATAOUT0/GPIO39 CL_VREF1
R380
MFG_MODE AD10 SDATAOUT1/GPIO48 +V3.3A 20..22,24..26,29,39..42,44..48,50,51,55..58

CL_RST# AJ23 CL_RST#0 7
28,45 HDA_SPKR AD9 SPKR
C AJ27 CRB_SV_DET_R C
CLGPIO0/GPIO24 R803
AJ13 AJ24
MISC
e
7 MCH_ICH_SYNC# MCH_SYNC# ALERT#/GPIO10 ME_SMC_ALERT# 42 3.24K
NETDETECT/GPIO14 AF22 SMC_ME_ALERT 42,55 1%
TP_ICH_AJ21 AJ21 AG19
TP3 CLGPIO3/GPIO9 LAN_WOL_EN 42,56,57
ICH8M REV 1.0_OAKMONT R809
+V3.3S 5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 100K
1
+V3.3A 20..22,24..26,29,39..42,44..48,50,51,55..58 C282 R395
0.1uF 453_1%
R349 10K SMB_CLK_A1 10%
R780 R350 10K SMB_DATA_A1
2
10K LO Note:
1% +V3.3M 13..15,24,35,36,42,45,50,56,57
Place R706 & R705
R702 10K SMB_CLK_M3 (SMBUS pullups) in
-s
BIOS_REC R701 10K SMB_DATA_M3
externally accessible
R351 10K SMB_CLK_M2 location (for adaptive
R356 10K SMB_DATA_M2 clocking)
5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
R790 10K SMB_CLK_S4 ICH8-M Pullups

R357 10K SMB_DATA_S4
p
20..22,24..26,29,39..42,44..48,50,51,55..58 +V3.3A
PM_RI# R385 10K

+V3.3S 5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 SMB_CLK_ME R387 10K
o
SMB_DATA_ME R386 10K
20..22,24..26,29,39..42,44..48,50,51,55..58 +V3.3A SMB_CLK R393 2.2K
t
B
SMB_DATA R399 2.2K B
R808 100 CRB_SV_DET_R +V3.3M 13..15,24,35,36,42,45,50,56,57 SMB_ALERT# R365 10K
PCIE_WAKE# R807 1K
+V3.3A 20..22,24..26,29,39..42,44..48,50,51,55..58 PM_BATLOW# R802 8.2K
C276
U101
p
0.1uF
R347 10K CL1 1 20 CL_RST#1 R404 10K
R348 10K CL2 EXPSCL1 VCC NO_STUFF
2 EXPSCL2
R375 10K DA1 18 5
EXPSDA1 SCL1 SMB_CLK_A1 25,26,45
+V3.3A 20..22,24..26,29,39..42,44..48,50,51,55..58 R381 10K DA2 19 6
EXPSDA2 SDA1 SMB_DATA_A1 25,26,45
la
Adaptive
SMB_CLK 3 8
SMB_DATA 4
SCL0 SCL2
9
SMB_CLK_M2 13..15 Clocking 5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
SDA0 SDA2 SMB_DATA_M2 13..15
R403
10K R363 10K I2C_EN1 7 12 SMB_CLK_M3_R R791 0
EN1 SCL3 SMB_CLK_M3 37,38
.
R364 10K I2C_EN2 11 13 SMB_DATA_M3_R R792 0 CLK_SATA_OE# R810 10K
EN2 SDA3 SMB_DATA_M3 37,38
R794 10K I2C_EN3 14
MFG_MODE R361 10K I2C_EN4 EN3 SMB_CLK_S4 PM_THRM# R806 8.2K
17 EN4 SCL4 15
10 16 SMB_DATA_S4
VSS SDA4 R405 10K
EXP. 5-CH-I2C HUB 21,42 H_RCIN#
INT_SERIRQ R390 10K
w
+V3.3A 20..22,24..26,29,39..42,44..48,50,51,55..58 PM_CLKRUN# R799 8.2K
+V3.3A 20..22,24..26,29,39..42,44..48,50,51,55..58
ICH_GPIO39 R406 10K
C706 +V3.3S 5,7,9,10,16..19,22,24..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 ALL_SYS_PWRGD R768 10K
0.1uF PM_RSMRST# R391 10K
10%
w
R358 R360 R359
2K 10K 10K
A 1% A
5
U60
w
1 ICH_GPIO27 R805 0
ALL_SYS_PWRGD 42,48 DOCK_LAN_EN# 21,36,42
PM_ICH_PWROK 4
2
Title
DELAY_VR_PWRGOOD 7,52
R777 74AHC1G08 ICH_GPIO12 R764 0
ICH8-M (3 of 4)
LAN_PHYPC 35
3
10K NO_STUFF

A
5 4 3 2 1
5 4 3 2 1
+V3.3A_RTC 21
5,7,9,10,16..19,22,23,25,26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S Layout Note:
Place CAPS within 100 mils of ICH on the bottom side or 140 mils on the top side.
U40E
m
C726 C724 3,4,6,9,10,20,21,45,48,54,56 +V1.05S A23 K7
5,16..18,26,28,30..32,34,49,50,52,53,56,57 +V5S 0.1uF 0.1uF VSS[001] VSS[099]
A5 VSS[002] VSS[100] L1
1 10% 10% U40F AA2 L13
VSS[003] VSS[101]
AD25 VCCRTC VCC1_05[01] A13 AA7 VSS[004] VSS[102] L15
Q48 B13 A25 L26
o
VCC1_05[02] VSS[005] VSS[103]
1
R837 BAT54 A16 C13 Customer + C738 C731 C740 AB1 L27
100 V5REF[1] VCC1_05[03] recommendation 220uF 0.1uF 0.1uF VSS[006] VSS[104]
T7 V5REF[2] VCC1_05[04] C14 10% AB24 VSS[007] VSS[105] L4
D14 10% 10% AC11 L5
2
+V5A 29,42,46..48,51,57 3 V5REF_SUS VCC1_05[05] VSS[008] VSS[106]
G4 V5REF_SUS VCC1_05[06] E14 AC14 VSS[009] VSS[107] M12
c
VCC1_05[07] F14 AC25 VSS[010] VSS[108] M13
AA25 VCC1_5_B[01] VCC1_05[08] G14 AC26 VSS[011] VSS[109] M14
D AA26 VCC1_5_B[02] VCC1_05[09] L11 AC27 VSS[012] VSS[110] M15 D
.
ICH8_V5REF1_V5REF2 AA27 L12 4,10,18,25,26,48,56 +V1.5S AD17 M16
VCC1_5_B[03] VCC1_05[10] L23 VSS[013] VSS[111]
AB27 VCC1_5_B[04] VCC1_05[11] L14 AD20 VSS[014] VSS[112] M17
20..23,25,26,29,39..42,44..48,50,51,55..58 +V3.3A C756 AB28 L16 VCCDMIPLL_ICH 1 2 GPLL_R R817 1 AD28 M23
0.1uF VCC1_5_B[05] VCC1_05[12] 1uH VSS[015] VSS[113]
1 AB29 VCC1_5_B[06] VCC1_05[13] L17 AD29 VSS[016] VSS[114] M28
10% D28 L18 C737 C293 AD3 M29
s
R818 VCC1_5_B[07] VCC1_05[14] 0.01uF 10uF VSS[017] VSS[115]
D29 M11 AD4 M3
CORE
10 Q47 VCC1_5_B[08] VCC1_05[15] 10% VSS[018] VSS[116]
E25 VCC1_5_B[09] VCC1_05[16] M18 AD6 VSS[019] VSS[117] N1
BAT54 E26 P11 402 AE1 N11
VCC1_5_B[10] VCC1_05[17] VSS[020] VSS[118]
E27 VCC1_5_B[11] VCC1_05[18] P18 AE12 VSS[021] VSS[119] N12
3
it c
F24 VCC1_5_B[12] VCC1_05[19] T11 AE2 VSS[022] VSS[120] N13
F25 T18 10,56,57 +V1.25S AE22 N14
C744 VCC1_5_B[13] VCC1_05[20] VSS[023] VSS[121]
G24 VCC1_5_B[14] VCC1_05[21] U11 AD1 VSS[024] VSS[122] N15
0.1uF H23 U18 AE25 N16
10% 10V VCC1_5_B[15] VCC1_05[22] VSS[025] VSS[123]
H24 VCC1_5_B[16] VCC1_05[23] V11 AE5 VSS[026] VSS[124] N17
1
SMC0402 J23 V12 C288 + C715 Customer AE6 N18
VCC1_5_B[17] VCC1_05[24] 22uF 220uF recommendation +V1.05S 3,4,6,9,10,20,21,45,48,54,56 VSS[027] VSS[125]
J24 VCC1_5_B[18] VCC1_05[25] V14 10% AE9 VSS[028] VSS[126] N26
K24 V16 AF14 N27
2
4,10,18,25,26,48,56 +V1.5S VCC1_5_B[19] VCC1_05[26] VSS[029] VSS[127]
K25 VCC1_5_B[20] VCC1_05[27] V17 AF16 VSS[030] VSS[128] N4
L23 VCC1_5_B[21] VCC1_05[28] V18 AF18 VSS[031] VSS[129] N5
a
L24 C718 C727 C733 AF3 N6
VCC1_5_B[22] VSS[032] VSS[130]
VCCA3GP
21,22 +V1.5S_PCIE_ICH L25 R29 0.1uF 0.1uF 4.7uF AF4 P12
VCC1_5_B[23] VCCDMIPLL 10% 10% 10% VSS[033] VSS[131]
M24 VCC1_5_B[24] AG5 VSS[034] VSS[132] P13
FB22 M25 AE28 AG6 P14
330ohm@100MHz VCC1_5_B[25] VCC_DMI[1] VSS[035] VSS[133]
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AH10 VSS[036] VSS[134] P15
C735 C300 C292 C739 N24 AH13 P16
220uF 22uF 22uF 2.2uF VCC1_5_B[27] VSS[037] VSS[135]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH16 VSS[038] VSS[136] P17
10% P24 AC24 5,7,9,10,16..19,22,23,25,26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S AH19 P23
m
VCC1_5_B[29] V_CPU_IO[2] VSS[039] VSS[137]
P25 VCC1_5_B[30] AH2 VSS[040] VSS[138] P28
R24 VCC1_5_B[31] VCC3_3[01] AF29 AF28 VSS[041] VSS[139] P29
+V1.5S_APLL_ICH_R
R25 C716 AH22 R11

VCC1_5_B[32] 0.1uF VSS[042] VSS[140]
R26 VCC1_5_B[33] VCC3_3[02] AD2 AH24 VSS[043] VSS[141] R12
C R27 VCC1_5_B[34]
10% AH26 VSS[044] VSS[142] R13 C
e
4,10,18,25,26,48,56 +V1.5S T23 AC8 C720 AH3 R14
VCC1_5_B[35] VCC3_3[03] 0.1uF VSS[045] VSS[143]
T24 AD8 AH4 R15
VCCP_CORE
VCC1_5_B[36] VCC3_3[04] 10% VSS[046] VSS[144]
T27 VCC1_5_B[37] VCC3_3[05] AE8 AH8 VSS[047] VSS[145] R16
T28 VCC1_5_B[38] VCC3_3[06] AF8 AJ5 VSS[048] VSS[146] R17
L15 T29 B11 R18
VCC1_5_B[39] VSS[049] VSS[147]
h
R797 0 V1.5S_APLL_ICH U24 AA3 B14 R28
10uH VCC1_5_B[40] VCC3_3[07] VSS[050] VSS[148]
U25 VCC1_5_B[41] VCC3_3[08] U7 B17 VSS[051] VSS[149] R4
C711 C283 V23 V7 C732 B2 T12
10uF 1uF VCC1_5_B[42] VCC3_3[09] 0.1uF VSS[052] VSS[150]
V24 VCC1_5_B[43] VCC3_3[10] W1 B20 VSS[053] VSS[151] T13
V25 W6 10% B22 T14
IDE
c
VCC1_5_B[44] VCC3_3[11] VSS[054] VSS[152]
W25 VCC1_5_B[45] VCC3_3[12] W7 B8 VSS[055] VSS[153] T15
Y25 VCC1_5_B[46] VCC3_3[13] Y7 C24 VSS[056] VSS[154] T16
C26 VSS[057] VSS[155] T17
AJ6 VCCSATAPLL VCC3_3[14] A8 C27 VSS[058] VSS[156] T2
s
VCC3_3[15] B15 C6 VSS[059] VSS[157] U12
AE7 B18 C750 C755 C752 D12 U13
VCC1_5_A[01] VCC3_3[16] 0.1uF 0.1uF 0.1uF Layout Note: Distribute in PCI section VSS[060] VSS[158]
AF7 VCC1_5_A[02] VCC3_3[17] B4 D15 VSS[061] VSS[159] U14
ARX
C291 10% 10% 10%
-
AG7 VCC1_5_A[03] VCC3_3[18] B9 D18 VSS[062] VSS[160] U15
1UF AH7 C15 D2 U16
VCC1_5_A[04] VCC3_3[19] VSS[063] VSS[161]
AJ7 D13 D4 U17
PCI
VCC1_5_A[05] VCC3_3[20] VSS[064] VSS[162]

VCC3_3[21] D5 E21 VSS[065] VSS[163] U23
AC1 VCC1_5_A[06] VCC3_3[22] E10 E24 VSS[066] VSS[164] U26
AC2 E7 5,7,9,10,16..19,22,23,25,26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S E4 U27
p
VCC1_5_A[07] VCC3_3[23] VSS[067] VSS[165]
ATX
C712 AC3 F11 E9 U3

1UF VCC1_5_A[08] VCC3_3[24] VSS[068] VSS[166]
AC4 VCC1_5_A[09] F15 VSS[069] VSS[167] U5
AC5 AC12 +V3.3A 20..23,25,26,29,39..42,44..48,50,51,55..58 C723 E23 V13
VCC1_5_A[10] VCCHDA 0.1uF VSS[070] VSS[168]
F28 VSS[071] VSS[169] V15
AC10 AD11 10% F29 V28
o
VCC1_5_A[11] VCCSUSHDA VSS[072] VSS[170]
AC9 VCC1_5_A[12] F7 VSS[073] VSS[171] V29
J6 TP_VCCSUS1_05_INT_ICH_1 C722 G1 W2
VCCSUS1_05[1] VSS[074] VSS[172]
t
AA5 AF20 TP_VCCSUS1_05_INT_ICH_2 0.1uF E2 W26
B VCC1_5_A[13] VCCSUS1_05[2] 10% VSS[075] VSS[173] B
AA6 VCC1_5_A[14] G10 VSS[076] VSS[174] W27
AC16 TP_VCCSUS1_5_ICH_1 G13 Y28
VCCSUS1_5[1] VSS[077] VSS[175]
G12 VCC1_5_A[15] G19 VSS[078] VSS[176] Y29
G17 J7 TP_VCCSUS1_5_ICH_2 +V3.3A 20..23,25,26,29,39..42,44..48,50,51,55..58 G23 Y4
C728 VCC1_5_A[16] VCCSUS1_5[2] VSS[079] VSS[177]
p
H7 VCC1_5_A[17] G25 VSS[080] VSS[178] AB4
0.1uF C3 G26 AB23
10% VCCSUS3_3[01] VSS[081] VSS[179]
AC7 VCC1_5_A[18] G27 VSS[082] VSS[180] AB5
AD7 AC18 C725 C736 H25 AB6
VCC1_5_A[19] VCCSUS3_3[02] 0.1uF 0.1uF VSS[083] VSS[181]
VCCSUS3_3[03] AC21 H28 VSS[084] VSS[182] AD5
D1 AC22 10% 10% H29 U4
la
VCCPSUS
VCCUSBPLL VCCSUS3_3[04] VSS[085] VSS[183]

VCCSUS3_3[05] AG20 H3 VSS[086] VSS[184] W24
F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 H6 VSS[087]
USB CORE
C746 L6 J1 A1
0.1uF VCC1_5_A[21] VSS[088] VSS_NCTF[01]
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 J25 VSS[089] VSS_NCTF[02] A2
.
+V3.3M 13..15,23,35,36,42,45,50,56,57 10% M6 P7 J26 A28
4,10,18,25,26,48,56 +V1.5S VCC1_5_A[23] VCCSUS3_3[08] C734 VSS[090] VSS_NCTF[03]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 J27 VSS[091] VSS_NCTF[04] A29
N7 4.7uF J4 AH1
VCCSUS3_3[10] VSS[092] VSS_NCTF[05]
W23 VCC1_5_A[25] VCCSUS3_3[11] P1 J5 VSS[093] VSS_NCTF[06] AH29
VCCSUS3_3[12] P2 K23 VSS[094] VSS_NCTF[07] AJ1
C742 TP_VCCLAN1_05_ICH_1 F17 P3 K28 AJ2
VCCPUSB
0.1uF TP_VCCLAN1_05_ICH_2 VCCLAN1_05[1] VCCSUS3_3[13] VSS[095] VSS_NCTF[08]

G18 P4 K29 AJ28
w
10% VCCLAN1_05[2] VCCSUS3_3[14] VSS[096] VSS_NCTF[09]
VCCSUS3_3[15] P5 K3 VSS[097] VSS_NCTF[10] AJ29
+V1.5S 4,10,18,25,26,48,56 F19 R1 K6 B1
VCCLAN3_3[1] VCCSUS3_3[16] VSS[098] VSS_NCTF[11]
G20 VCCLAN3_3[2] VCCSUS3_3[17] R3 VSS_NCTF[12] B29
L24 R5
R414 1 GLANPLL_R GLANPLL VCCSUS3_3[18] ICH8M REV 1.0_OAKMONT
1 2 A24 VCCGLANPLL VCCSUS3_3[19] R6
1uH
GLAN POWER
C757 C305 A26 G22 TP_VCCCL1_05_ICH
w
10uF 2.2uF VCCGLAN1_5[1] VCCCL1_05
A27 VCCGLAN1_5[2]
10% B26 A22 VCCCL1_5_INT_ICH
VCCGLAN1_5[3] VCCCL1_5
B27 VCCGLAN1_5[4]
B28 F20 C304 C303
A VCCGLAN1_5[5] VCCCL3_3[1] A
B25
VCCCL3_3[2] G21 1UF 0.1uF
10% Oakmont Form Factor Reference Design Intel Confidential
VCCGLAN3_3
w
+V1.5S_PCIE_ICH 21,22 NO_STUFF NO_STUFF
ICH8M REV 1.0_OAKMONT Title
C307 ICH8-M (4 of 4)
4.7uF 13..15,23,35,36,42,45,50,56,57 +V3.3M
10%
+V3.3S 5,7,9,10,16..19,22,23,25,26,28,30,32..34,38,40,42,44,45,49,50,52,55..58 A
5 4 3 2 1
5 4 3 2 1
+V3.3A 20..24,26,29,39..42,44..48,50,51,55..58
C139 C617
Kedron/Clink supported
m
C622
22UF
0.1uF 0.1uF on Minicard 1
10% 10%
o
+V1.5S 4,10,18,24,26,48,56
C616 C166
Minicard 2
c
C619 0.1uF 0.1uF
D J39 22UF 10% 10% D
.
1 WAKE# +3.3V_1 2
23,26,45 PCIE_WAKE#
41 CHANNEL_DATA 3 RSVD1 GND7 4
41 BT_PRI_CLK 5 RSVD2 +1.5V_1 6
38 CLK_MINICARD2_OE# 7 8 TP_MC2_RSVD13 1
CLKREQ# RSVD13 TP_MC2_RSVD14 J38 Place these TPs
9 10 1
s
GND1 RSVD14 TP_MC2_RSVD15 J37 externally
38 CLK_PCIE_MINICARD2# 11 REFCLK- RSVD15 12 1
13 14 TP_MC2_RSVD16 1 J36 accessible near
38 CLK_PCIE_MINICARD2 REFCLK+ RSVD16 MiniCard 2
15 16 TP_MC2_RSVD17 1 J35
GND2 RSVD17 J34
it c
KEY NO_STUFF
17 RSVD3 GND8 18
19 20 +V3.3_PCIE_VAUX 57
RSVD4 RSVD18 RF_KILL# 42,58
21 GND3 PERST# 22 PLT_RST# 7,19,22,26,40,58
23 PER_N0 +3.3V_AUX 24
22 PCIE_RXN1
25 PER_P0 GND9 26
22 PCIE_RXP1 C165
27 GND4 +1.5V_2 28
29 30 C163 0.1uF
GND5 SMB_CLK SMB_CLK_A1 23,26,45 22UF
31 32 10%
22 PCIE_TXN1 PET_N0 SMB_DATA SMB_DATA_A1 23,26,45
22 PCIE_TXP1 33 PET_P0 GND10 34
a
35 GND6 USB_D- 36 USB_PN5 22
37 RSVD5 USB_D+ 38 USB_PP5 22
39 RSVD6 GND11 40
41 RSVD7 LED_WWAN# 42 WWAN_GPIO 58
43 RSVD8 LED_WLAN# 44 WLAN_GPIO 57,58
45 46 J33
RSVD9 LED_WPAN#
47 RSVD10 +1.5V_3 48 1 MT1 MT4 4
49 50 2 LATCH 5
m
RSVD11 GND12 MT2 (GND ALL) MT5
51 RSVD12 +3.3V_2 52 3 MT3
55 GNDM1 GNDM2 56
MINI_CARD_LATCH_ TYCO
PCI-e_MINI_CARD
C C
h e
+V3.3S 5,7,9,10,16..19,22..24,26,28,30,32..34,38,40,42,44,45,49,50,52,55..58
20..24,26,29,39..42,44..48,50,51,55..58 +V3.3A For Mini-card Spec 1.0 Stuff

R139 & R171 and NO_STUFF
c
R138 & R169. Default is
Mini-card Spec 1.1
R138 0 V3.3A_MINI2
s
C35 C57
R139 0 C68 0.1uF 0.1uF
NO_STUFF 22UF 10% 10%
-
R169 R171 Place R138,
0 0 R139, R169 &
NO_STUFF R171 so they +V1.5S 4,10,18,24,26,48,56
are easy to
V3.3A_MINI1 rework.
p
Minicard 1
J32 C56 C52 C82
1 2 22UF 0.1uF 0.1uF
23,26,45 PCIE_WAKE# WAKE# +3.3V_1 10% 10%
3 4
o
41 CHANNEL_DATA RSVD1 GND7
41 BT_PRI_CLK 5 RSVD2 +1.5V_1 6
38 CLK_MINICARD1_OE# 7 CLKREQ# RSVD13 8
t
9 GND1 RSVD14 10
B 38 CLK_PCIE_MINICARD1# 11 12 +V3.3A 20..24,26,29,39..42,44..48,50,51,55..58 B
REFCLK- RSVD15
38 CLK_PCIE_MINICARD1 13 REFCLK+ RSVD16 14
15 GND2 RSVD17 16
R638
KEY 10K
p
17 RSVD3 GND8 18
19 RSVD4 RSVD18 20 RF_KILL# 42,58
21 22 +V3.3A 20..24,26,29,39..42,44..48,50,51,55..58
GND3 PERST# PLT_RST# 7,19,22,26,40,58
23 PER_N0 +3.3V_AUX 24
22 PCIE_RXN2
25 26
la
22 PCIE_RXP2 PER_P0 GND9 C46
27 GND4 +1.5V_2 28
29 30 C45 0.1uF
GND5 SMB_CLK SMB_CLK_A1 23,26,45 22UF
31 32 10%
22 PCIE_TXN2 PET_N0 SMB_DATA SMB_DATA_A1 23,26,45
22 PCIE_TXP2 33 PET_P0 GND10 34
.
35 GND6 USB_D- 36 USB_PN6 22
37 RSVD5 USB_D+ 38 USB_PP6 22
39 RSVD6 GND11 40
41 RSVD7 LED_WWAN# 42 WWAN_GPIO 58
43 44 J40
RSVD8 LED_WLAN# WLAN_GPIO 57,58
23 CL_CLK1 45 RSVD9 LED_WPAN# 46 1 MT1 MT4 4
47 48 2 LATCH 5
23 CL_DATA1
w
RSVD10 +1.5V_3 MT2 (GND ALL) MT5
23 CL_RST#1 49 RSVD11 GND12 50 3 MT3
51 RSVD12 +3.3V_2 52
55 56 MINI_CARD_LATCH_ TYCO
GNDM1 GNDM2
PCI-e_MINI_CARD
w
Title
w
Mini-Card
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
5,16..18,24,28,30..32,34,49,50,52,53,56,57 +V5S
it c
5,7,9,10,16..19,22..25,28,30,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S
J29
60 60 59 59
58 58 57 57
4,10,18,24,25,48,56 +V1.5S 56 55
56 55
54 54 53 53
52 52 51 51 SMC_LID 42,58
a
50 50 49 49
48 48 47 47 PLT_RST# 7,19,22,25,40,58
46 46 45 45
20..25,29,39..42,44..48,50,51,55..58 +V3.3A 44 43
44 43 AZ_SPEAKER_L 28
42 42 41 41 AZ_SPEAKER_R 28
40 40 39 39
38 38 37 37 AZ_MUTE 28
36 35
m
36 35
34 34 33 33 USB_PN9 22
32 32 31 31 USB_PP9 22
30 30 29 29
37 CLK_EXPCARD_OE#
28 28 27 27 USB_PN2 22
C 26 26 25 25 USB_PP2 22
C
e
23,25,45 PCIE_WAKE#
24 24 23 23
22 PCIE_TXP3 22 22 21 21 ND_SW# 55
22 PCIE_TXN3 20 20 19 19
18 18 17 17 NETDETECT_LED 57
16 16 15 15 S3_LED 58
22 PCIE_RXP3
h
14 14 13 13 LED_BATT_FULL 58
22 PCIE_RXN3
12 12 11 11 LED_BATT_LOW 58
37 CLK_PCIE_EXPCARD1 10 10 9 9
37 CLK_PCIE_EXPCARD1# 8 8 7 7 IR_RXD 40
6 5
c
6 5 IR_MODE 40
23,25,45 SMB_DATA_A1 4 4 3 3 IRDA_CIR_SLT 40
23,25,45 SMB_CLK_A1 2 2 1 1 IR_TXD 40
s
MECH_1 61
MECH_2 62
-
CONN60_0_635MM_SMT_RECPT
o p
t
B B
la p
w .
w
A A
w
Title
Sky Forest Connector
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
m
MODEM MDC 1.5 CONNECTOR
42,45,49,56..58 +V3.3
J24
C 1 2 C
1 2
e
R710 33 HDA_SDOUT_MDC 3 4
18,21,28,45 HDA_SDOUT 3 4
5 5 6 6
R712 33 HDA_SYNC_MDC 7 8
18,21,28,45 HDA_SYNC 7 8
21 HDA_SDIN1 9 9 10 10
R717 33 HDA_RST#_MDC 11 12 HDA_BIT_CLK_MDC R718 33
h
18,21,28 HDA_RST# 11 12 HDA_BIT_CLK 18,21,28,45
MDC1.5_SOCKET
s c
p -
t o
B B
la p
w .
w
A Intel Confidential A
Oakmont Form Factor Reference Design
w
Title
Modem Connector

A
5 4 3 2 1
5 4 3 2 1
HDA_SD INPUT DEVICE
m
HDA_SDIN0 AUDIO
HDA_SDIN1 MODEM
o
HDA_SDIN2 HDMI
c
HDA_SDIN3 DOCKING
D D
.
Place C229, C250, C657, C644 close to U57
Place R701 and R703 close to pin 13
s
Width of IO pins (pins on the right of symbol) should be at least 10 mils with 10 mils spacing
GND reference analog signals to analog ground
NO signal should cross analog and digital ground bridge
it c
+V3.3S 5,7,9,10,16..19,22..26,30,32..34,38,40,42,44,45,49,50,52,55..58
C226 10uF
+V5S 5,16..18,24,26,30..32,34,49,50,52,53,56,57
U94 J17 Headset
R245 2.2K R10519 10K AZ_SENSEA_JACKA 5 GREEN
C247 AZ_VREF_C
27 37 R243 2.2K 1% 4
VREF LINE1-VREFO-R
a
10uF AGND 29 AZ_LINE1_VREF_R 1 2 AZ_JACKA_R_FB 3
LINE1-VREF0-L AZ_LINE1-R_C C6201 AZ_LINE1-R_JACK
1 24 2 220uF FB15 600Ohm@100MHz
+
DVDD1 LINE1-R AZ_LINE1-L_C 10% C2029 1
9 23 2 220uF AZ_LINE1-L_JACK 6
+
DVDD2 LINE1-L 10% AZ_JACKA_L_FB
4 DVSS1 1 2 2
7 46 R255 2.2K FB16 600Ohm@100MHz 1
C656 C643 DVSS2 LINE2-VREFO-R AZ_LINE2_VREF_R R10520 2.2K JA9333L-WL1M9
LINE2-VREFO 31
10uF 10uF 25 15 AZ_LINE2-R_C
C652 1 2 220uF AZ_LINE2-R_JACK
+
AVDD1 LINE2-R AZ_LINE2-L_C 10%
38 14 1 2 220uF AZ_LINE2-L_JACK AGND J22
+
m
AVDD2 LINE2-L C662 10% R703 39.2K AZ_SENSEB_JACKB PINK
26 AVSS1 5
42 32 1% 4 Microphone
AVSS2 MIC1-VREFO-R
47K
47K
47K
47K
28 MIC1_VREF_R R244 2.2K 1 2 AZ_JACKB_R_FB 3
R709 33 AZ_RESET#_R MIC1-VREFO-L NO_STUFF FB18 600Ohm@100MHz
18,21,27 HDA_RST# 11 RESET# MIC1-R 22
C 18,21,27,45 HDA_BIT_CLK
R706 33 AZ_BIT-CLK_R 6 BIT-CLK MIC1-L 21 6 C
e
AGND 18,21,27,45 HDA_SYNC R708 33 AZ_SYNC_R 10 1 2 AZ_JACKB_L_FB 2
SYNC
R246
R256
R210
R238
R705 33 AZ_SDATA-OUT_R 5 45 FB19 600Ohm@100MHz 1
18,21,27,45 HDA_SDOUT SDATA-OUT MIC2-VREFO-R
R707 33 AZ_SDATA-IN_R 8 30 JA9333L-WP1M9
21 HDA_SDIN0 SDATA-IN MIC2-VREFO-L
MIC2-R 17
C670 1.0uF AZ_PCBEEP_C 12 16
PCBEEP MIC2-L AZ_JACKA_R_FB
h
10% 18 AGND
32 CD_L CD-L
20 39 AZ_JACKA_L_FB
32 CD_R CD-R SURR-OUT-L
32 CD_GND 19 CD-GND SURR-OUT-R 41 AGND
CEN-OUT 43
13 44 C230
c
SENSE A LFE-OUT C206 C215 470pF C239
34 SENSE-B MIC_CHASSIS 58
33 35 470pF 470pF 5% 470pF
DCVOL FRONT-OUT-L AZ_SPEAKER_L 26
40 36 5% 5% 5%
JDREF FRONT-OUT-R AZ_SPEAKER_R 26
26 AZ_MUTE
s
AZ_JDREF_C
2 GPIO-0 SPDIFI/EAPD 47
R713 10K HDA_SPKR_R 3 GPIO-1 48
23,45 HDA_SPKR SPDIFO
1% R704
1K
-
1%
1K
1%
Azalia_Codec_ALC882
AGND
C663 AZ_SENSEB
100pF
R714
AZ_SENSEA
o p
R250
20K
t
1%
B B
Tied at one point only under the
AGND
codec or near the codec
p
C237 0.1uF
10%
FB17 120ohm@100MHz
la
FB21 120ohm@100MHz
FB14 120ohm@100MHz
.
FB20 120ohm@100MHz
AGND
ww Oakmont Form Factor Reference Design

Title
Intel Confidential A
w
High Definition Audio

A
5 4 3 2 1
5 4 3 2 1
All OC#X Pull-ups Locate Near ICH8-M
o m
c
D D
s.
it c
24,42,46..48,51,57 +V5A U89
USB_OC#0 22
1 GND OC1# 8
2 7 USBA_VCC FB32 50OHM
C609 IN OUT1 USBB_VCC FB31 50OHM
3 EN1 OUT2 6
0.1uF R662 1K EN1A 4 5
EN2 OC2# USB_OC#1 22
10%
TPS2052
1
a
C562 + C582 C561 + C583
470PF 220uF 470PF 220uF J13
10% 10% USBA VCC_FB 1
2
USBA- VCC1 TOP
2 P#0 PORT
USBA+ 3 P0
L7 4 GND1 Mech1 9
1 4 USBB VCC_FB 5 10
22 USB_PN0 VCC2 BOTTOM Mech2
m
USBB- 6
USBB+ P#1 PORT
22 USB_PP0 2 3 7 P1
8 GND2
90_100MHz U31
B1 A2 +V3.3A 20..26,39..42,44..48,50,51,55..58 USB-PORTS
ESD_CH2 ESD_CH1
e
C A1 B2 C
V- V+
CM1230_02
L8
h
22 USB_PN1 1 4
22 USB_PP1 2 3
U33
90_100MHz B1 A2 +V3.3A 20..26,39..42,44..48,50,51,55..58
ESD_CH2 ESD_CH1
c
A1 V- V+ B2
CM1230_02
-s
24,42,46..48,51,57 +V5A U54
USB_OC#4 22
1 GND OC1# 8
2 7 USBC_VCC FB34 50OHM
C678 IN OUT1 USBD_VCC FB33 50OHM
3 EN1 OUT2 6
p
0.1uF R715 1K EN1B 4 5
EN2 OC2# USB_OC#3 22
10%
TPS2052
1
C248 + C242 C255 + C258
470PF 220uF 470PF 220uF J25
10% 10% USBC VCC_FB 1
o
2
2
USBC- VCC1 TOP
2 P#0 PORT
USBC+ 3 P0
t
L21 4 GND1 Mech1 9
1 4 USBD VCC_FB 5 10
B 22 USB_PN4 VCC2 BOTTOM Mech2 B
USBD- 6
USBD+ P#1 PORT
22 USB_PP4 2 3 7 P1
8 GND2
p
90_100MHz U99
B1 A2 +V3.3A 20..26,39..42,44..48,50,51,55..58 USB-PORTS
ESD_CH2 ESD_CH1
A1 V- V+ B2
CM1230_02
la
L22
22 USB_PN3 1 4
2 3
.
22 USB_PP3
U100
90_100MHz B1 A2 +V3.3A 20..26,39..42,44..48,50,51,55..58
ESD_CH2 ESD_CH1
A1 V- V+ B2
CM1230_02
ww A
w
Title
USB 2.0
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
m
21 SATA_TXP0
21 SATA_TXN0
21 SATA_RXN0 SATA Port 0, Direct Connect
21 SATA_RXP0 12 Volt drives not supported.
e
C J28 C
5,7,9,10,16..19,22..26,28,32..34,38,40,42,44,45,49,50,52,55..58 +V3.3S 2 1
TX GND_2m_S_1
3 TX# GND_2m_S_4 4
5 RX# GND_2m_S_7 7
6 RX
h
C754 8 11
0.1uF C753 V_3.3_1 GND_1m_P_4
9 V_3.3_2 GND_2m_P_5 12
10% 22UF R833 4.3 PC_+V3_3 10 13
V_3.3_3_PC GND_2m_P_6
c
R846 1 PC_+V5 14 V_5.0_7_PC
15 V_5.0_8
16 V_5.0_9 GND_2m_P_10 17
TP_SATA_01 18 P_Reserve_11
GND_1m_P_12 19
s
20 V_12_13_PC
21 V_12_14 Mech1 23
22 V_12_15 Mech2 24
-
5,16..18,24,26,28,31,32,34,49,50,52,53,56,57 +V5S
Serial_ATA_Recepticle_Rev
1
p
C761 C760 +
0.1uF 0.1uF C759 C768
10% 10% 22UF 100uF
2
t o
B B
la p
w .
w
A A
w
Title
SATA
5 4 3 2 1
5 4 3 2 1
o m
c
D D
42 KBC_SCANIN[7:0]
s.
it c
J16
KBC_SCANIN0 24
KBC_SCANIN1 24
23 23
KBC_SCANIN2 22
KBC_SCANIN3 22
21 21
KBC_SCANIN4 20
KBC_SCANIN5 20
19 19
KBC_SCANIN6 18
KBC_SCANIN7 18
17 17
KBC_SCANOUT15 16 16
a
KBC_SCANOUT14 15
KBC_SCANOUT13 15
14 14
KBC_SCANOUT12 13
KBC_SCANOUT11 13
12 12
KBC_SCANOUT10 11
KBC_SCANOUT9 11
10 10
KBC_SCANOUT8 9
KBC_SCANOUT7 9
8 8
m
KBC_SCANOUT6 7
KBC_SCANOUT5 7
6 6
KBC_SCANOUT4 5
KBC_SCANOUT3 5
4 4
KBC_SCANOUT2 3
KBC_SCANOUT1 3
2
e
C KBC_SCANOUT0 1
2 C
1
KB_FPC_ZIF
42 KBC_SCANOUT[15:0]
c h
- s 47PF CP1C
47PF CP1B
47PF CP1D
47PF CP1A
p
6 7 5 8
Spares
J27 3 2 4 1
6
o
5
4 TOUCH_PAD_MOUSE_CLK_FB +V5S 5,16..18,24,26,28,30,32,34,49,50,52,53,56,57
TOUCH_PAD_MOUSE_CLK 42
TOUCH_PAD_MOUSE_DATA_FB FB36 120ohm@100MHz
t
3 TOUCH_PAD_MOUSE_DATA 42
2 +V5A_MB_FB FB35 120ohm@100MHz
1 FB37 120ohm@100MHz
B B
FPC_HDR C2037
0.1uF
p
10%
.la
A
ww A
w
Title
Keyboard and Touch Pad Connectors
5 4 3 2 1
5 4 3 2 1
o m
5,7,9,10,16..19,22..26,28,30,33,34,38,40,42,44,45,49,50,52,55..58 +V3.3S
10K
4.7K
D D
R755
R752
s
INT_IRQ14
IDE_PDIORDY
IDE_PATADET
it c
IDE_PD_CSEL
470
10K
+V5S 5,16..18,24,26,28,30,31,34,49,50,52,53,56,57
R788
R757
R314
a
100K
ODD Pull-Ups/Pull-Downs
IDE_RST#
3
m
Q37
BSS138
23 IDE_RST 1
2
e
C J26 R311 C
10K
1 AUDIO_L-CH DMARQ 22 IDE_PDDREQ 21
28 CD_L
2 AUDIO_R-CH IORDY 27 IDE_PDIORDY 21
28 CD_R IDE_PD_CSEL
3 AUDIO_GND CSEL 47
28 CD_GND
h
INTRQ 29 INT_IRQ14 21
5 IDE_RST#
21 IDE_PDD[15:0] RESET#
PDIAG# 32 IDE_PATADET 23
IDE_PDD0 21 30
DD0 0.9 IOCS16#
IDE_PDD1 19 28
DD1 DMACK# IDE_PDDACK# 21
c
IDE_PDD2 17 25
DD2 DIOW# IDE_PDIOW# 21
IDE_PDD3 15 24
DD3 DIOR# IDE_PDIOR# 21
IDE_PDD4 13
IDE_PDD5 DD4
11 DD5
IDE_PDD6 9 49
DD6 TEST
s
IDE_PDD7 7 50
IDE_PDD8 DD7 RSVD +V5S 5,16..18,24,26,28,30,31,34,49,50,52,53,56,57
6 DD8
IDE_PDD9 8
IDE_PDD10 DD9
10 38
-
DD10 +5V-1
100uF
0.1uF
0.1uF
22UF
IDE_PDD11 12 39
DD11 +5V-2
10%
10%
IDE_PDD12 14 40
DD12 +5V-3
1
IDE_PDD13 16 41 +
IDE_PDD14 DD13 +5V-4
18 DD14 +5V-5 42
C705
C703
C277
C690
IDE_PDD15 20
2
DD15
p
21 IDE_PDA0 33 DA0 GND0 4
37 DASP# GND3 43
44
o
GND4
GND5 45
36 0.7 46
21 IDE_PDCS3# CS1# GND6
t
21 IDE_PDCS1# 35 CS0# GND7 48
B CONN50_DVD_PLUG_K5D B
J26 Connects to ODD Interposer Header J4003
la p
w .
w
A A
w
Title
Optical Disk Drive
5 4 3 2 1
5 4 3 2 1
o m
c
D D
.
5,7,9,10,16..19,22..26,28,30,32,34,38,40,42,44,45,49,50,52,55..58 +V3.3S
MFUNC5 R417 43k
s
R420 43k
22 PCI_LOCK# R419 43k
23,40,42,44 INT_SERIRQ
MFUNC2 R423 43k
MFUNC1 R424 43k
R418 43k
it c
R412 47 CB_CLK_R 22 INT_PIRQA#
34 CB_CLK
34
34
34 CB_CBE#[3:0]
VPPD0
VPPD1
CB_CBE#0
CB_CBE#1
CB_CBE#2
CB_CBE#3
VR_PORT_C
34 CB_AD[31:0]
CB_AD10
CB_AD11
CB_AD12
CB_AD13
CB_AD14
CB_AD15
CB_AD16
CB_AD17
CB_AD18
CB_AD19
CB_AD20
CB_AD21
CB_AD22
CB_AD23
CB_AD24
CB_AD25
CB_AD26
CB_AD27
CB_AD28
CB_AD29
CB_AD30
CB_AD31
C315
CB_AD0
CB_AD1
CB_AD2
CB_AD3
CB_AD4
CB_AD5
CB_AD6
CB_AD7
CB_AD8
CB_AD9
1.0uF
10%
5,7,9,10,16..19,22..26,28,30,32,34,38,40,42,44,45,49,50,52,55..58 +V3.3S
a
+VCCA_CB 34
M12
M10
M11
G11
G13
G10
G12
H12
H11
C11
D10
H13
N12
H10
K11
K12
K13
B10
A12
B12
E11
B13
K10
F12
F11
F10
J13
J11
J10
C9
C8
D7
C7
C5
C4
D9
N9
U104
B9
B7
A4
B4
B3
A8
K7
K9
L9
L8
CAD0
CAD1
CAD2
CAD3
CAD4
CAD5
CAD6
CAD7
CAD8
CAD9
CAD10
CAD11
CAD12
CAD13
CAD14
CAD15
CAD16
CAD17
CAD18
CAD19
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD28
CAD29
CAD30
CAD31
CC/BE0#
CC/BE1#
CC/BE2#
CC/BE3#
CCLK
LEDA1/GPIO0/MFUNC0
LEDA2/GPIO1/MFUNC1
MFUNC2
IRQSER/MFUNC3
MFUNC4
MFUNC5
VPPD0
VPPD1
CLK_48_RSVD
VR_PORT
C311
C301 0.1uF
0.1uF 10%
D6 10%
34 CB_AUDIO CAUDIO
m
34 CB_BLOCK# A13 CBLOCK#
34 CB_DEVSEL# D11 CDEVSEL# VCCCB B11
34 CB_FRAME# A10 CFRAME# VCCP L3
34 CB_GNT# D13 CGNT#
A6 5,7,9,10,16..19,22..26,28,30,32,34,38,40,42,44,45,49,50,52,55..58 +V3.3S
34 CB_INT# CINT#
C10
e
C 34 CB_IRDY# CIRDY# C
34 CB_CLKRUN# A5 CCLKRUN# VCC6 N11
34 CB_PAR E12 CPAR VCC5 N7
34 CB_PERR# D12 CPERR# VCC4 M1
B8 E1 C302 C313 C310 C309 C314 C308 C312
34 CB_REQ# CREQ# VCC3
D8 D5 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
34 CB_RST# CRST# VCC2 10% 10% 10% 10% 10% 10% 10%
h
34 CB_SERR# B6 CSERR# VCC1 C13
34 CB_STOP#
34 CB_STSCHG
34 CB_TRDY#
E10
C6
C12
CSTOP#
CSTSCHG
CTRDY#
PCI1510GGU_ZGU VCC0
GND0
A7
A2
c
34 CB_RSVD1 A3 CRSVD/A03 GND1 A11
34 CB_RSVD2 E13 CRSVD/E13 GND2 D1
34 CB_RSVD3 J12 CRSVD/J12 GND3 F13
GND4 H4
34 CB_CD1# L13 CCD1# GND5 K8
s
34 CB_CD2# B5 CCD2# GND6 M13
34 CB_VS1 B2 CVS1 GND7 N2
34 CB_VS2 A9 CVS2
-
VR_EN#_R D4 VR_EN#
N13 VCCD0#
R411 34 VCCD0#
L12
SUSPEND#
100 34 VCCD1# VCCD1#
SPKROUT
DEVSEL#
RI_OUT#
MFUNC6
1%
FRAME#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PERR#
SERR#
GRST#
TRDY#
STOP#
PRST#
IRDY#
IDSEL
p PCLK
REQ#
GNT#
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PAR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
N8
M7
L7
N6
K4
M6
L6
N5
N4
M2
M5
L4
N3
K5
L5
M4
J4
H1
H3
H2
G2
G4
F1
C3
F3
E2
F4
B1
D2
E4
D3
E3
K6
M3
J2
A1
G1
F2
K2
J1
C1
K1
N1
K3
C2
G3
L2
L1
J3
L10
M9
N10
M8
L11
o
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
t
B
SPKROUT#_R
B
SUSPEND#_R
Wake Support
22 PCI_AD[31:0]
42 PCI_GATED_RST#
22 PCI_CBE#0
22 PCI_CBE#1
p
22 PCI_CBE#2
22 PCI_CBE#3
37 CLK_PCI_CARDBUS
PCI_AD24 R416 100 PCI_AD24_R
1%
la
22 PCI_DEVSEL#
22 PCI_FRAME#
22 PCI_GNT#0
22 PCI_IRDY#
22 PCI_PAR
.
22 PCI_PERR#
43K
43K
22 PCI_REQ#0 PCI_PME# 22
22,42 PCI_RST#
22 PCI_SERR#
+V3.3S 5,7,9,10,16..19,22..26,28,30,32,34,38,40,42,44,45,49,50,52,55..58
22 PCI_STOP#
22 PCI_TRDY#
R422
R421
23,40,42,44 PM_CLKRUN#
ww A
w
Title
Cardbus Controller
5 4 3 2 1
5 4 3 2 1
m
+V3.3S 5,7,9,10,16..19,22..26,28,30,32,33,38,40,42,44,45,49,50,52,55..58
RT2
+1 2 V3.3SS_CBCONN
+VCCA_CB 33 1.1A C717 C285
o
0.1uF 1uF +VCCA_CB 33
.JJ41
41 10% 10%
33 CB_AD[31:0] VCC_0 17
CB_AD0 2 51
CAD0 VCC_1
1
CB_AD1 3 +VPPA_CB +V5S 5,16..18,24,26,28,30..32,49,50,52,53,56,57 C719
c
CB_AD2 CAD1 RT3 0.1uF
37 CAD2
CB_AD3 4 18 +1 2 V5S_CBCONN 10%
2
D CB_AD4 38
CAD3 VPP1
52 D
.
CB_AD5 CAD4 VPP2
5 1.1A
CB_AD6 CAD5 C721 C729 U103
39 CAD6
CB_AD7 6 1 0.1uF 1uF 9 13 +VPPA_CB
CB_AD8 CAD7 GND0 10% 10% 12V AVCC0
41 CAD8 GND1 34 3 3_3V0 AVCC1 12
CB_AD9 8 35 4 11
s
CB_AD10 CAD9 GND2 3_3V1 AVCC2
42 CAD10 GND3 68 5 5V0 AVPP 10
CB_AD11 9 6 15
CB_AD12 CAD11 5V1 VPPD0 VPPD0 33
10 CAD12 16 SHDN# VPPD1 14 VPPD1 33
1
CB_AD13 44 13 TP_CARDBUS_OC# 8 1 C730
CAD13 CPAR CB_PAR 33 OC# VCCD0# VCCD0# 33
CB_AD14 11 14 7 2 0.1uF
it c
CAD14 CPERR# CB_PERR# 33 GND VCCD1# VCCD1# 33
CB_AD15 45 15 10%
2
CB_AD16 CAD15 CGNT# CB_GNT# 33 TPS2211
46 CAD16 CINT# 16 CB_INT# 33
CB_AD17 55 19 CB_CONN_CLK_R R816 33
CB_AD18 CAD17 CCLK CB_CLK 33
22 CAD18 CIRDY# 20 CB_IRDY# 33
CB_AD19 56
CB_AD20 CAD19
23 CAD20
CB_AD21 24 43
CAD21 CVS1 CB_VS1 33
CB_AD22 25 57
CAD22 CVS2 CB_VS2 33
CB_AD23 26
CB_AD24 CAD23
27 CAD24
a
CB_AD25 28
CB_AD26 CAD25
29 CAD26 RSRVD0 32 CB_RSVD1 33
CB_AD27 30 40
CAD27 RSRVD1 CB_RSVD3 33
CB_AD28 64 47
CAD28 RSRVD2 CB_RSVD2 33
CB_AD29 31
CB_AD30 CAD29
65 CAD30
CB_AD31 66 48
33 CB_CBE#[3:0] CAD31 CBLOCK# CB_BLOCK# 33
CB_CBE#0 7 33
CB_CBE#1 CCBE0# CCLKRUN# CB_CLKRUN# 33
m
12 CCBE1# CSTOP# 49 CB_STOP# 33
CB_CBE#2 21 59
CCBE2# CSERR# CB_SERR# 33
CB_CBE#3 61 60
CCBE3# CREQ# CB_REQ# 33
33 CB_DEVSEL# 50 CDEVSEL#
62 CB_AUDIO 33
e
C CAUDIO C
33 CB_TRDY# 53 CTRDY#
CSTSCHG 63 CB_STSCHG 33
33 CB_FRAME# 54 CFRAME#
CCD1# 36 CB_CD1# 33
33 CB_RST# 58 CRST# CCD2# 67 CB_CD2# 33
h
G1 G1
G2 G2
G3 G3
G4 G4
c
G5 G5
G6 G6
G7 G7
G8 G8
G9 G9
s
G10 G10
G11 G11
G12 G12
69 G13
-
SHIELD1 G13
70 SHIELD2 G14 G14
71 SHIELD3 G15 G15
72 SHIELD4 G16 G16
p
68PIN_CARDBUS
t o
B B
la p
w .
w
A A
w
Title
Cardbus Connector and Power Switch
5 4 3 2 1
5 4 3 2 1
SI2307DS
+V3.3M 13..15,23,24,36,42,45,50,56,57 +V3.3M_LAN_SW 36
m
C612 27pF 2 3Q23
5%
C589
1
LAN_XTAL2 R644 1000pF C590
o
LAN_XTAL1 1M 10% 22uF
1
Y2
25.00MHz
Layout Note: Place R643 100K LAN_EDC_3.3EN#
3LAN_PHYPC_EN#
2
GLAN_CLK series
c
resistor close to C600 27pF
Nineveh
D 5% D
.
H5
H6
U47
R678 33 GLAN_CLK_R E2 J9
XTAL2
XTAL1
21 GLAN_CLK JKCLK VSSA[17]
J8
s
VSSA[16] Q22
21 LAN_RSTSYNC E3 JRSTSYNC VSSA[15] J5
J3 BSS138
VSSA[14]
21 LAN_TXD0 D1 JTXD0 VSSA[13] J1 23 LAN_PHYPC 1
LCI
Layout Note: Add test F3 G9
points on LAN_TXD[2:0] 21 LAN_TXD1 JTXD1 VSSA[12]
it c
21 LAN_TXD2 F1 G8
2
and LAN_RXD[2:0] JTXD2 VSSA[11]
VSSA[10] G6
D3 JRXD0 VSSA[09] F6
21 LAN_RXD0
D2 JRXD1 VSSA[08] E9
21 LAN_RXD1
C1 JRXD2 VSSA[07] D6
21 LAN_RXD2
VSSA[06] C9
VSSA[05] C8
C630 0.1uF GLAN_RXP_C H2 C7
22 GLAN_RXP 10% C631 0.1uF GLAN_RXN_C GLAN_TXP VSSA[04]
J2 GLAN_TXN VSSA[03] C6
22 GLAN_RXN 10%
VSSA[02] A9
GLCI
a
J4 A8 Place close to PNP
22 GLAN_TXP GLAN_RXP VSSA[01] Emitter
H4 F4 +V3.3M_LAN_SW 36
22 GLAN_TXN GLAN_RXN VSS[04]
VSS[03] E1
R648 1.40K LAN_KMRN_RCOMP_P G7 C4
1% LAN_KMRN_RCOMP_N KBIAS_P VSS[02]
H7 KBIAS_N VSS[01] A1
+V1.0_LAN_M C653 C651
0.1uF 4.7uF
A4 F7 C235 10% 10%
m
36 LAN_LED_LNK#_ACT LED0 VDD1P0[03] 0.01uF
B4 LED1 VDD1P0[02] E8
36 LAN_LED_1000# 10%
A5 LED2 VDD1P0[01] D7
36 LAN_LED_100#
3
+V3.3M_LAN_SW 36
C 36 LAN_MDI0P B8 MDI_PLUS[0] VCCF1P0 E5 CTRL_18 1 Q30 C
e
B9 BCP69 Place at least 1cm2
36 LAN_MDI0N MDI_MINUS[0]
1
C216 C618 mounting PAD for
36 LAN_MDI1P D9
D8
MDI_PLUS[1] MDI VCCFC1P0 H3 0.1uF
10%
4.7uF
10% 2 4
collector
36 LAN_MDI1N
2
MDI_MINUS[1] +V1.8_LAN_M 36,45
VCC3P3[02] F2
h
36 LAN_MDI2P F9 MDI_PLUS[2] VCC3P3[01] B3
Place resistor Rcomp as F8
close as possible to the 36 LAN_MDI2N MDI_MINUS[2] +V1.8_LAN_M 36,45
device (less than 1") H8 G5 +V1.8_LAN_M +V1.8_LAN_M
36 LAN_MDI3P MDI_PLUS[3] VCC1P8[04]
H9 F5
c
36 LAN_MDI3N MDI_MINUS[3] VCC1P8[03]
VCC1P8[02] D5
C2 C650 C638 C608 C606 C629 C625
VCC1P8[01]
0
Layout Note: TP_LAN_ATEST_P +V1.0_LAN_M 10uF 10uF 0.1uF 0.1uF 470PF 470PF
NO_STUFF
A7 IEEE_TEST_P
Keep this resistor on top side TP_LAN_ATEST_N B7 G4 10% 10%
IEEE_TEST_N VCC1P0
-s
R199
CAD Note: TP_LAN_RSVDJ6 J6 E4

Connect resistor TP_LAN_RSVDJ7 RESERVED_J6 VCC[02]
J7 RESERVED_J7 VCC[01] D4
to GND near ball
E6 B1 Place close to PNP Place close to
R649 1.40K LAN_RBIAS_P V1P0_OUT Collector Nineveh
1%
E7 RBIAS_P JTAG
E6 RBIAS_N
RESERVED
C3 CTRL_10
CTRL_10 CTRL_18
B2
p
TP_LAN_RSVDB5 CTRL_18
B5 RSVD_B5
JTAG_TMS
JTAG_TDO
JTAG_TCK
R204 0 LAN_DISABLE#
JTAG_TDI
23,42 PM_LAN_ENABLE A6 RSVD_A6

NO_STUFF TP_LAN_TEST2 C5 A2 TP_THERM_D_P R212 +V3.3M_LAN_SW 36
TP_LAN_TEST_EN RSVD_C5 THERM_D_P TP_THERM_D_N 0
B6 A3
o
TEST_EN THERM_D_N NO_STUFF Place close to PNP
C654 C648 Emitter
t
NINEVEH(REV 1p0) 0.1uF 4.7uF
G1
H1
G3
G2
B R657 10% 10% B
NO_STUFF
100 Layout Note: C234
1% Keep this resistor on top 0.01uF
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TDI
side 10% 3
p
CTRL_10 1 BCP69
Q29
Place atleast 1cm2
mounting PAD for
collector 2 4
la
+V1.0_LAN_M
+V1.0_LAN_M
.
+V1.0_LAN_M
C655 C637 C599 C614 C595 C603

10uF 10uF 0.1uF 0.1uF 470PF 470PF
10% 10%
w
Place close to PNP Place close to
Collector Nineveh
w
Title
w
Nineveh GLAN

A
5 4 3 2 1
5 4 3 2 1
+V3.3M_LAN_SW 35 +V3.3M_LAN_SW 35 +V3.3M_LAN_SW 35
m
C579 C563 C565 C557 C577 C201 C581 C580
+V3.3M_LAN_SW 35 +V3.3M_LAN_SW 35 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10% 10% 10% 10% 10%
o
R195
10K
56
50
38
27
18
10
c
4
5
U2009 J15B
D 17 48 J14 D
NC
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
21,23,42 DOCK_LAN_EN# SEL 0B1 LAN_MDI0P_Q_DOCK 45
.
47 1 RJ11_1 S1
1B1 LAN_MDI0N_Q_DOCK 45 1 TIP
2B1 43 LAN_MDI1P_Q_DOCK 45 2 2
42 RJ11_2 S2
3B1 LAN_MDI1N_Q_DOCK 45 RING
37 CON2_HDR
4B1 LAN_MDI2P_Q_DOCK 45
2 36
s
35 LAN_MDI0P A0 5B1 LAN_MDI2N_Q_DOCK 45
3 32 RJ11 & RJ45 +LEDS
35 LAN_MDI0N A1 6B1 LAN_MDI3P_Q_DOCK 45
35 LAN_MDI1P 7 A2 7B1 31 LAN_MDI3N_Q_DOCK 45
8 +V1.8_LAN_M 35,45 +V3.3M_LAN_SW 35
35 LAN_MDI1N A3
35 LAN_MDI2P 11 A4 0LED1 22 LAN_LED_LINK#_DOCK 45
it c
35 LAN_MDI2N 12 A5 1LED1 23 LAN_LED_1000#_DOCK 45
14 52 J15A
35 LAN_MDI3P A6 2LED1 LAN_LED_100#_DOCK 45
15 T1
35 LAN_MDI3N A7
PI3L500 LAN Switch 1 TCD_0 CMT_0 24 CMT_0
2 23 LAN_MDI0P_M 1
LAN_MDI0P_Q TRD+_0 TXD+_0 LAN_MDI0N_M 0+
35 LAN_LED_LNK#_ACT 19 LED0 0B2 46 3 TRD-_0 TXD-_0 22 2 0-
20 45 LAN_MDI0N_Q 4 21 CMT_1 LAN_MDI1P_M 3
35 LAN_LED_1000# LED1 1B2 TCD_1 CMT_1 1+
54 41 LAN_MDI1P_Q 5 20 LAN_MDI1N_M 4
35 LAN_LED_100# LED2 2B2 TRD+_1 TXD+_1 1-
40 LAN_MDI1N_Q 6 19 LAN_MDI2P_M 5
3B2 LAN_MDI2P_Q TRD-_1 TXD-_1 2+
4B2 35 7 TCD_2 CMT_2 18 CMT_2 LAN_MDI2N_M 6 2- GND4 G4
a
34 LAN_MDI2N_Q 8 17 LAN_MDI3P_M 7 G3
5B2 LAN_MDI3P_Q TRD+_2 TXD+_2 LAN_MDI3N_M 3+ GND3
6B2 30 9 TRD-_2 TXD-_2 16 8 3- GND2 G2
57 29 LAN_MDI3N_Q 10 15 CMT_3 G1
THRM 7B2 TCD_3 CMT_3 GND1
11 TRD+_3 TXD+_3 14
25 LAN_LED_LNK#_ACT_Q R182 0 12 13 A4
0LED2 NO_STUFF TRD-_3 TXD-_3 R202 300 RJ45_A3_R LED_100# GRN
26 A3
GND10
GND11
GND12
GND13
1LED2 LED_100
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9 LAN_LED_100#_Q SINGLE_PORT_XFMR
2LED2 51
LAN_LED_1000#_Q R181 0 LAN_LED_1000#_R A6
m
R203 300 RJ45_A5_R LED_1000# YEL
A5 LED_1000 LAN_AGND
1
6
9
13
16
21
24
28
33
39
44
49
53
55
RJ11 & RJ45 +LEDS
Place Near Pin A3
Place Near Pin A5

470PF
470PF
C C
e
Place one cap near
C200
C202
C164 C145 C172 C153 each TCD pin of
5
U34 0.1uF 0.1uF 0.1uF 0.1uF magnetics module

10% 10% 10% 10%
VDD
c h
75
75
75
75
LAN_MDI0P_M 1 6 LAN_MDI1P_M LAN_MDI3N
I/O1 I/O6 LAN_MDI3P
LAN_MDI2N
LAN_MDI0N_M 3 4 LAN_MDI1N_M LAN_MDI2P
I/O3 I/O4
R174
R170
R159
R142
LAN_MDI1N
-s
LAN_MDI1P
LAN_MDI0N
LAN_MDI0P
GND
R187 R188 R189 R190 R191 R192 R193 R194
CMT
SRV05-4_TVS_DIODE_ARRAY 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
2
1% 1% 1% 1% 1% 1% 1% 1%
p
C180 LANMDI1_R LANMDIO_R LANMDI2_R LANMDI3_R
1500pF
10%
5
U36 C588 C587 C586 C585
o
0.1uF 0.1uF 0.1uF 0.1uF
VDD
C572 C573 C185 10% 10% 10% 10%
t
1000pF 1000pF 10uF
B 5% 5% LAN_AGND B
LAN_MDI3N_M 1 6 LAN_MDI2N_M
I/O1 I/O6
p
* Place R861 & R863 close to each other.
LAN_MDI3P_M 3 4 LAN_MDI2P_M
I/O3 I/O4 SPI_SI_R R862 15
+V3.3M 13..15,23,24,35,42,45,50,56,57 1% SPI_SI 22
+V3.3M 13..15,23,24,35,42,45,50,56,57
la
U65 U67
8 5 SPI_CS#1_SI_R R854 47 8 5 SPI_CS#0_SI_R R863 47
GND
VDD SI SPI_CS#1_SO_R R857 15 VDD SI SPI_CS#0_SO_R R859 15

SO 2 * SO 2 * SPI_SO 22
1 1% 1 1%
CE# SPI_CS#1 22 CE# SPI_CS#0 22
.
SRV05-4_TVS_DIODE_ARRAY R852 3.3K SPI_WP#0 3 6 SPI_CS#1_CLK R860 3.3K SPI_WP#1 3 6 SPI_CS#0_CLK
2
WP# SCK WP# SCK
R848 3.3K SPI_HOLD#0 7 4 R858 3.3K SPI_HOLD#1 7 4 R861

HOLD# VSS HOLD# VSS 47
SST SPI FLASH SST SPI FLASH
w
Energy detect circuitry
13..15,23,24,35,42,45,50,56,57 +V3.3M
ED_MDI0P_R
R853 47
SPI_CLK 22
C596
0.1uF
w
LAN_MDI0P_M C182 0.01uF R185 R647 10%
10% 10K 200K R650
5
U42 1.5K
NO_STUFF
+V3.3M 13..15,23,24,35,42,45,50,56,57
A A
ENRGY_DET_MDI
C591
1 + SPI Decoupling Oakmont Form Factor Reference Design Intel Confidential
ED_MDI1P_R
4 ENRGY_DET_GPIO13 21
w
10pF 3
5%
- Title
C765 C772 C769 C774
LAN Docking and SPI
ENRGY_DET_VREF
LMV331M5X 0.1uF 0.1uF 0.1uF 0.1uF

2
LAN_MDI1P_M C181 0.01uF R186 10% 10% 10% 10%

10% 10K R646
R184
100K
100K
1% Place 2 near U43 and 2 near U45
A
R642 3.92k
1%
5 4 3 2 1
5 4 3 2 1
+V3.3M_CK505 56,57
Place each 0.1uF cap as close as
CPU,MCH and XDP BCLK FREQUENCY
m
7,10,48,56,57 +V1.25M possible to each VDD_IO pin. Place
the 10uF cap on the VDD_IO plane.
SELECTION TABLE
C668 C665 C681 +VDDIO_CLK
0.1uF 0.1uF 0.1uF FSC FSB FSA Host Clock
10% 10% 10%
frequency MHz
o
BSEL2 BSEL1 BSEL0
1
2
5
6
Q3002 C682 C667 C679 100
0.1uF 0.1uF 0.1uF 1 0 1
C684 C683 C673 C669 SI3442BDV 10% 10% 10% 133
0.1uF 0.1uF 4.7uF 0.1uF 3 0 0 1
c
10% 10% 10% 10% 166
0 1 1
D
CK505 200 D
.
1 0
4
0
TSSOP64 0 0 0 266
+VDDIO_CLK C664 C685 C666 C680
R731 475 0.1uF 10uF 0.1uF 0.1uF 333
23 CLK_SATA_OE#
56,57 +V3.3M_CK505 10% 10% 10% 1 0 0
s
R312 475 400
26 CLK_EXPCARD_OE#
U32 1 1 0
2 48 IO_VOUT Reserved
9
VDD_PCI IO_VOUT 1 1 1
VDD_48
it c
16 VDD_PLL3
R324 33 61 64
42 CLK_PCI_KBC VDD_REF SCLK SMB_CLK_M3 23,38 CK-505 & DB200 OE table
39 VDD_SRC SDA 63 SMB_DATA_M3 23,38 O/P O/P
10K
33pF 56,57 +V3.3M_CK505 CK-PARTS OE# signal Port Pin CLK Outputs
NO_STUFF
NO_STUFF
55 VDD_CPU Port Pin
5%
Adaptive 12 VDD_IO SRC5/PCI_STOP# 38 PM_STPPCI# 23 CLK_PCIE_SATA SRC2 21
C263
R876
R327 20 37 CLK_SATA_OE# A 1 CLK_PCIE_SATA# SRC2# 22
Clocking R732 10K 26
VDD_PLL3_IO SRC5#/CPU_STOP# PM_STPCPU# 23
10K VDD_SRC_IO_1 CPU0 R260 33
42 VSS_SRC3 CPU0 54 CLK_CPU_BCLK 3 CLK_PCIE_EXPCARD1 SRC4 27
36 53 CPU#0 R261 33 CK-505 CLK_EXPCARD_OE# B 3 CLK_PCIE_EXPCARD1#SRC4# 28
VDD_SRC_IO_2 CPU0# CLK_CPU_BCLK# 3
a
49 VDD_CPU_IO
51 CPU1 R262 33 CLK_PCIE_DOCK SRC10 34
CPU1 CLK_MCH_BCLK 6
50 CPU#1 R263 33 CLK_PCIE_DOCK_OE# H 33 CLK_PCIE_DOCK# SRC10# 35
CPU1# CLK_MCH_BCLK# 6
R328 12.1 PCI0_OE#_R 1
40 CLK_PCI_SIODOCK 1% PCI0/OE#0/2 SRC8_ITP R264 33
SRC8/ITP 47 CLK_ITP 20 CLK_PCIE_3GPLL SRC9 30
R746 12.1 PCI1_OE#_R 3 PCI1/OE#1/4 SRC8#/ITP# 46 SRC#8_ITP# R265 33
CLK_ITP# 20 CLK_MCH_OE# G 32 CLK_PCIE_3GPLL# SRC9# 31
40 CLK_PCI_SIO 1%
R745 12.1 PCI2_TME 4 35 SRC10# R270 33 CLK_PCIE_MINICARD1 DIF_0 7
44 CLK_PCI_TPM PCI2/LTE SRC10# CLK_PCIE_DOCK# 45
m
1% 34 SRC10 R271 33 CLK_MINICARD1_OE#CLK 4 CLK_PCIE_MINICARD1#DIF_0# 8
SRC10 CLK_PCIE_DOCK 45 REQ0#
R329 12.1 PCI3 5 DB-200
33 CLK_PCI_CARDBUS 1% PCI3
CLK_PCIE_MINICARD2 DIF_1 14
PCI4_SRC5_EN CLK_MINICARD2_OE# CLK 17 CLK_PCIE_MINICARD2#DIF_1# 13
6 PCI4/SRC5_EN SRC11/OE#10 33 CLK_PCIE_DOCK_OE# 45 REQ1#
SRC11#/OE#9 32 CLK_MCH_OE# 7
R330 12.1 PCIF5_ITP_EN 7
e
C 22 CLK_PCIF_ICH 1% PCIF5/ITP_EN C
XTAL_IN 60 30 SRC9 R342 33
XTAL_IN SRC9 CLK_PCIE_3GPLL 7
31 SRC9# R343 33
SRC9# CLK_PCIE_3GPLL# 7
XTAL_OUT 59 XTAL_OUT SRC7 R266 33 CLK_SRC_DB200_R R253 0
SRC7/OE#8 44 CLK_SRC_DB200 38
R333 33 SRC#7 R267 33 CLK_SRC_DB200#_R R254 0
h
SRC7#/OE#6 43 CLK_SRC_DB200# 38
23 CLK_USB48 FSA 10 USB/FSA
R733 41 SRC6 R268 33 Adaptive Clocking
10K SRC6 CLK_PCIE_ICH 22
Adaptive C267 40 SRC#6 R269 33
SRC6# CLK_PCIE_ICH# 22
0.1uF 57
Clocking FSB/TESTMODE
c
10% 27 SRC4 R340 33
SRC4 CLK_PCIE_EXPCARD1 26
NO_STUFF 28 SRC#4 R341 33
SRC4# CLK_PCIE_EXPCARD1# 26
FSC 62 REF/FSC/TESTSEL SRC3
SRC3/OE#_0/2 24
R748 2.2K 25 SRC3#
3,7 MCH_BSEL0 SRC3#/OE#1/4
-s
3,7 MCH_BSEL1
R257 2.2K 21 SRC2 R336 33
3,7 MCH_BSEL2 SRC2/SATA CLK_PCIE_SATA 21
8 22 SRC2# R337 33
Y4 VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 21
R258 33 11
23 CLK_REF_ICH VSS_48 SS_CLK R750 33
1 2 15 VSS_IO SRC1/SE1 17 DREFSSCLK 7
R259 33 19 18 SS_CLK# R747 33
40 CLK_REF_SIO VSS_PLL3 SRC1#/SE2 DREFSSCLK# 7
14.318MHZ 52 VSS_CPU
C246 C252 +VDDIO_CLK 23 13 DOT96 R334 33
VSS_SRC1 SRC0/DOT96 DREFCLK 7
33pF 33pF C659 29 14 DOT96# R335 33 NO_STUFF
VSS_SRC2 SRC0#/DOT96# DREFCLK# 7
p
5% 5% C658 0.1uF 45 SRC3 R338 33
0.1uF 10% VDD_SRC_IO_3 SRC3# R339 33
58 VSS_REF CKPWRGD/PWRDWN# 56 CLK_PWRGD 23
10% NO_STUFF C269 C268 NO_STUFF
NO_STUFF CK505 0.1uF 0.1uF C270
10% 10% C271 0.1uF
Adaptive Clocking NO_STUFF NO_STUFF 0.1uF 10%
o
NO_STUFF 10%
Adaptive Clocking NO_STUFF
t
B For Adaptive Clocking support B
Place resistors under R754 and
p
R751 so that there is no stub on
MCH side
. la
A
ww A
w
Title
CK505

Custom
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,40,42,44,45,49,50,52,55..58
a
C369 C367 C384
10uF 0.1uF 0.1uF
10% 10%
m
0
0
C368 C383 C385
0.1uF 0.1uF 0.1uF U9
NO_STUFF
NO_STUFF
10% 10% 10% 5 7 DIF0 R478 33
VDD0 DIF_0 CLK_PCIE_MINICARD2 25
9 8 DIF#0 R479 33
VDD1 DIF_0# CLK_PCIE_MINICARD2# 25
R48
R44 12
e
C 16
VDD2
14 DIF2 R515 33 C
VDD3 DIF_1 CLK_PCIE_MINICARD1 25
20 13 DIF#2 R516 33
VDD4 DIF_1# CLK_PCIE_MINICARD1# 25
37 CLK_SRC_DB200 2 CLK_IN
37 CLK_SRC_DB200# 3 CLK_IN#
DB200
h
23,37 SMB_DATA_M3 10 SDATA CLKREQ0# 4 CLK_MINICARD2_OE# 25
23,37 SMB_CLK_M3 11 SCLK CLKREQ1# 17 CLK_MINICARD1_OE# 25
DB200IREF 18 IREF
0
c
1 DB200_PLL_BW
PLL_BW
NO_STUFF
NO_STUFF
6 GND0
R501 15
475 GND1 R480
19 GNDA
R49
R45
10K
s
CLK_PCIE_MINICARD2#
-
CLK_PCIE_MINICARD2
CLK_PCIE_MINICARD1#
CLK_PCIE_MINICARD1
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,40,42,44,45,49,50,52,55..58
p 1%
1%
1%
1%
10K
10K
49.9
49.9
49.9
49.9
o R10515
R10516
R514
R517
R476
R477
t
CLK_MINICARD2_OE#
B CLK_MINICARD1_OE# B
la p
w .
w
A A
w
Title
Clock Buffer

Custom
5 4 3 2 1
5 4 3 2 1
20..26,29,40..42,44..48,50,51,55..58 +V3.3A
o m
c
D 20..26,29,40..42,44..48,50,51,55..58 +V3.3A D
.
R735
R722 10K
C676 1.40K
0.1uF 1%
s
U56
16 15 PCA9557_RST#
VDD RESET#
8 VSS
6 BOARDID01
I/O0
it c
42,51 SMB_BS_CLK 1 SCLK I/O1 7
2 9 BOARDID23
42,51 SMB_BS_DATA SDATA I/O2
I/O3 10
R724 0 A0_R 3 11 REV_FAB_ID0
R726 0 A1_R A0 I/O4 REV_FAB_ID1 R738
4 A1 I/O5 12
R728 0 A2_R 5 13 REV_FAB_ID2 10K
A2 I/O6 REV_FAB_ID3
I/O7 14
PCA9557PW
a
8-bit I/O Port Expander
m
C FAB ID Strapping Table C
e
FAB_REV BOARD FAB
20..26,29,40..42,44..48,50,51,55..58 +V3.3A 3 2 1 0
h
0 0 0 0 1
FAB REVISION 0 0 0 1 2
0 0 1 0 3
0 0 1 1 4
c
R730 R736 BOARD REVISION Strapping Table
10K 10K
No_Stuff No_Stuff
BOARD REVISION BOARD ID
-s
3 2 1 0
0 0 0 0 Foutain Grove
REV_FAB_ID0 0 0 0 1 Matanzas
REV_FAB_ID1 0 0 1 0 TBD
REV_FAB_ID2 0 0 1 1 TBD
REV_FAB_ID3
0 1 0 0 TBD
0 1 0 1 TBD
p
R725 R723 R737 R729 0 1 1 0 TBD
10K 10K 10K 10K 0 1 1 1 TBD
1 0 0 0 TBD
1 0 0 1 TBD
o
1 0 1 0 TBD
1 0 1 1 TBD
t
B 1 1 0 0 TBD B
1 1 0 1 TBD
1 1 1 0 TBD
1 1 1 1 TBD
la p
slave address
0 0 1 1 A2 A1 A0 R/W
.
fixed programmable
PCA9557 Address

A
w
Title
I/O Port Expander

A
5 4 3 2 1
5 4 3 2 1
m
5,7,9,10,16..19,22..26,28,30,32..34,38,42,44,45,49,50,52,55..58 +V3.3S
o
20..26,29,39,41,42,44..48,50,51,55..58 +V3.3A +V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,42,44,45,49,50,52,55..58
R795 R793
c
10K 10K
D U61 D
.
5 VCC1 LAD0 64 LPC_AD0 21,42,44
17 VCC2 LAD1 2 LPC_AD1 21,42,44
31 VCC3 LAD2 4 LPC_AD2 21,42,44
POWER & GROUND

42 VCC4 LAD3 7 LPC_AD3 21,42,44
60 14
s
VCC5 LFRAME LPC_FRAME# 21,42,44
LDRQ0 24 ICH_DRQ#0 21
48 VTR LDRQ1 12 ICH_DRQ#1 21
PCI_RESET 22 PLT_RST# 7,19,22,25,26,58
C697 8 25
VSS1 LPCPD PM_SUS_STAT# 23,42,44
LPC INTERFACE
it c
0.1uF 20 16
R774 VSS2 CLKRUN PM_CLKRUN# 23,33,42,44
29 VSS3 SER_IRQ 19 INT_SERIRQ 23,33,42,44
8.2K 37 47
VSS4 IO_PME PM_RI# 23
45 VSS5 PCI_CLK 21 CLK_PCI_SIO 37
62 VSS6 LPC_CLK_33 10 CLK_PCI_SIODOCK 37
SIO_14M 23 CLK_REF_SIO 37
TP_RS232_EN 27 GPIO10
26 IRDA_CIR_SLT 28 GPIO11
23,42,45 SMC_EXTSMI# 30 GPIO12/IO_SMI# DLAD(0) 63
a
TP_SIO_GPIO13 32 1
GPIO13/IRQIN1 DLAD(1)
DOCKING LPC INTERFACE

TP_LPCD_OPNREQ_OUT# 33 3
GPIO14/IRQIN2 DLAD(2)
GENERAL PURPOSE I/O

RS232_R# 34 6
TP_LPCS_PME# GPIO15 DLAD(3)
35 GPIO16 DLFRAME 13
TP_LPCD_RI# 36 11
LPCD_PWRGD GPIO17 DLDRQ1
38 GPIO30 DCLKRUN 15
39 GPIO31 DSER_IRQ 18
17 L_BKLTSEL1# TP_GPIO32 40 9
m
R775 TP_GPIO33 GPIO32 DLPC_CLK_33
41 GPIO33 DSIO_14M 26
100K TP_LPCD_LPCPD# 43
TP_LPCD_LPCRST# GPIO34
44 GPIO35
TP_LPCD_PWREN# 46 GPIO36
C 61 GPIO37 RXD1 52 SER_SINA C
e
17 L_BKLTSEL0# SER_SOUTA J23
TXD1 53
54 SER_DSRA# SER_SINA 6
UART1
DSR1 SER_CTSA# SER_SOUTA 6
CTS1 56 5 5
58 TP_SER_RIA# SER_CTSA# 4
RI1 4
IR
UART2
49 59 TP_SER_DCDA# SER_RTSA# 3
26 IR_TXD IRTX2 DCD1 3
h
50 55 SER_RTSA# SER_DSRA# 2
26 IR_RXD IRRX2 RTS1#/SYSOPT0 2
51 57 SER_DTRA# SER_DTRA# 1
26 IR_MODE IRMODE/IRRX3 DTR1#/SYSOPT1 1
SIO1007-JV SM06B-SSR-H-TB
c
5,7,9,10,16..19,22..26,28,30,32..34,38,42,44,45,49,50,52,55..58 +V3.3S
R766 10K SER_RTSA# R767 10K
s
Base Address:
NO_STUFF 00 = 0x002E
01 = 0x004E
R762 10K SER_DTRA# R765 10K 10 = 0x162E
-
NO_STUFF 11 = 0x164E
Default:
11= 0x164E
o p
t
B B
la p 5,7,9,10,16..19,22..26,28,30,32..34,38,42,44,45,49,50,52,55..58 +V3.3S
.
C709 C693 C710 C702 C704
C707 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
22UF

A
w
Title
SIO

A
5 4 3 2 1
5 4 3 2 1
o m
c
D J30 D
.
1 1
22 USB_PP7 2 2
22 USB_PN7 3 3
25 BT_PRI_CLK 4 4 10 Pin connector used
s
58 BT_ACTIVE 5 5
+V3.3_BT 6 for Taiyo Yuden
6 Module
25 CHANNEL_DATA 7 7
8 8
9 9
it c
10 10
C773
2.2uF BM10-SRSS-TB
10%
a
e m
C C
c h
-s
20..26,29,39,40,42,44..48,50,51,55..58 +V3.3A
20..26,29,39,40,42,44..48,50,51,55..58 +V3.3A +V3.3_BT

C767
1uF
10% C766 R851
0.01uF 100K
10%
p
R850
10K
U66
4 S2 D2A 2
3
Si1865DL
D2B C771 C770
5
o
42 BT_ON ON/OFF 2.2uF 0.1uF
R2 1 6 R1,C1 10%
R2 R1,C1
t
R856
B 10K B
la p
w .
w
A A
w
Title
Bluetooth
5 4 3 2 1
5 4 3 2 1
+V3.3A 20..26,29,39..41,44..48,50,51,55..58
m
C250 C243 C238 C265 C264
22uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10%
+V3.3A 20..26,29,39..41,44..48,50,51,55..58
o
Remove shunt J20 on page 58
for H8 external reflash
VCL
C695 +V3.3A 20..26,29,39..41,44..48,50,51,55..58
0.1uF +V3.3A 20..26,29,39..41,44..48,50,51,55..58
c
51 +VREF_ADC 10%
D R353 J21 D
.
10K 6
R345 R317 KBC_PROG_TX# 6
5 5
+V3.3A 20..26,29,39..41,44..48,50,51,55..58 10K 10K KBC_PROG_RX# 4
Y5 MD0 4
3 3
1 2 U98 MD1 2
s
TP_KBC_PA7 2
1 VCC1 PA7/KIN15#/PS2CD 33 1 1
C259 10MHZ C266 R354 R355 86 34 TP_KBC_PA6 C657
18PF 18PF 10K 10K VCC3 PA6/KIN14/PS2CC 1uF SM06B-SSR-H-TB
VCL 13 38
VCL PA3/KIN11#/PS2AD TOUCH_PAD_MOUSE_DATA 31
it c
36 VCC2 PA2/KIN10#/PS2AC 39 TOUCH_PAD_MOUSE_CLK 31
77 AVREF
76 35 TP_KBC_PA5
AVCC PA5/KIN13#/PS2BD TP_KBC_PA4
PA4/KIN12#/PS2BC 37
MD1 9 19
MD1 P95/IRQ14# KBC_CAPSLOCK 58
MD0 10 20 TP_KBC_P94
MD0 P94/IRQ13#
P93/IRQ12# 21 KBC_NUMLOCK 58
TP_KBC_X1 140
TP_KBC_X2 X1 KBC_SCANIN0
141 X2 P60/KIN0#/FTCI/TMIX 78
SMC_XTAL 143 79 KBC_SCANIN1 +V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,44,45,49,50,52,55..58
XTAL P61/KIN1#/FTOA
a
SMC_EXTAL 144 80 KBC_SCANIN2
EXTAL P62/KIN2#/FTIA/TMIY KBC_SCANIN3 R287 10K
+V3.3A 20..26,29,39..41,44..48,50,51,55..58 P63/KIN3#/FTIB 81 SMC_RUNTIME_SCI# 23
8 82 KBC_SCANIN4 R10521 10K
58 SMC_RST# RES# P64/KIN4#/FTIC SMC_EXTSMI# 23,40,45
SMC_STBY# 12 83 KBC_SCANIN5
R362 100 NMI_R STBY# P65/KIN5#/FTID KBC_SCANIN6
58 SMC_INITCLK 11 NMI P66/IRQ6#/KIN6#/FTOB 84
85 KBC_SCANIN7 R294 1.40K 1% ALS_DATA
R321 10K KBC_DISABLE# P67/IRQ7#/KIN7#/TMOX R300 1.40K 1% ALS_CLK
15 P51/TMOY KBC_SCANIN[7:0] 31
16 96 KBC_SCANOUT15
m
23,48 ALL_SYS_PWRGD P50/EXEXCL P27/PW15
14 97 KBC_SCANOUT14 +V3.3A 20..26,29,39..41,44..48,50,51,55..58
39,51 SMB_BS_CLK P52/EXIRQ6#/SCL0 P26/PW14
17 98 KBC_SCANOUT13 R302 10K
39,51 SMB_BS_DATA P97/IRQ15#/SDA0 P25/PW13 SMC_WAKE_SCI# 23
18 99 KBC_SCANOUT12 R761 4.7K
51 BC_ACOK P96/0/EXCL P24/PW12 SMB_BS_DATA 39,51
TP_SMB_BS_ALRT# 22 100 KBC_SCANOUT11 R760 4.7K
P92/IRQ0# P23/PW11 SMB_BS_CLK 39,51
C TP_KBC_P91 23 P91/IRQ1# P22/PW10 101 KBC_SCANOUT10 R352 10K
NMI_GATE 58
C
e
24 102 KBC_SCANOUT9
55 SMC_ONOFF# P90/IRQ2#/ADTRG# P21/PW9
103 KBC_SCANOUT8 R308 10K KBC_PROG_TX#
P20/PW8 KBC_SCANOUT7 R10522 10K KBC_PROG_RX#
23,56,57 LAN_WOL_EN 68 P70/EXIRQ0#/AN0 P17 104
20..26,29,39..41,44..48,50,51,55..58 +V3.3A 69 105 KBC_SCANOUT6 R304 10K BATTFULL_GPIO
23,45,48,56,57 PM_SLP_M# P71/EXIRQ1#/AN1 P16
70 106 KBC_SCANOUT5 R290 10K BATTCHRG_GPIO
23,45,56,57 PM_S4_STATE# P72/EXIRQ2#/AN2 P15
h
VBRK_MON 71 107 KBC_SCANOUT4 R313 10K DOCK_PE_OPNREQ#
P73/EXIRQ3#/AN3 P14 KBC_SCANOUT3 R306 10K DOCK_SYS_PWRGD#
72 P74/EXIRQ4#/AN4 P13 108
TP_P75_EXIRQ5#_AN5 73 109 KBC_SCANOUT2 R323 10K DOCK_PE_DET#
R700 0 EC_BRK_CURRENT_R 74 P75/EXIRQ5#/AN5 P12 KBC_SCANOUT1 R289 10K NETDETECT#
51 EC_BRK_CURRENT P76/AN6 P11 110
TP_P77_AN7 75 112 KBC_SCANOUT0 R273 10K SMC_LID
c
P77/AN7 P10 R274 10K BT_ON
51 EC_CS_GAIN_SEL 40 PA1/KIN9# KBC_SCANOUT[15:0] 31
41 121 R864 10K DOCK_PE_PWRGD#
23,35 PM_LAN_ENABLE PA0/KIN8# P30/LAD0 LPC_AD0 21,40,44
136 122 R346 10K SMC_ME_ALERT
23 PM_PWRBTN# P40/TMCI0/TXD2/DSERIRQ P31/LAD1 LPC_AD1 21,40,44
52 IMVP_VR_ON 137 P41/TMO0/RXD2/DCLKRUN# P32/LAD2 123 LPC_AD2 21,40,44
-s
5,23 PM_THRM# 2 P43/TMCI1 P33/LAD3 124 LPC_AD3 21,40,44
3 P44/TMO1 P34/LFRAME# 125 LPC_FRAME# 21,40,44
58 NMI_GATE PLT_RST_R R296 100
23 PM_RSMRST# 4 P45/TMRI1 P35/LRESET# 126 BUF_PLT_RST# 18,22,44,45
5 CPU_PWM_FAN 5 P46/PWX0 P36/LCLK 127 CLK_PCI_KBC 37
TP_KBC_P47 6 128
P47/PWX1 P37/SERIRQ INT_SERIRQ 23,33,40,44
5,7,9,10,16..19,22..26,28,30,32..34,38,40,44,45,49,50,52,55..58 +V3.3S 115 131 +V3.3M 13..15,23,24,35,36,45,50,56,57
21,23 H_RCIN# PB5/WUE5#/DLAD2 P82/CLKRUN# PM_CLKRUN# 23,33,40,44
SMC_RSTGATE# 116 132
PB4/WUE4#/DLAD3 P83/LPCPD# PM_SUS_STAT# 23,40,44
117 134 KBC_PROG_RX# R661 1K PM_LAN_ENABLE
p
5 SMB_THRM_CLK PB3/WUE3#/DLFRAME# P85/IRQ4#/RXD1/IRRXD
118 135 R305 10K ME_SMC_ALERT#
5 SMB_THRM_DATA PB2/WUE2# P86/IRQ5#/SCK1/SCL1 SMB_CLK_ME 23
R719 119 138
23 SMC_RUNTIME_SCI# PB1/WUE1#/LSCI P42/EXIRQ7#/TMRI0/SCK2/SDA1 SMB_DATA_ME 23
8.2K 120
23,40,45 SMC_EXTSMI# PB0/WUE0#/LSMI#
23 SMC_WAKE_SCI# 129 P80/PME# VSS1 7
130 42
o
R720 0 H_A20GATE_R P81/GA20 VSS2
21 H_A20GATE VSS3 95
TP_BS_DISA# 113 111
PB7/WUE7#/DLAD0 VSS4
t
23 PM_BATLOW# 114 PB6/WUE6#/DLAD1 VSS5 139
B 67 B
AVSS
17 KBC_PROG_TX# 133 P84/IRQ3#/TXD1/IRTXD GND_SYS_CURRENT
PC7/WUE15#/DLDRQ 87 BT_ON 41
TP_KBC_RES0# 142 88
RESO# PC6/WUE14#/LDRQ TURBO_GPIO 58
p
PC5/WUE13# 89 BATT_CONNECT# 51
46 +V5A3A_MBL_PWRGD 51 PG7/EXIRQ15#/EXSCLB PC4/WUE12# 90 SMC_LID 26,58
57 EC_VAUX_ON 52 PG6/EXIRQ14#/EXSDAB PC3/WUE11# 91 RF_KILL# 25,58
53 92 TP_PC2_WUE10#
17 ALS_CLK PG5/EXIRQ13#/EXSCLA PC2/WUE10#
17 ALS_DATA 54 PG4/EXIRQ12#/EXSDAA PC1/WUE9# 93 SMC_SHUTDOWN 55
55 94 TP_SATA_DET#1
la
5 CPU_TACHO_FAN PG3/EXIRQ11#/EXTMIY PC0/WUE8#
56 PG2/EXIRQ10#/EXTMIX
58 BATTFULL_GPIO
57 PG1/EXIRQ9#/EXTMCI1 PD7/TIOCB2/TCLKD 59 BC_SHDN 51
58 BATTCHRG_GPIO
55 NETDETECT# 58 PG0/EXIRQ8#/EXTMCI0 PD6/TIOCA2 60 DOCK_PWR_EN# 45
PD5/TIOCB1/TCLKC 61 DOCK_PE_PWRGD# 45
.
43 PF7/EXPW15 PD4/TIOCA1 62 DOCK_PE_RST# 45
23,55 SMC_ME_ALERT TP_ICHRM 44 PF6/EXPW14 PD3/TIOCD0/TCLKB 63 DOCK_PE_QSEN# 45
45 64 +V3.3A 20..26,29,39..41,44..48,50,51,55..58
45 DOCK_PE_DET# PF5/EXPW13 PD2/TIOCC0/TCLKA DOCK_HDMI_EN# 18
TP_VCHRM 46 65
PF4/EXPW12 PD1/TIOCB0 DOCK_CRT_EN# 16
47 66 +V3.3A 20..26,29,39..41,44..48,50,51,55..58
45 DOCK_PE_OPNREQ# PF3/IRQ11#/EXTMOX PD0/TIOCA0 DOCK_LAN_EN# 21,23,36
48 PF2/IRQ10#
45 DOCK_SYS_PWRGD# KBC_MDE R320 4.7K
23 ME_SMC_ALERT# 49 25
w
PF1/IRQ9# MD2 KBC_FWE R318 4.7K
50 PF0/IRQ8# FWE 26
23,45,48,56..58 PM_SLP_S3# 27 KBC_PE5 R374 4.7K
ETRST# KBC_PE4 R373 4.7K
PE4/ETMS 28
0
45,51 +VAC_IN_L +V5A 24,29,46..48,51,57 29 KBC_PE3 R372 4.7K Stuff R319 for
PE3/ETDO KBC_PE2 R371 4.7K
NO_STUFF
PE2/ETDI 30 write protect
31 KBC_PE1 R370 4.7K
PE1/ETCK
R319
C691 32 KBC_PE0 R369 4.7K
w
R751 0.1uF PE0/LID3#
24.3K
1% H8S/2104
8 16V 10%
0
NO_STUFF
A VBRK_MON_IN U58A Stuff R368 to A

3 + Oakmont Form Factor Reference Design Intel Confidential
R368
1 VBRK_MON +V3.3 27,45,49,56..58 change host address
w
2 - when sharing a
R763
4.02K
C696
1uF AD8552 flash device Title
1% 4 R272
10K
H8 2104 KBC
Q35
33 PCI_GATED_RST# 3 2BSS138 Size Document Number Rev
GND_SYS_CURRENT PCI_RST# 22,33
A
SMC_RSTGATE#
1
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
e m
C C
h
This Page intentionally Left Blank
sc
p -
t o
B B
la p
w .
w
A A
w
Title
Blank

Custom
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,45,49,50,52,55..58 +V3.3S
a
m
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,45,49,50,52,55..58
C C254 C253 C240 C
e
0.1uF 0.1uF 0.1uF
U96
21,40,42 LPC_AD0 26 LAD0 +3.3V1 10
21,40,42 LPC_AD1 23 LAD1 +3.3V2 19
h
21,40,42 LPC_AD2 20 LAD2 +3.3V3 24
21,40,42 LPC_AD3 17 LAD3 NC4 12
37 CLK_PCI_TPM 21 LCLK GPIO2 2

R276 16 3
c
4.7K 18,22,42,45 BUF_PLT_RST# LRESET# NC2
21,40,42 LPC_FRAME# 22 LFRAME# PP 7
23,40,42 PM_SUS_STAT# 28 LPCPD# GPIO6 6
23,33,40,42 INT_SERIRQ 27 SERIRQ
23,33,40,42 PM_CLKRUN# 15 CLKRUN# GND1 4
TPM_BADD
-s
9 BADD GND2 11
GND3 18
20..26,29,39..42,45..48,50,51,55..58 +V3.3A 25
GND4 C251
1 NC1
5 13 XTAL_I 10pF
R275 VSB3 XTALI_32K_IN 5%
0
BADD pin low - SMBUS address 0x2E 8 TEST_I XTAL_O 14
C241
BADD pin high - SMBUS address 0x4E
4
NO_STUFF 0.1uF SLB 9635 TT 1.2
Y3
p
32.7680KHZ
1
C245
XTAL_O 10pF
o
5%
t
B B
la p
w .
w
A A
w
Title
TPM

A
5 4 3 2 1
5 4 3 2 1
m
J31
S1 S99 PCIE_WAKE#_DOCK
S1 S99
S2 S2 S100 S100 DOCK_PWR_EN# 42
22 USB_PN8 S3 S3 S101 S101 CLK_PCIE_DOCK_OE# 37
S4 S103
o
S4 S103
22 USB_PP8 S5 S5 S104 S104 PCIE_TXP4_DOCK 22
S7 S7 S105 S105
S8 S8 S107 S107 PCIE_TXN5_DOCK 22
S9 S9 S108 S108 PCIE_TXP5_DOCK 22
SMB_DATA_DOCK
c
S10 S10 S109 S109 PCIE_RXN5_DOCK 22
S12 S12 S110 S110 PCIE_RXP5_DOCK 22
D 18 HDMI_DDC_CLK_DOCK S13 S13 S111 S111 D
.
S14 S14 S112 S112
S15 S113 +V3.3M 13..15,23,24,35,36,42,50,56,57
18 HDMI_TX1P_DOCK S15 S113 HDA_DOCK_RST# 21
S16 S114 +V1.8_LAN_M 35,36
18 HDMI_TX1N_DOCK S16 S114
S17 S115 HDA_SPKR_DOCK
18 HDMI_TX2P_DOCK S17 S115
S18 S116
s
18 HDMI_TX2N_DOCK S18 S116
S19 S19 S119 S119
18 HDMI_TX0P_DOCK S20 S20 S120 S120
18 HDMI_TX0N_DOCK S21 S21 S121 S121 LAN_MDI1P_Q_DOCK 36
S23 S122 C47 C44
16 CRT_BLUE_DOCK S23 S122
it c
Route connection to dock S24 S127 0.01uF 0.01uF
S24 S127 10% 10% +V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,49,50,52,55..58
on L5/6 with thick 16 CRT_GRN_DOCK S25 S25 S128 S128
traces S26 S26 S129 S129 SATA_RXP2 21
+V1.8_GMCH 7,9,10 S27 S130
16 CRT_RED_DOCK S27 S130 SATA_RXN2 21
S28 S28 S131 S131 SATA_TXP2 21
+V1.8 9,10,13,14,18,47,56 S29 S132 C22
16 CRT_HSYNC_DOCK S29 S132 SATA_TXN2 21
S30 S133 0.1uF
+V1.8 9,10,13,14,18,47,56 HDA_SDATAIN_DOCK S30 S133
S31 S31 S135 S135
36 LAN_LED_1000#_DOCK S32 S32 S136 S136
+V1.05S 3,4,6,9,10,20,21,24,48,54,56 S33 S137
S33 S137
5
a
S34 S139 U3
S38 Note: PE_DET# - GND in 36 LAN_MDI2N_Q_DOCK S34 S139 DOCK_RSTBTN# 55
+V1.05S 3,4,6,9,10,20,21,24,48,54,56 S35 S140 1
CRB, shorted to PE_DET# in 36 LAN_MDI3P_Q_DOCK S35 S140 DOCK_PE_OPNREQ# 42 DOCK_PE_RST# 42
S36 S141 DOCK_PERST# 4
Docking Board. 36 LAN_MDI3N_Q_DOCK S36 S141
36 LAN_LED_LINK#_DOCK S37 S37 S143 S143 DOCK_PE_PWRGD# 42 2 BUF_PLT_RST# 18,22,42,44
S38 S144 SMI#_DOCK
S38 S144 74AHC1G08
S43 S145
3
S43 S145
S44 S44 S147 S147 PCIE_TXN4_DOCK 22
R23 0 +V1.05S_MCH S45 S148
m
S45 S148
S46 S46 S149 S149 PCIE_RXN4_DOCK 22
R28 0 +V1.05S S47 S150
S47 S150 PCIE_RXP4_DOCK 22
S48 S48 S151 S151
22 USB_OC#8 S49 S49 S152 S152
C SMB_CLK_DOCK S51 S51 S153 S153 C
e
42 DOCK_PE_DET# S52 S52 S154 S154
S53 S53 S155 S155
23,42,56,57 PM_S4_STATE# S54 S54 S156 S156
S56 S56 S157 S157
S57 S158 HDA_BCLK_DOCK
18 HDMI_DDC_DATA_DOCK S57 S158
h
S58 S58 S161 S161 LAN_LED_100#_DOCK 36
+V3.3A 20..26,29,39..42,44,46..48,50,51,55..58 S60 S162
18 HDMI_TXCP_DOCK S60 S162
S61 S61 S163 S163 LAN_MDI0N_Q_DOCK 36
18 HDMI_TXCN_DOCK S62 S62 S164 S164 LAN_MDI0P_Q_DOCK 36
S64
c
S64
S65 S65 M84 M84 CLK_PCIE_DOCK 37
18 HDMI_HTPLG_DOCK
S66 S66 M126 M126 CLK_PCIE_DOCK# 37
16 CRT_VSYNC_DOCK S67 S67
S68 S68 +VAC_IN_L 42,51
s
S69 S69
S70 S70 P1 P1
16 CRT_DDC_CLK_DOCK S71 S71 P2 P2
-
S72 P3
16 CRT_DDC_DATA_DOCK
HDA_SYNC_DOCK
HDA_SDO_DOCK
S73
S74
S72
S73
S74
P3
P4 P4 Docking Audio must be
S75
S79
S77
S75
S79 3.3V when using Oakmont
p
36 LAN_MDI2P_Q_DOCK S77
36 LAN_MDI1N_Q_DOCK S80 S80 G1 G1
S85 S85 G2 G2
S86 G3 +V5 56,57
S86 G3
S87 S87 G4 G4
R485 0 +V1.8_DIMM S88 G5
o
R486 0 +V1.8 S88 G5
S89 S89 G6 G6
R487 0 +V1.8_GMCH S90 G7 C365
S90 G7
t
S91 G8 0.1uF
B S91 G8 B
S92 S92 G9 G9
23,42,48,56..58 PM_SLP_S3# S93 S93 G10 G10
23,42,48,56,57 PM_SLP_M# S95 S95 G11 G11
S96 G12 R504
55,58 PS_ON_SW# S96 G12 10K U14
p
42 DOCK_SYS_PWRGD# S97 S97 1%
23,25,26 SMB_CLK_A1 3 1A1 VCC 24
PCI-E DOCKING CONN 4
23,25,26 SMB_DATA_A1 1A2
27,42,49,56..58 +V3.3 7 2 SMB_CLK_DOCK
23,25,26 PCIE_WAKE# 1A3 1B1
74CBT3384_PD_1A4 8 5 SMB_DATA_DOCK
1A4 1B2 PCIE_WAKE#_DOCK
11 6
la
23,40,42 SMC_EXTSMI# 1A5 1B3
27,42,49,56..58 +V3.3 9
18,21,27,28 HDA_SYNC 21 HDA_SDIN3 1B4
14 10 SMI#_DOCK
18,21,27,28 HDA_SDOUT 2A1 1B5
R489 33 HDA_SYNC_R 17
18,21,27,28 HDA_BIT_CLK 2A2
R507 R491 33 HDA_SDOUT_R 18 15 HDA_SDATAIN_DOCK
2A3 2B1
.
R490 Layout Note: place series R488 33 HDA_BIT_CLK_R 21 16 HDA_SYNC_DOCK
8.2K 10K 2A4 2B2
resistors within 0.5 of 22 19 HDA_SDO_DOCK
docking switch 23,28 HDA_SPKR 2A5 2B3
20 HDA_BCLK_DOCK
2B4 HDA_SPKR_DOCK
2B5 23
42 DOCK_PE_QSEN# 1 1OE#
21 HDA_DOCK_EN# 13 2OE# GND 12
w
SN74CBTD3384
w
A A
w
Title
Docking
Not to be used with UDI enabled Docking Board Size Document Number Rev
A
5 4 3 2 1
5 4 3 2 1
V5A_MBL_PWRGD R667 0 +V5A3A_MBL_PWRGD
NO_STUFF
+V3_LDO
m
VREF2 +V3_LDO R237 0
+V5A 24,29,42,47,48,51,57 NO_STUFF
R239 0
2 3
o
Place C1247 R664 Q82 +VBATA 47,48,51,55,57
R240 C645 10K BSS138 AGND_51120
near U31.4
40.2K 1000pF C621 R217 R208
1% 5% 1000pF 0 100K
1
10%
c
VR_ALW_ENABLE 55
1
C190
D 51120_EN1 0.1uF C574 D
.
AGND_51120 10% 22UF
2
5
6
7
8
R241 AGND_51120
10K R220 R669 Q3003
1% 0 0 51120_DRVH1_R R206 0 51120_DRVH1_Q IRF7811A +V5A 24,29,42,47,48,51,57
4
NO_STUFF
51120_TONSEL
s
1
2
3
Icc-max=6A continuous
L11
51120_+V5A_MBL_Q 1 2
OCP=15A
AGND_51120
0.47uF
3.3uH
it c
+V5_LDO_FILT AGND_51120
1
51120_SKIPSEL CR4
5
6
7
8
1
C203
Q3004 C213 C210
R222 51120_VBST1 51120_DRVL1_Q 4 IRF7822 B320A 0.1uF 150uF
R679 0 10%
1
2
3
2
0 NO_STUFF
32
31
30
29
28
27
26
25
EU3
33
DRVL1
SKIPSEL
TONSEL
PGOOD1
EN1
VBST1
DRVH1
LL1
24,29,42,47,48,51,57 +V5A TH
a
+VBATA 47,48,51,55,57
R230 C633 AGND_51120 +V3_LDO
9.76k_1% 470pF AGND_51120
5% 1 24 +V5_LDO_FILT
VO1 PGND1
1
NO_STUFF NO_STUFF C607
51120_COMP1 2 23 51120_CS1_R R654 4.99K 0.1uF
+V5_LDO_FILT_RC1 COMP1 CS1 1% 10%
2
C634 51120_VFB1 3 22 +V5_LDO
m
2200PF VREF2 VFB1 VIN
NO_STUFF
4 VREF2 TPS51120 VREG5 21
5 20 R655 49.9
GND V5FILT
C 1% C
e
R231 0 6 19 C198 C196
AGND_51120
NO_STUFF VFB2 VREG3 1.0uF 10uF
7 18 51120_CS2_R R658 4.99K C197
COMP2 CS2 1% 10uF
R232 0 51120_VFB2 8 17
VO2 PGND2
h
R226 NO_STUFF +VBATA 47,48,51,55,57
0
PGOOD2
AGND_51120
DRVH2
51120DRVH2_RQ
DRVL2
13 VBST2
EN5
EN3
EN2
LL2
51120_COMP2
51120VBST2
1
C593
C597 0.1uF
VR_ALW_ENABLE_R 9
10
11
12
14
15
16
5
6
7
8
R682 C218 22UF 10%
2
30.1K 100pF Q3005
1% NO_STUFF 20..26,29,39..42,44,45,47,48,50,51,55..58 +V3.3A 51120DRVH2 R659 0 IRF7811A
s
NO_STUFF 4
+V3.3A 20..26,29,39..42,44,45,47,48,50,51,55..58
+V5_LDO_EN3
1
2
3
+V5_LDO_FILT_RC2 C207
C644 0.47uF L12 Icc-max=6A continuous
-
470pF 51120VBST2_Q 1 2
5% 3.3uH OCP=18A
1
NO_STUFF CR5
5
6
7
8
R221 0
1
Q3006 C217 + C642 + C224
p
AGND_51120 +V5_LDO R218 0 51120_DRVL2_Q 4 IRF7822 B320A 0.1uF 220uF 220uF
R674
1
10% 10% 10%
2
3
2
100K
42 +V5A3A_MBL_PWRGD
o
55 VR_ALW_ENABLE
R668
t
10K V5A_MBL_PWRGD
B AGND_51120 B
+V3.3A 20..26,29,39..42,44,45,47,48,50,51,55..58
+V3.3A 20..26,29,39..42,44,45,47,48,50,51,55..58
p
V5 Output Mode C?, R1098 V3.3 Output Mode C?, R1041 &
R380 R382
Selection & R1097 Selection R1042
R690 C225
23.7K 1000pF Fixed Output
Fixed Output
la
1% 5% STUFF
Mode NO_STUFF STUFF Mode NO_STUFF
R683 Adjustable Mode Adjustable Mode
10K STUFF NO_STUFF (default) STUFF NO_STUFF
.
(default)
1%
V5 Mode R378 R379, C222 V3.3 Mode R381 R384, C223
w
Selection & C129 Selection & C224
PROGRAMMING TABLE
Current Mode NO_STUFF STUFF Current Mode NO_STUFF STUFF
AGND_51120
PIN AGND VREF2 FLOAT +V5_LDO_FILT
AUTO-SKIP PWM D_CAP Mode D_CAP Mode
SKIPSEL AUTO-SKIP PWM STUFF NO_STUFF STUFF NO_STUFF
w
FAULTS FAULTS (default) (default)
OFF OFF D-CAP
COMP N/A N/A N/A MODE
A A
TONSEL(CH1/2) 380KHz/590KHz 290KHz/440KHz 220KHz/330KHz 180KHz/280KHz Oakmont Form Factor Reference Design Intel Confidential
w
Title
VFB1 N/A SHOULD NOT BE USED N/A 5V FIXED OUTPUT
TPS51120 System Power
VFB2 N/A SHOULD NOT BE USED N/A 3.3V FIXED OUTPUT
SWITCHER Size Document Number Rev
EN1,EN2 OFF SHOULD NOT BE USED N/A SWITCHER ON A
LDO OFF
EN3,EN5 SHOULD NOT BE USED N/A LDO ON
5 4 3 2 1
5 4 3 2 1
m
Discharge Mode R158, C101
Selection R178 R177 R360
Selection & C102
R114 0
Tracking NO_STUFF Current Mode NO_STUFF 46,48,51,55,57 +VBATA
STUFF STUFF
o
Discharge
(Default) AGND_DDR
D_CAP Mode
Non-tracking (default) STUFF NO_STUFF
STUFF C491 C116 C492
c
Discharge NO_STUFF 10uF 10uF 10uF
D 9,10,13,14,18,45,56 +V1.8 D
.
Vout = 0.9V/0.75V
Iout = 3A
R97 0 DDR_VBST_RC C124 1 2
s
+V0.9 15,56 0.1uF 10%
Vout = 1.8/1.5V
V Iout = 10A
5
6
7
8
it c
Q3007
DDR_DRVH_R R98 0 DDR_DRVH_RQ 4 IRF7811A
C121 C503 C122 C513 9,10,13,14,18,45,56 +V1.8
1
2
3
10uF 10uF 10uF 1.0uF
L20
DDR_VBST_R
DDR_LX2 1 2
1.0uH
1
a
5
6
7
8
1
C123
Q3008 CR3 0.1uF
DDR_LDR2 R96 0 DDR_LDR2_RC 4 IRF7822 B320A 10%
2
1
2
3
2
+V5A_FILT
24
23
22
21
20
19
m
R590 EU1
AGND_DDR
0 R10523 DDR_CS_RC
VLDOIN
DRVH
LL
DRVL
VTT
VBST
NO_STUFF 0
1 18 +V5A 24,29,42,46,48,51,57 C129 R115 Note: OCP set +V5A 24,29,42,46,48,51,57
VTTGND PGND
C 2 VTTSNS CS_GND 17 1000pF 5.90K point at 14A C
e
DDR_MODE_P2_HDR 3 16 10%
GND CS
M_VREF_MCH 4 MODE 15
R597 0 DDR_VTTREF_R 5 TPS51116 V5IN 14 C522 1 2
DDR_COMP_RC VTTREF V5FILT 1.0uF R595 10
6 COMP PGOOD 13
7,13,14 VDDQSNS
VDDQSET
h
Layout Note: C103,
R155 & R157 shoud be R131
NC1
NC2
place close to R123 2.05K 25 +V5A_FILT C518
S3
S5
chipset. 0 1% THRM 1.0uF
NO_STUFF
c
7
8
2DDR_VDDQSET_P2_HDR9
10
11
12
R118 DDR_COMP_RC2
0 DDR_VTTREF_RC C138 C141
AGND_DDR
0.01uF 1000pF
AGND_DDR
C135 10% 10%
0.033uF NO_STUFF NO_STUFF 20..26,29,39..42,44..46,48,50,51,55..58 +V3.3A
-s
5%
DDR_PGGOD_RU R126 10K

AGND_DDR
PM_SLP_S4# 23,56
20..26,29,39..42,44..46,48,50,51,55..58 +V3.3A
R141
p
9,10,13,14,18,45,56 +V1.8 10 1 2 10%
C594 0.1uF
1
5
U83
24,29,42,46,48,51,57 +V5A 1
o
50 PM_SYS_PWRGD
4 PM_PWROK 48
2
t
B 74AHC1G08 B
3
p
20..26,29,39..42,44..46,48,50,51,55..58 +V3.3A
la
+V3.3A 20..26,29,39..42,44..46,48,50,51,55..58
1 2 10%
C604 0.1uF C613 0.1uF
10%
5
.
U86
5
1 U90
4 5130_DDR_PWRGD 1
48 5130_PWRGD 2 4 MPWROK 7,23
2
74AHC1G08
3
74AHC1G08
3
w
50 VRPWRGD_3.3M_R Adds 3.3M to the MPWROK tree.
Needed to support G3->M1 and
DDR2 VREG
w
Moff to M1 transitions.
A A
w
Title
DDR VR

A
5 4 3 2 1
5 4 3 2 1
46,47,51,55,57 +VBATA
4,10,18,24..26,56 +V1.5S
6 5
+V1.5S
R689 332 V1.5RC C641 5600pF V1.5S_INV R248 0
1
1% C212
C220 3300pF V1.5S_FBRC R235 2.49K V1.5S_FB 0.1uF C647
1 2 1% 1% 10% 22uF AGND_5130
2
R234 10.7K Q3009B
V1.5S_TG_R 4 IRF9910 +V1.5S 4,10,18,24..26,56
o
R233
13.7K L13
1% V1.5S_BG_Q
8 7 1 2
3 3.3uH
c
+V1.05S 3,4,6,9,10,20,21,24,45,54,56
1
AGND_5130
D D
1
.
Q3009A CR11 C646 C223
R686 332 V_EV_GMCH_RC C640 5600pF V_EV_GMCH_INV 2 IRF9910 B320A 330uF 0.1uF
1% 10%
2
C639 V_EV_GMCH_FBRC R236 2.49K V_EV_GMCH_FB
2
R687 2.37K 3300pF 1%
s
1% VR3 1
2 1
+VBATA 46,47,51,55,57
R685 MBR0530 6 5
10K
it c
C623
1% 0.1uF
1
10% 46,47,51,55,57 +VBATA C188
+V5REF R211 0.1uF C571
0 22uF GMCH & ICH
V1.5S_BST
R663 10K Q3011B 10%
2
+V1.25M 7,10,37,56,57
AGND_5130
+V5REF 1
C611 0.1uF
1% R196 0
5130_OUT2_R
4 IRF9910 Core Rails
Q81 10% L10 +V1.05S 3,4,6,9,10,20,21,24,45,54,56
R675 332 V1.25M_RC C628 V1.25M_INV BAT54 8 7 1 2
1% 5600pF 3 3.3uH
a
C624 V1.25M_FBRC 2.49K +V1.25M_FB R684 R656 10K
MCH_ICH_CORE_OCP
3300pF R225 1% 0 3 R216 2.2 1%
1
R219 4.87K C605 0.1uF
5130_OUT2
1
1% 10% Q3011A CR10 + C569 C191
V1.5S_SW
C211 MCH_ICH_CORE_BG IRF9910 B320A 220uF 0.1uF
NO_STUFF
2
V1.5S_BG
0.01uF 10% 10%
V1.5SOCP
V1.5S_TG
2
4N1_FLT
4N1_LH1
R676 R688 10%
2
10K 0 AGND_5130
m
1% 1
VGMCH_SW
V1.5S_INV VR1
MBR0530 +V5REF +VBATA 46,47,51,55,57
48
47
46
45
44
43
42
41
40
39
38
37
1 2
C AGND_5130
U48 3 Q211 C
e
+V5REF +VBATA 46,47,51,55,57 AGND_5130 BAT54
OUT1_U
OUT1_D
OUT2_D
INV1
LH1
LL1
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
FLT
1 2 10% 24,29,42,46,47,51,57 +V5A
V1.5S_FB
1 36 C192 0.1uF
FB1 LL2
1
V1.5_VRON2 35 R197 2.2 VGMCH_BST C193
R247 V_EV_GMCH_INV SS_STBY1 OUT2_U 5130LH2 +V3REF 0.1uF C564 +V5REF +V3REF
3 INV2 LH2 34
3
h
10K V_EV_GMCH_FB 4 33 +V5REF 10% 22UF
2
Q32 V1.05S_VRON FB2 VIN
5 SS_STBY2 VREF3.3 32
BSS138 5130PWMSEL
6 TPS5130PT 31 C189 C584
5130CT PWM_SEL VREF5 C601 10uF 10uF
1 7 CT REG5V_IN 30
4N1_5ON 8 4 IN 1 29 1.05M_VIN 0.22uF 10% 10%
c
GND LDO_VIN
3
5130REF9 28 V1.05SNS- C194 1000pF

Controller 10%
2
Q86 R671 10K 5130VREFON REF LDO_CUR 10%

10 STBY_VREF5 LDO_GATE 27
BSS138 R670 10K 5130VREFON_3 11 26
5ONG1 STBY_VREF3_3 LDO_OUT V1.05G R198 4N1_1.25MG C559
12 STBY_LDO INV_LDO 25
1
2.2
VIN_SENSE3
AGND_5130
C627 C626 1000pF 7,10,37,56,57 +V1.25M
-s
PG_DELAY
SS_STBY3
OUTGND3
C221 0.1uF 33pF 5130_1.25_INV_LDO R639 1.21K 10%
2
OUT3_U
OUT3_D
R695 R696 0.01uF 10% 5% 1% NO_STUFF
PGOUT
2
TRIP3
0 100K C222 10% C575 1000pF R178 0.050
INV3
1
2
5
6
FB3
LH3
LL3
+V5REF 0.01uF R645 NO_STUFF 10% C558
AGND_5130
10% 5.11K 46,47,51,55,57 +VBATA Q3012 10uF
LDO_VRON TPS5130PT 1% 6 5 SI3442BDV
+V1.05M LDO 10%
13
14
15
16
17
18
19
20
21
22
23
24
1
AGND_5130 AGND_5130 C214 C205 9,56 +V1.05M
AGND_5130
R252 +V5REF R229 0 V1.25M_SS 22uF 0.1uF 3
p
3
10K V1.25MBG 10%
+V1.25M_FB
V1.25M_INV
5130PGDELAY
2
Q33 V1.25M_VRON V1.25MSW
V1.25M_OCP
5130LH3
BSS138 Q3010B
4
3
1
1 R228 R691 C632 V1.25MTG R205 0 V1.25M_TG
4 IRF9910 C560 +
4N1_1.05ON 100 10K Q31 0.01uF 0.1uF C567
o
3
BSS138 10% R207 L9 7,10,37,56,57 +V1.25M 10% 100uF

2
2
Q85 V1.25M_ON_INV
1 2.2 8 7 1 2
3
1
3
t
BSS138 3.3uH
B B
1
1.05ONG 1 Q84 C610 0.1uF C576 C183 C179
2
BSS138 AGND_5130
10% CR9 330uF 330uF 0.1uF
AGND_5130
0.01uF
1 B320A 10%
2
2
1
10%
AGND_5130
R693 R694 V1.25MBST Q3010A
2
0 100K IRF9910
p
2
2
C615
VR2
+V1.25M
10K
AGND_5130
MBR0530
2
1
0.1uF
10%
la
AGND_5130
+V5REF
23,42,45,56..58 PM_SLP_S3# AGND_5130
C602
R10524
3 Q76 1
BAT54
20..26,29,39..42,44..47,50,51,55..58 +V3.3A
5130_PWRGD
.
23,42,45,56,57 PM_SLP_M#
R681
100K R214 AGND_5130
+VBATA 46,47,51,55,57
10K
w
AGND_5130
+V3.3A 20..26,29,39..42,44..47,50,51,55..58
+V3.3A 20..26,29,39..42,44..47,50,51,55..58
w
C635 1 2 10%
0.1uF C219 0.1uF
10%
5
U93
A A
1
4 5130_PWRGD_U R692 10K
1.5_1.05_PWRGD_R 52
w
2
5
74AHC1G08 1
U50 Title
47 PM_PWROK
3
4 ALL_SYS_PWRGD 23,42 Crestline VR

2
IMVP pulls 5130 PWRGD down to 1.3V via IMVP 74AHC1G08

3
internal bleed path back to S-rails when in sub S0 5130_PWRGD 47 A

states. Buffer needed to isolate 5130 PWRGD from
IMVP6 controller. Needed for ME. Date: Sheet 48 of 64
5 4 3 2 1
5 4 3 2 1
AGND_VCORE Trace will need to be 30mil.
o m
c
Attach GND and VGFX_CORE +V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,50,52,55..58 +VBAT 17,52,53,55,56
D underneath GMCH at Graphics D
.
Interface Power Pins
5,16..18,24,26,28,30..32,34,50,52,53,56,57 +V5S
R344 0 R721 0 Connect Power ground to Controller R315 C232 C229 C227 C231
ground under the controller 10K 0.01uF 0.01uF 0.01uF 0.01uF
s
DFGT_VR_EN_A0 56 10% 10% 10% 10%
AGND_VCORE GND_GVR R10295 0
DFGT_VR_EN 7
10
NO_STUFF R880 0
DFGT_VID_0 7
C674 1.0uF
DFGT_VID_1_R R881
it c
0 DFGT_VID_1 7
DFGT_VID_0_R
GVR_PGDLY
R292
DFGT_VID_2_R C228 C649 C236 C661
SH3 R882 0 DFGT_VID_2 7 47uF 47uF 4.7uF 4.7uF
2
1 2 GVR_GNDS_R R727 30.1 GVR_GNDS DFGT_VID_3_R
NO_STUFF 1% R883 0 DFGT_VID_3 7
C256 DFGT_XTRA_VID
C249 1.0uF
R309 1000pF
1K
GVR_FB_R
10% R295
1% 0
30
31
25
26
27
28
29
GVR_VCC
1
a
GND_GVR U55
9,56 +VCC_GFXCORE
PWRGD
STDBY#
SHDN#
VID0
VID1
VID2
VID3
VID4
R310 100 R316 12.1K
5
1% C260 1% D
1000pF GND_GVR GND_GVR
10% 11 16 G
GNDS VCC Q3013
4
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,50,52,55..58 GND_GVR GVR_FB 10 24 GVR_BSTR291 0 GVR_BST_R C671 HAT2168H
m
FB BST 0.22uF S +VCC_GFXCORE 9,56
1
2
3
C688 100pF GVR_CCV 8 23 GVR_DRVH_G
CCV DH L14
MAX8776
R326 R331 71.5K GVR_TIME 6 22 GVR_SW_PHASE 1 2
10K TIME LX
C 1% 0.88uH C
e
GVR_VRHOT# 4 19
GND_GVR
VRHOT# VDD
32 20 GVR_DRVL_G
SKIP# DL
5
D R286
1
GFX_VR_PWRINR325 10K GVR_POUT 3 21 3.57K
POUT PGND 1%
h
G CR12
12 15 4 Q3014 B320A
C689 IC1 GND HAT2164H
GND_GVR 0.1uF 33 S
1
2
3
2
THRMPAD
THRM
10% R284
TON
CSN
OFS
CSP
c
REF
IC2
R285 1.78k GVR_NTC 1
NC
2
5,16..18,24,26,28,30..32,34,50,52,53,56,57 +V5S
GND_GVR
9 GND_GVR 1K
17
13
14
18
C262 0.22uF GVR_REF
s GVR_TON
GVR_THRM
GVR_CSN
GVR_OFS
GVR_CSP
GND_GVR
-
0
GVR_VCC
NO_STUFF
R332 200K
R742
1%
R716
p
13.7K R322 0
1%
C675
GND_GVR C672 0.1uF
0.22uF 10%
o
1
R301 0
R711
t
B 100K B
C677
0.01uF
2
10%
p
GND_GVR
R872 30.1K DFGT_VID_0_R GND_GVR
NO_STUFF 1%
la
R873 30.1K DFGT_VID_1_R
NO_STUFF 1%
.
NO_STUFF 1%
+V3.3 27,42,45,56..58

NO_STUFF 1%
ww Oakmont Form Factor Reference Design Intel Confidential A
w
Title
Graphics Core VR

A
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
Adds 3.3M to the MPWROK tree.
20..26,29,39..42,44..48,51,55..58 +V3.3A
5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,52,55..58 +V3.3S
m
13..15,23,24,35,36,42,45,56,57 +V3.3M
5,16..18,24,26,28,30..32,34,49,52,53,56,57 +V5S
C R283 C
e
100K
R277
R279 R281 100K
24.9K 13K
1% PM_SYS_PWRGD 47
h
1%
U95
1 OUTBOUTC 16
47 VRPWRGD_3.3M_R R298
2 OUTAOUTD 15
3 14 PP_HYST 13K
c
V+ HYST 1%
4 INA- IND+ 13
+V5S_PWRGD
Adds 3.3M to the MPWROK tree. 5
6
INA+ IND- 12
11 +V3.3S_PWRGD
+V3.3M_PWRGD INB- INC+
7 INB+ INC- 10
s
8 REF V- 9
1
C244 R299
R280 0.1uF 10K
10K LTC1444 1%
10%
-
2
1% R282 PP_REFIN R297 10K
10K
1%
VREF = 1.221V
p
R293
2.4M
t o
B B
la p
w .
w
A A
w
Title
System Power Good

A
5 4 3 2 1
5 4 3 2 1
m
46..48,55,57 +VBATA
J1
R1 10K 2
L16 2
4 1 VAC_BRCK_IN 1 3
o
+AC_INPUT 3
55 BC_ACOK_BATT
3
3 2 BRCK_IN_GND 4 5
Q2 GND MECH1 +VAC_IN_L 42,45
MECH2 6
BSS138 1k@100MHz
1 JPD1041-W22-TR
2 1
c
CR1 RB081L-20
2
20..26,29,39..42,44..48,50,55..58 +V3.3A +VAC_IN
D R425 10K D
.
Q3015
42 BC_ACOK 3
5 2
3
1
Q3 R15 6.65K R440 1K SI7483ADP
BSS138 C4 C1 1% 1% C15 C322 C8 C10
s
1 22uF 0.1uF R3 C7 22uF 22uF 22uF 22uF
4
10% 100K 0.1uF
BC_DCIN AGND_BC 1% 10%
1 3
2
+VBC_LDO Q4 BAT54 ACOK#_R
R18 10K C6
it c
1uF
3
10% R2
+VBC_LDO BC_BATT Q5 100K
BSS138 1%
42 BC_SHDN 1
AGND_BC
+VBC_LDO EU2005 BC_ACOK#
1 C319
2
R456 R439 R455 R447 10K BC_CELLS DCIN 1uF
17 CELLS
41.2K 130K 100K NO_STUFF 1% 10 BC_ACIN +VBC_LDO
1% BC_ACOK# ACIN
11 ACOK#
2 R433 33
BC_SHDN# LDO AGND_BC
8 SHDN#
22 BC_DLOV 1 Q51 3
BC_REFIN_D
DLOV
5
AGND_BC
BC_REFIN 12 BAT54 D
a
+VBC_REF REFIN BC_BST R8 0 BC_BST_R
1 3 BST 24
Q6 BAT54 +VBC_REF 4 G
REF BC_DHI R432 0 BC_DHI_R Q3016
DHI 25 4
BC_CLS 3 HAT2168H
+VBC_LDO CLS BC_LX S
23
1
2
3
R14 10K BC_VCTL LX
15 VCTL
R448 C331 R16 R431 R17 21 BC_DLO R9 0 BC_DLO_R
DLO
1
49.9K 0.1uF 49.9K 45.3K 37.4k_1% BC_ICTL C12
1% 1% 1% 13 ICTL
20 0.1uF
BC_ICHG PGND 10%
9
2
ICHG BC_CSIP
m
CSIP 19
BC_IINP 28 IINP BC_CSIN
CSIN 18
BC_CCV 7 CCV BC_CSSP
CSSP 27
AGND_BC
R437 C21 BC_CCI 6 C327
20K CCI
C C18 R10 R438 C329 0.1uF
CSSN 26 BC_CSSN 1 2 10% 1 20.1uF C
GND2
0.01uF 49.9K 49.9K 0.01uF 10% BC_CCS 5 C13 0.1uF 10%
GND
e
10% 1% 1% 10% CCS BC_BATT
BATT 16
1
D BC_CSIP 1 2 10%
R13 R12 R11 MAX8724 CR2 C17 0.1uF
29
14
25.5K 0 178 G MBRS130LT3 BC_CSIN 1 2 10%
1% 1% Q3017 C19 0.1uF
4
1
BC_CCS_C1 R4 HAT2164H BC_CSSP 1 2 10%
2
AGND_BC AGND_BC 0
BC_CCV_C
R436 R7 R6 R435 R434 S C325 0.1uF

BC_CCI_C
1
2
3
2
+VBC_LDO +VBC_REF 0 10 10 10 10 BC_CSSN 1 2 10%
L17 C324 0.1uF
3.3uH BC_BATT 1 2 10%
2
C11 C326 AGND_BC
C20 0.1uF
4.7uF 1.0uF R5 C323
20K 0.1uF C332 C330 C328
1
c
10% 0.1uF 0.022uF 220pF
10% 10% 10%
AGND_BC
AGND_BC AGND_BC
AGND_BC AGND_BC AGND_BC
-s
AGND_BC
R21 0.020 R454 0.005 +V_BC_OUT
1%
C33 C32 46..48,55,57 +VBATA

10UF
10UF
BC_CSIN_CSSP_R R20 0.005
1%
1
C30 C344 C29 C348
47uF 0.1uF 47uF 22uF C347
p
10% 10UF
2
20..26,29,39..42,44..48,50,55..58 +V3.3A
BC_THERMA R31 1.74K

R461 1%
o
470
BATTCONN_PU
t
B B
J4
1 +VCHGR_OUT DIS#
1
2
p
2 CHG
3 3
3
4 DIS# 2
4 Q57 Q56
5 5 SMB_BS_CLK 39,42
6 BSS138
6 SMB_BS_DATA 39,42
7 BC_THERMA 1
7 42 BATT_CONNECT#
8 BAT54C
8 BATT_CON1
9 3
la
2
9 R464 100K
Oakmont_batt R465
1M
R466
10K
1
.
CHG
System Current Sense Amp (6A Dynamic Range) H8 ADC Reference

+V5A 24,29,42,46..48,57
w
(Place close to H8) (Place very close to the EC)
20..26,29,39..42,44..48,50,55..58
42 +VREF_ADC 24,29,42,46..48,57 +V5A +V3.3A
42 +VREF_ADC
R740
U57 22 R367
475
3.3V ADC reference
1 8 8 R754
+V_BC_OUT SHDN# GSEL 1% 0
w
2 RS- VCC 7
+VBATA 3 6 MAX4072_OUT R739 20K MAX4072_OUT_RC 5 U58B NO_STUFF
RS+ OUT +
4 5 MAX4072_REFIN 7
GND RFIN EC_BRK_CURRENT 42
6 -
MAX4072 C686
C257 C687 1uF AD8552
A 0.1uF 0.1uF C261 4 A
10%
16V
10% 22UF
w
1
LM4040
The precision ADC and and 3.3 ADC reference
optons are mutually exclusive. DO NOT STUFF Title
3.0V Precision ADC BOTH AT THE SAME TIME OR THE PRECISION C274
GND_SYS_CURRENT
42 EC_CS_GAIN_SEL
Reference circuit Q42 REFERNCE COULD BE DAMAGED. C692
22UF
0.1uF
10%
System Charger VR
R307 0 2
Current Sense Range
0 - 3A: EN_CS_GAIN_SEL = 3.3V

0-6A EN_CS_GAIN_SEL = 0V
GND_SYS_CURRENT
GND_SYS_CURRENT
A
5 4 3 2 1
5 4 3 2 1
CPU VCC_Core VR and MUX Buffer

5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,55..58 +V3.3S
o m
c
D D
5,16..18,24,26,28,30..32,34,49,50,53,56,57 +V5S
LAYOUT NOTE: PLACE
.
C159 820pF 6260_FB_C Q2C5 AS CLOSE TO
C543 Q3C4 AS POSSIBLE
s
C803 1500pF R621
180pF 10% 15
10% 1% Q3018 +V5S 5,16..18,24,26,28,30..32,34,49,50,53,56,57
1 5
6260_COMP_R
H_PROCHOT# 3
it c
R620 1.5K 6260_FB_R GND1 TOVER#
2 GND2
1% +VBAT 17,49,53,55,56 3 4
HYST VCC
MAX6501 C120 C127
1
C529 2.2uF 0.1uF
R163 0 1.0uF R156 10% 10%
1
10% 10 Temperature Monitor
C146 R608
AGND_VCORE
R147 1000pF 84.5K EU20
2
a
6.98K 10% 1% 6260_VDIFF 11 20 the ISL6260 -002 part
1% 6260_FB VDIFF VDD can be used as an
10 FB 3V3 39
2 6260_COMP C530 alternate. (iPN
9 COMP
6260_VW 8 1.0uF C74499-002
VW 6260_VIN 10%
3,7,21 H_DPRSTP# 37 DPRSTP# VIN 18
AGND_VCORE
Connect from ICH & daisy chain 27
PWM1 PWM1 53
m
through CPU - Do not 'T' 23
ISEN1 ISEN1 53
4 H_VID6 34 VID6
C
4 H_VID5 33 VID5 PWM2 26 PWM2 53 C
32 22
e
4 H_VID4 VID4 ISEN2 ISEN2 53
4 H_VID3 31 VID3
4 H_VID2 30 VID2
4 H_VID1 29 VID1 FCCM 24 FCCM 53
4 H_VID0 28 VID0
R110499 PM_DPRSLPVR_IMVP6
h
7,23 PM_DPRSLPVR 36 DPRSLPVR
1% 1 25
3 PSI# PSI# PWM3 PWM3 53
48 1.5_1.05_PWRGD_R 2 PGD_IN ISEN3 21 ISEN3 53
23 VR_PWRGD_CLKEN# 38 CLK_EN#
35
c
42 IMVP_VR_ON VR_ON
40 PGOOD
7,23 DELAY_VR_PWRGOOD
4 VCCSENSE 12 VSEN
4 VSSSENSE 13 VRTN VSUM 17 VSUM 53
-s
4 7 6260_OCSET
6260_SOFT VR_TT# OCSET R165
6 SOFT
C540 0.01uF 6260_RBIAS 3 16 35.7K
10% 6260_NTC RBIAS VO R606 1%
5 NTC
14 13.7K R884
DROOP 1% 45.3K
1%
10K
19 VSS 1%
41 GND DFB 15
VSUM_R
p
140K6260_RBIAS_R R127
J10 .
1
1 2 R602
100K 6260_DFB R155 C545 C157
NO_STUFF C143 1% 100K .022uF .01uF
o
0.015uF NTC 10%
R75
R75 R79
R79 10% R614
NO_STUFF
NO_STUFF
2
27.4 27.4 10K
t
B 1% B
R164
71.5K
VCC_PRM 53
1%
Absolutely No Stuff 1%
p
(Change Field)
C802
0.1uF
DROOP
R598
Place near C160 10%

Controller 330pF
la
Layout Note: Use
27.4 Ohm routing AGND_VCORE
for Vssense and

Vccsense
.
AGND_VCORE
R592 0
AGND_VCORE

A
w
Title
IMVP-6

A
5 4 3 2 1
5 4 3 2 1
6208_1_BOOT_U3B3_R
m
R112
0
+VBAT 17,49,52,55,56
+V5S 5,16..18,24,26,28,30..32,34,49,50,52,56,57
6208_1_BOOT_U3B3
o
C118 C150 C154 C161 C158 C532 C547 C148 C804
c
1.0uF 0.01uF 0.01uF 0.01uF 0.01uF 47uF 47uF 4.7uF 4.7uF
5
D D
D 10% 10% 10% 10%
.
C125
0.22uF
G
U27 10%4 Q3019
6 2 HAT2168H +VCC_CORE 4,54,56
s
VCC BOOT S
52 FCCM 7
1
2
3
EN L6
UGATE 1 6208_1_UGATE
6208_1_PHASE_U3B3
it c
Phase1 0.45uH
PHASE 8
1
3 5 6208_1_LGATE R172
52 PWM1 PWM LGATE
5
4 D D R161 R168 10_1%
GND CR8 76.8K 10.7K
G G B320A 1% 1%
4 Q3020 4 Q3021 C528 LAYOUT NOTES:
2
a
+V5S 5,16..18,24,26,28,30..32,34,49,50,52,56,57 HAT2164H HAT2164H 0.22uF DCR1_RC R132 0 Place near Controller
S S 10%
1
2
3
1
2
3
Place R2N19 & R2P4 right
6208_2_BOOT_U2C2_R
NO_STUFF R135 0 next to each other. Route a

VCC_PRM 52
NO_STUFF
R76
single trace from the input
m
0 pad of the inductor and T at
52 FCCM ISEN1 52
the resistors. --> Do not
6208_2_BOOT_U2C2
C
VSUM 52 use plane flood. This C
0
C84
e
1.0uF +VBAT 17,49,52,55,56
applies for R2P15 & R2P14
and R2P9 & R2P11 as well.
C105 C111 C108 C113 C453 C486 C102
5
D
R526
C90 0.01uF 0.01uF 0.01uF 0.01uF 47uF 47uF 4.7uF
h
Place CR3C1 near Q3C3
0.22uF 10% 10% 10% 10%
U18 G and Q3C4. Route sharing
10%
6 2 4 Q3022 the ground and switch
c
VCC BOOT
FCCM_R7
EN
HAT2168H nodes with low side FETs.
1 6208_2_UGATE S L4 This applies for CR2C1 and
1
2
3
UGATE
CR2C2 as well.
-s
Phase3 8 6208_2_PHASE 0.45uH
PHASE
5
D
1
5
1
3 5 6208_2_LGATE D R150 Place the 0402 caps near
52 PWM3 PWM LGATE
4 G CR7 R145 R140 10_1% the drain of the high side
DCR2_RC
GND G Q3024 B320A 76.8K 10.7K
4
4 Q3023 HAT2164H 1% 1% FETs for each phase.
0
p
To Enable Two-Phase HAT2164H S NO_STUFF C539
2
1
2
3
2
0.22uF R149 0
NO_STUFF
NO_STUFF
operation (Disable S
1
2
3
Phase-3), Remove 10% Place near Controller
o
6208_3_BOOT_U2C1_R
R2C7, and Stuff

R552
R528
R148 0
VCC_PRM 52
R2B16, and Stuff NO_STUFF
t
B B
R2P17” R50
0 ISEN3 52
+V5S 5,16..18,24,26,28,30..32,34,49,50,52,56,57
VSUM 52
6208_3_BOOT_U2C1
+VBAT 17,49,52,55,56
p
C43
1.0uF C70 C72 C66 C69 C398 C410 C58 C63
0.01uF 0.01uF 0.01uF 0.01uF 47uF 47uF 4.7uF 4.7uF
la
5
D 10% 10% 10% 10%

C49
0.22uF G
.
U11 10% 4 Q3025
6 2 HAT2168H
VCC BOOT S
52 FCCM 7
1
2
3
EN L1
UGATE 16208_3_UGATE
w
Phase2
PHASE 86208_3_PHASE 0.45uH
2
3 5 6208_3_LGATE R125
52 PWM2 PWM LGATE
4 R105 R117 10_1%
DCR3_RC
GND
5
D D CR6 76.8K 10.7K
w
1% 1%
G G
1
A 4 4 B320A C534 0.22uF R144 0 A

Q3026 10%
2
HAT2164H S Q3027 S
w
1
2
3
1
2
3
HAT2164H Title
NO_STUFF R143 0
NO_STUFF IMVP-6 Core VR
52 VSUM Size Document Number Rev

52 ISEN2
Place near Controller A
52 VCC_PRM
5 4 3 2 1
5 4 3 2 1
o m
c
D D
.
Vccp Core Decoupling
s
3,4,6,9,10,20,21,24,45,48,56 +V1.05S
it c
Place these inside socket
C531 C422 C421 C501 C502 C397 cavity on L8 ( North side
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10% 10% 10% Secondary)
Vcc Core Decoupling
4,53,56 +VCC_CORE
a
m
Place these inside socket C790 C791 C494 C505 C510 C442 C451 C792 C419 C793
cavity on L8 ( North side 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
C C
Secondary)
h e
Place these inside socket C425 C428 C794 C795 C796 C481 C493 C504 C797 C511
cavity on L8 ( South side 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
Secondary)
s c
C776 C777 C778 C779 C780 C781 Place inside CPU socket
10uF 10uF 10uF 10uF 10uF 10uF cavity of L1(North side
-
Primary)
p
Place inside CPU socket
C782 C783 C784 C785 C786 C787 cavity of L1 (South side
10uF 10uF 10uF 10uF 10uF 10uF Primary)
t o
B B
p
South Side Secondary C430 C798 C799 C800 C460 C801 North Side Secondary
330uF 330uF 330uF 330uF 330uF 330uF
10% 10% 10% 10% 10% 10%
NO_STUFF NO_STUFF
la
Takasago Low ESL Capacitors
w .
w
A A
w
Title
CPU Decoupling

A
5 4 3 2 1
5 4 3 2 1
m
46..48,51,57 +VBATA
o
+ C341 R30 17,49,52,53,56 +VBAT
15uF 390K Q3028
c
3 8
D 2 7 D
.
C28 0.33uF 1 6
5
SI4425DY + C27 + C343 + C342
15uF 15uF 15uF 46..48,51,57 +VBATA
4
s
R32 PWRONLATCHG
1M
it c
R29 R40 R481
100K 100K 100K
Power
Button Latch
3 Q7 1 PS_LATCH# SHUTDWN#
45,58 PS_ON_SW#
BAT54
3
3 Q58 1 Q59 Q8
a
BAT54 BSS138 BSS138
1 1
+V3.3A 20..26,29,39..42,44..48,50,51,56..58
2
C353 1000PF
R474 R470
100K 100K
43K
10%
m
NO_STUFF
3
PS_PWRBTN
SMC_ONOFF# 42
Q60
R473
Force Shutdown BSS138
C Either insertion of AC Q9 1 C
42 SMC_SHUTDOWN
e
or button press latch BSS138
1
2
3
51 BC_ACOK_BATT will assert enable of
3
1.5A & V3.3A
2
2 Q61 Q10 R475
h
BSS138 BAR43S 100K
Q50
Active high BAT54C
1
1
means AC present
2
3
c
from the Battery VR_ALW_ENABLE 46
46..48,51,57 +VBATA
charger
-s
SHUTDWN# 1
Net Detect
R753 R759 +V3.3A 20..26,29,39..42,44..48,50,51,56..58
100K 100K
Net Detect
Button Latch R741
26 ND_SW# 100K Signals EC of a net
p
3 Q401 ND_SW_LEFT ND_SW_RIGHT
Active high means BAT54
detect button event.
button press detect and NETDETECT# 42
3
latch from start up Q44 Q43 Q41
o
BSS138 BSS138 BSS138 Q39 3.3V Net Detect Level Shifter
circuit 100K pull up to 1 1 1 BSS138
t
B +VBATA on this page 1
B
1000PF
2
2
43K
10%
SMC_NET_DETECT: Net
NO_STUFF
2
Detect trigger signal
to ICH8. Also clears
C694
R756
p
SMC_ME_ALERT 23,42
netdetect button
latch.
. la
20..26,29,39..42,44..48,50,51,56..58 +V3.3A
w
5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,56..58 +V3.3S
R471 10K
C352
U75 0.01uF
1 4 10% 1 2 10%
w
GND VCC C356 0.1uF
5
U74
2 3 MASTER_RESET# 1
45 DOCK_RSTBTN# IN OUT
4
A PM_SYSRST# 23 A
MAX6816 2
Place R1523 R469 100K
NO_STUFF
R472 0
w
74AHC1G08
Title
3
in accessible
location 3,20 ITP_DBRESET# Start Up Sequence

A
5 4 3 2 1
5 4 3 2 1
o m
+V3.3 27,42,45,49,57,58
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55,57,58
R200
c
R402 100
100 1%
D 1% D
.
17,49,52,53,55 +VBAT
3,4,6,9,10,20,21,24,45,48,54 +V1.05S PP_V3SDIS PP_V3DIS
3
4,10,18,24..26,48 +V1.5S
1 Q102 Q24
s
BSS138 BSS138
Q3029 Q87 1 1
6 BAT54
5 4
2
it c
2
3
1
SI3442BDV
VBATA_DISCHARGE
3
5,16..18,24,26,28,30..32,34,49,50,52,53,57 +V5S +V1.25S 10,24,57 +V5 45,57
C233 R698
a
22UF 100K R680 R666 R641
100 470 100
1% 1%
PM_SLP_S3 PP_V5SDIS PP_V1.25SDIS PP_V5DIS
3
Q80 Q79 R651 Q72
3
BSS138 BSS138 100K BSS138
m
Q93 1 1 1
BSS138 R749
1 1M
23,42,45,48,57,58 PM_SLP_S3#
2
C C
2
e
PP_S4GT
15,47 +V0.9
+VCC_GFXCORE 9,49 9,10,13,14,18,45,47 +V1.8
h
4,10,18,24..26,48 +V1.5S R653
1M
R108 R600
100K 221 R458
R209 1% 75
c
47 R227
47 PP_V0.9DIS
3
PP_GFXCOREDIS Q73 Q69 PP_V1.8DIS
3
3
+VCC_CORE 4,53,54 PP_V1.5SDIS BSS138 BSS138
-s 3
Q26 1 DDR_DIS 1 Q54
BSS138 Q28 BSS138
1 BSS138 1
2
3
1
R39 Q20
2
2
47 BSS138
2
23,42,45,57 PM_S4_STATE# 1
p
PP_VIMVPDIS
2
3
PM_GFXCORE_BUF
Q13
BSS138
1
o
23,47 PM_SLP_S4#
2
t
13..15,23,24,35,36,42,45,50,57 +V3.3M +V1.25M 7,10,37,48,57
B B
20..26,29,39..42,44..48,50,51,55,57,58 +V3.3A
R743 R734
100 470
p
1%
PP_V3MDIS
3
R215
100K Q94 PP_V125MDIS
3
+V1.05S 3,4,6,9,10,20,21,24,45,48,54 BSS138
PP_V33M_DIS 1
la
Q38 +V3.3M_CK505 37,57
+V1.05M 9,48 1 BSS138
2
+V3.3A20..26,29,39..42,44..48,50,51,55,57,58 R43
3
470 R376
2
470
.
Q27
BSS138 R628
1 R37 PM_SLP_S3_BUF_R 470
49 DFGT_VR_EN_A0 100K PP_V33MCKDIS
3
3
R388
2
Q63 10K PP_V105M_DIS Q3038 Q98
3
BSS138 BSS138 BSS138
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PM_SLP_S3_BUF 1 Q71 1 1
BSS138 LAN_WOL_EN 23,42,57
3
PM_SLP_M 1
2
2
Q12
BSS138 R10517
2
3
1 100K
23,42,45,48,57,58 PM_SLP_S3#
Q100
w
BSS138 R389
2
1 1M
23,42,45,48,57 PM_SLP_M#
A A
2
w
Title
DISCHARGE CIRCUITS

A
5 4 3 2 1
5 4 3 2 1
20..26,29,39..42,44..48,50,51,55,56,58 +V3.3A
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55,56,58
24,29,42,46..48,51 +V5A +V1.25M 7,10,37,48,56
m
5,16..18,24,26,28,30..32,34,49,50,52,53,56 +V5S +V1.25S 10,24,56
8 Q3030 Q3031
7 3 IRF7811A 8 8 Q3032
6 2 7 3 7 3
o
5 1 6 2 6 2
5 1 5 1
46..48,51,55 +VBATA IRF7822 IRF7822
4
c
4
R10531 100K
VBATA_SLEEP 18
3
D D
.
R278 Q91 C168 Net Detect VAUX Switch
100K BSS138 0.01uF
1 10%
+V3.3A 20..26,29,39..42,44..48,50,51,55,56,58
20..26,29,39..42,44..48,50,51,55,56,58 +V3.3A
s
2
45,56 +V5
3
27,42,45,49,56,58 +V3.3 +V3.3_PCIE_VAUX 25
Q90 8 Q3033 8 Q3035
BSS138 7 3 IRF7811A 7 3
it c
1 6 2 8 Q3034 6 2
23,42,45,48,56,58 PM_SLP_S3#
PS_S3CNTRL 5 1 7 3 IRF7822 5 1
6 2 46..48,51,55 +VBATA IRF7822
2
5 1
20..26,29,39..42,44..48,50,51,55,56,58 +V3.3A
4
R213 100K SLPS4#_CONTROL R652 100K VAUX_G_SWITCH
4
3
1
R665 C570
100K Q25 0.1uF R672
3
BSS138 10% R673 100K C598
2
a
PS_S4CNTRL 1 100K Q74 0.01UF
BSS138 10%
3
VAUX_S3M_OK 1
2
Q75
BSS138
2
3
23,42,45,56 PM_S4_STATE# 1
3
Q78
Q77 BSS138
m
2
BSS138 1
23,42,45,48,56,58 PM_SLP_S3# 1
2
20..26,29,39..42,44..48,50,51,55,56,58 +V3.3A
2
C C
e
+V3.3M 13..15,23,24,35,36,42,45,50,56
8 Q3036
42 EC_VAUX_ON
h
7 3 IRF7822
46..48,51,55 +VBATA 6 2
5 1
c
R201 100K V3M_G_SWITCH
4
R251 C199
3
100K 0.01uF
Q89 10%
s
BSS138
SLP_S3M_OK 1
-
3
2
3
Q88
BSS138 Q34
1 BSS138 Q36
23,42,45,48,56 PM_SLP_M#
1
p
LAN_WOL_EN 23,42,56
2 3 WLAN_GPIO_R R10518 0 WLAN_GPIO 25,58
26 NETDETECT_LED
2
Added for WOL in

2
S3/Moff. Enabled by For Golan

BSS138
20..26,29,39..42,44..48,50,51,55,56,58 +V3.3A
CLGPIO3=LAN_WOL_EN. support no
o
1
stuff
8 Q3037
R869.
t
7 3 IRF7822+V3.3M_CK505 37,56
B 6 2 PS_S3CNTRL B
5 1
46..48,51,55 +VBATA
p
4
R758 100K PM_SLP_M_SW
R776 C272
3
100K 0.01uF
la
Q96 10%
BSS138
PM_SLP_M_Q
1
3
.
2
Q99
BSS138
1
2
w
Added to isolate CK505 from 3.3M
when WOL/Moff is enabled.
w
A A
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Title
Sleep control

A
5 4 3 2 1
5 4 3 2 1
20..26,29,39..42,44..48,50,51,55..57 +V3.3A
SMC_INITCLK_U
m
+V3.3A 20..26,29,39..42,44..48,50,51,55..57
J20
14 14 14 14 1 2 R223
C763 U64A U64B U64E U64C 100K
0.1uF 1X2_2MM
.
o
NMI_GATE# R847 1MSMC_INIT_CLK1 1 2 SMC_INIT_CLK2 3 4 SMC_INIT_CLK3 11 10 5 6 R677 0
3 SMC_INITCLK 42
3
Q104 14 NO_STUFF
U64D Q49 74HC04 74HC04 C764 74HC04 74HC04
VCC
BSS138 4.7uF
SMC_RST#_DR855 SMC_RST 7 7 10% 7 7
2 4.7K 9 8 1
c
RST#
GND
D 74HC04 SMC_INIT_CLK4 R849 100K SMC_INITCLK# D
2
.
7 Boot Block
MAX809 Programming J20 R681
1
Place J20, R225
3
NORMAL (1 2) STUFF
Q103 &R681 in an
s
BSS138
accessible Program NO_SHUNT NO_STUFF
42 NMI_GATE 1
location
2
it c
SMC_RST# 42
20..26,29,39..42,44..48,50,51,55..57 +V3.3A +V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..57

27,42,45,49,56,57 +V3.3
3
3
3
Q11 Q55 Q45 Q105
2
Q95 Q14 Q83 Q92 BSS138 BSS138 1 SI2307DS BSS138

Q3039 BSS138 BSS138 BSS138 BSS138 1 1 1
1 SI2307DS 1 1 1 1
23,42,45,48,56,57 PM_SLP_S3#
3
2
2
m
3
2
LED_WLAN_R LED_WWAN_R HDD_LED_R BT_LED_R
LED_CAPS_R LED_NUM_R LED_BATT_LOW_R LED_BATT_FULL_R C51
S3_LED_R 470pF
5%
C R441 R450 R444 R442 C
e
R443 R451 R445 R452 33 33 33 33
R453 33 33 33 33
33
LED_WLAN LED_WWAN HDD_LED BT_LED
LED_CAPS LED_NUM LED_BATT_LOW LED_BATT_FULL
25,57 WLAN_GPIO
h
S3_LED
42 KBC_CAPSLOCK 25 WWAN_GPIO
42 KBC_NUMLOCK 21 SATA_LED#
42 BATTCHRG_GPIO 41 BT_ACTIVE
42 BATTFULL_GPIO
c
-s
+V3.3S 5,7,9,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..57
R449
2.2K
p
+MIC C337 1.0uF
Power Good & Turbo Mode
MIC_CHASSIS 28
LED Driver
+V3.3A 20..26,29,39..42,44..48,50,51,55..57
Nut Tree Header
t o
C762
B 0.1uF B
J3 14
5
1 2 U63 U64F
AGND 3 4 PS_ON_SW# 45,55 7,19,22,25,26,40 PLT_RST# 1
LED_TURBO LED_PWR_GD
p
5 6 4 13 12
7 8 LED_TURBO 2
26 S3_LED 42 TURBO_GPIO
LED_PWR_GD 9 10 74HC04
LED_BATT_LOW 26
11 12 HDD_LED 74AHC1G08
3
26 LED_BATT_FULL LED_NUM LED_CAPS 7
13 14
15 16 BT_LED
la
25,42 RF_KILL# LED_WWAN LED_WLAN
17 18
+MIC 19 20 SMC_LID 26,42
CON20_FPC_ZIF_VT
w .
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Mounting Holes
A MT1 MT11 MT4 MT7 MT6 Oakmont Form Factor Reference Design Intel Confidential A
1 1 1 1 1
Title
w
Nut Tree LED Drivers
MT8 MT2 MT3 MT5 MT9 MT10
1 1 1 1 1 1
NO_STUFF
A
5 4 3 2 1
5 4 3 2 1
Steps 1 leads to either 1BAT for battery only Oakmont Mobile Power On Sequence
m
mode or 1AC for AC mode. 5AC leads to 5a
to 5b to 5c to 6. Battery mode requires +VBAT +VBATA Battery OR AC
SHT 51
o
button press to begin power up. AC mode insertion cause 1
requires button press to boot. Sequence waits here for

1 Battery
1BAT Charger
c
D
button press before Pack D
1AC Circuit
.
doing step 1BAT = 5AC.
5AC Startup AC
PM_SLP_S3# BC_ACOK_BATT SHT 51
Only AC insertion
PS_ON_SW# Circuit Adapter
s
causes 1AC
7 7 +V5S +VBATA PG 54 SHT 51
+V1.8S_HDMI
it c
+VBATA SHT 55
+V1.8 6 +V5A +V3.3A
SWITCH
SMC_ONOFF#
SHT 18 3 +V5A SYSTEM 5a
7 +V3.3S +V3.3A VR VR_ALW_ENABLE MAX-809
SLP_S3 +V3.3A
VBATA_SLEEP
2 SHT 43 ICH8
a
SWITCHES +V1.25M 3 SHT 46
7 +V1.25S
SHT
SHT 57 4
7 21,22,23,24
+V5A3A_MBL_PWRGD
PWRGD
+V3.3_PCIE_AUX 7 PM_S4_STATE# +VBATA H8 SMC SMC_RST#_D
+V3.3A
m
SHT 42 & 44 MPWROK CLPWROK
SWITCH
7 +V5 6 +V5A 14
C SHT 57 C
5b
e
PM_PWRBTN# CLK_PWRGD
7 +V3.3 SLP_S4 +V3.3A
CLGPIO3/GPIO9
SWITCHES EC_VAUX_ON
OR
VRMPWRGD
SHT 57
RSMRST#_PWRGD PM_RSMRST# 5c 17 H_PWRGD
PM_SLP_S4# +VBATA
PM_SLP_S3#
c
(300ms MAX)
EC_VAUX_ON 7 +V1.8
3a IMVP_VR_ON 99ms DELAY PM_ICH_PWROK
6 PWROK
11 16
-s
10
7 +V0.9
DDR VR 6 SHT 23 18
to line
PLT_RST#
+V3.3M SHT 47 switches
p
PWRGD VRPWRGD_3.3M_R PM_SLP_S4#
SHT 50 +V3.3A 6 PM_S4_STATE# 6 to DDR VR
o
+V5S
DDR_PGGOD_RU
6 PM_SLP_S3#
SYSTEM 8
t
B B
+V3.3S 6 PM_SLP_M# +VCC_GMCH_CORE, +VCC_CORE,
VR POWER SHT 47 MPWROK 9 LAN_WOL_EN +VCCP +VCCP
GOOD to ICH & MCH +V3.3M +V3.3A
p
MONITOR 7 SWITCH
+V3.3A +V3.3M_CK505 SHT 57 OR PWRGD
5130_PWRGD
7 SWITCH
CRESTLINE
la
9 SHT 57 SHT MCH CPU
SHT 47 PM_PWROK 19 H_CPURST#
8 PM_SYS_PWRGD
6,7,8,9,10,11
.
+VBAT PWROK
11
ALL_SYS_PWRGD
SHT 48
CLK_PWRGD 14 +VCC_CORE IMVP_VR_ON MPWROK
CLPWROK SHT 3,4
+V3.3M +V1.5S +V1.25M
w
12 7
ICH LOGIC 7 GVR_VR_EN
CK505 ENABLE VR_PWRGD_CLKEN#
ENABLE PGD_IN
+V1.05S
+VBAT
GFX VR
+VCC_GFXCORE
+V1.05M
System VCCP 7
w
SHT 49
IMVP CPU MCH,ICH CORE LDO 7
A
Clock +V3.3S 13 +V3.3A A
CORE VR Oakmont Form Factor Reference Design Intel Confidential
SHT 37 8 5130_PWRGD
w
Title
+V3.3S SHT 52 10 POWER SEQUENCING TIMING BLOCK DIAGRAM
DB200 PM_PWROK SHT 48
CLOCK EN 15 DELAY_VR_PWRGOOD
A
BUFFERS VR_PWRGD_CLKEN
SHT 38
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
This Page intentionally Left Blank
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a
m
C C
h e
sc
p -
t o
B B
la p
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A A
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Title
Revision History

A
5 4 3 2 1
ECO# OAK128: Pages 25 and page 38, swapped every instance of CLK_PCIE_MINICARD2, CLK_PCIE_MINICARD2#, &
CLK_MINICARD2_OE# to CLK_PCIE_MINICARD1, CLK_PCIE_MINICARD1#, & CLK_MINICARD1_OE#
respectively.
5 4 3 2 1
o m
c
D D
s.
it c
J3000
1 1
2 2
3 3
NT_GND NT_AGND
4 4
5 5
6 NT_PS_ON_SW#
6 NT_S3_LED
7 7
8 NT_LED_TURBO R3001 33 NT_LED_TURBO_R
a
8 NT_LED_PWR_GD R3000 33 NT_LED_PWR_GD_R
9 9
10 NT_LED_BATT_LOW
10 NT_LED_BATT_FULL
11 11
12 NT_HDD_LED
12 NT_LED_NUM
13 13
14 NT_LED_CAPS
14 NT_RF_KILL#
15 15
16 NT_BT_LED
m
16 NT_LED_WWAN
17 17
18 NT_LED_WLAN
18 NT_+MIC
19 19
C 20 NT_SMC_LID C
20
e
FPC_ZIF_RA
c h
s
CR3007 CR3008
1
MIC3000 CR3000 CR3001 CR3002 SW3001 OR/GRN OR/GRN SW3000
20Hz-16KHz BRIGHT GREEN BRIGHT GREEN BRIGHT GREEN Micro_Push_Button CR3003 CR3004 CR3005 CR3006 SG N SG N Micro_Push_Button
1
1
-
1 OUT 1 3 BRIGHT GREEN BRIGHT GREEN BRIGHT GREEN BRIGHT GREEN
2 GND WLAN WWAN BT 2 4 Caps-lock Num-lock HDD S3 1 3
RF_KILL Activity 2 4 Power-button
Microphone Battery PWR LED
2
(Full/Low) (PWR GD/TURBO)
2
2
p
NT_GND NT_GND
NT_GND_LED_LID_STATE
o
3
NT_AGND
Q3000
t
B
BSS138 B
NT_SMC_LID 1
2
p
NT_GND
. la
w
Battery LED Condition Table
No Charge Charging
Capacity >= 75% Capacity >= 90%

Blinking
w
Green
Green 90% > Capacity >= 75%

Green
w
Title
Mounting Holes
75% > Capacity >= ??% 75% > Capacity >= ??% Nut Tree AIC
MT3000 MT3001 MT3002
1 1 1
Orange Orange Size Document Number Rev
NT_GND NT_GND NT_GND A
NO_STUFF
5 4 3 2 1
5 4 3 2 1
o m
c
D D
s.
it c
a
ODD_INT_RSVD
ODD_INT_TEST
ODD_INT_PDIOR#
ODD_INT_PDIOW#
ODD_INT_PDDACK#
ODD_INT_PDIAG#
ODD_INT_PATADET
ODD_INT_D_PRST#_R
m
ODD_INT_IRQ14
ODD_INT_PD_CSEL
ODD_INT_PDIORDY
ODD_INT_PDDREQ
e
C C
J4000 J4001
22 DMARQ DMARQ 22
27 1 ODD_INT_AUD_LEFT_CH 1 27
IORDY AUDIO_L-CH ODD_INT_AUD_RIGHT_CH AUDIO_L-CH IORDY
h
47 CSEL AUDIO_R-CH 2 2 AUDIO_R-CH CSEL 47
29 3 ODD_INT_AUD_GND 3 29
INTRQ AUDIO_GND AUDIO_GND INTRQ
5 RESET# RESET# 5
32 PDIAG# PDIAG# 32
30 IOCS16# IOCS16# 30
c
28 21 ODD_INT_DD0 21 28
DMACK# 0.78 DD0 ODD_INT_DD1 DD0 0.78 DMACK#
25 DIOW# DD1 19 19 DD1 DIOW# 25
24 17 ODD_INT_DD2 17 24
DIOR# DD2 ODD_INT_DD3 DD2 DIOR#
DD3 15 15 DD3
13 ODD_INT_DD4 13
DD4 DD4
-s
11 ODD_INT_DD5 11
DD5 ODD_INT_DD6 DD5
49 TEST DD6 9 9 DD6 TEST 49
+V5_ODD_INT 50 7 ODD_INT_DD7 7 50
RSVD DD7 ODD_INT_DD8 DD7 RSVD +V5_ODD_INT
DD8 6 6 DD8
8 ODD_INT_DD9 8
DD9 ODD_INT_DD10 DD9
38 +5V-1 DD10 10 10 DD10 +5V-1 38
39 12 ODD_INT_DD11 12 39
+5V-2 DD11 ODD_INT_DD12 DD11 +5V-2
40 +5V-3 DD12 14 14 DD12 +5V-3 40
41 16 ODD_INT_DD13 16 41
+5V-4 DD13 DD13 +5V-4
p
42 18 ODD_INT_DD14 18 42
+5V-5 DD14 ODD_INT_DD15 DD14 +5V-5
DD15 20 20 DD15
4 33 ODD_INT_DA0 33 4
GND0 DA0 ODD_INT_DA1 DA0 GND0
23 GND1 DA1 31 31 DA1 GND1 23
26 34 ODD_INT_DA2 34 26
o
GND2 DA2 ODD_INT_DASP# DA2 GND2
43 GND3 DASP# 37 37 DASP# GND3 43
44 GND4 GND4 44
t
45 GND5 GND5 45
46 0.58 36 ODD_INT_CS1# 36 0.58 46
GND6 CS1# ODD_INT_CS0# CS1# GND6
48 35 35 48
B GND7 CS0# CS0# GND7 B
CONN50_DVD_RCP_K2D CONN50_DVD_RCP_K5D
p
ODD_GND ODD_GND
J4000 Connects to Oakmont Header J26 J4001 Connects to ODD Device
. la
A
ww A
w
Title
ODD interposer
5 4 3 2 1
5 4 3 2 1
m
+V5S_SF 64
CONN60_0_635MM_SMT_PLUG
+V3.3S_SF 64 62 MECH_2
61
o
MECH_1 SW2000 J2001
Expresscard Slot/54mm
1 3 26 GND0
2 4
60 59 LID_Switch PCIE_TXP3_SF 25
60 59 PETP0
58 57
c
+V1.5S_SF 58 57 PCIE_TXN3_SF
56 56 55 55 24 PETN0
54 53
D 54 53 NT_SMC_LID_R D
.
52 52 51 51 SMC_LID_SF 64 23 GND1
50 50 49 49
48 47 PCIE_RXP3_SF 22
48 47 PLT_RST#_SF 64 PERP0
46 45 R2013
64 +V3.3A_SF 46 45 100 PCIE_RXN3_SF
44 44 43 43 AZ_SPEAKER_L_SF 64 21 PERN0
s
42 42 41 41 AZ_SPEAKER_R_SF 64
40 40 39 39 20 GND2
38 38 37 37 AZ_MUTE_SF 64
36 35 CLK_PCIE_EXPCARD_SF 19
36 35 TP_USB_PN9_SF REFCLK+
34 34 33 33
TP_USB_PP9_SF CLK_PCIE_EXPCARD#_SF
it c
32 32 31 31 18 REFCLK-
CLKREQ#_SF 30 29 SF_GND
30 29 USB_PN2_SF EXPRESS_CPPE#_SF
28 28 27 27 17 CPPE#
PCIE_WAKE#_SF 26 25 USB_PP2_SF
26 25 CLK_EXPCARD_OE#_SF
24 24 23 23 16 CLKREQ#
PCIE_TXP3_SF 22 21 +V3.3S_EXPRESS
PCIE_TXN3_SF 22 21 NETDETECT#_SF 64
20 20 19 19 15 +3.3VS_0
18 18 17 17 NETDETECT_LED_SF 64
PCIE_RXP3_SF 16 15 14
16 15 S3_LED_SF 64 +3.3VS_1
PCIE_RXN3_SF 14 13
14 13 LED_BATT_FULL_SF 64
12 11 +V3.3AUX_EXPRESS EXPRESS_PERST#_SF 13
12 11 LED_BATT_LOW_SF 64 PERST#
a
CLK_PCIE_EXPCARD_SF 10 9
CLK_PCIE_EXPCARD#_SF 10 9
8 8 7 7 IR_RXD_SF 64 12 +3.3VAUX
6 6 5 5 IR_MODE_SF 64
SMB_DATA_A1_SF 4 3 PCIE_WAKE#_SF 11
4 3 IRDA_CIR_SLT_SF 64 WAKE#
SMB_CLK_A1_SF 2 1 +V1.5S_EXPRESS
2 1 IR_TXD_SF 64
10 +1.5V_1
J2002
9 +1.5V_2
m
SMB_DATA_A1_SF R2006 1K SMDATA_SF 8
1% SMB_DATA
SMB_CLK_A1_SF R2007 1K SMCLK_SF 7
1% SMB_CLK
6
e
C SF_GND
RESV1 C
SF_GND 5 RESV2
+V3.3S_SF 64 EXPRESS_CPUSB#_SF 4 27
L2000 CPUSB# SHLD1
SHLD2 28
USB_PP2_SF EXP_USB_PP1_SF
h
1 4 3 USB_D+ SHLD3 29
+V1.5S_SF 30
USB_PN2_SF EXP_USB_PN1_SF SHLD4
2 3 2 USB_D-
64 +V3.3A_SF +V3.3S_EXPRESS 90_100MHz 1 GND3
c
CONN26_EXPRESSCARD-HOST-CONN
U2005
EU2004 +V1.5S_EXPRESS B1 A2 +V3.3A_SF 64
ESD_CH2 ESD_CH1
-s
5 3.3VIN_1 3.3VOUT_1 7
6 8 64 +V3.3A_SF A1 B2 SF_GND SF_GND
3.3VIN_2 3.3VOUT_2 +V3.3AUX_EXPRESS V- V+ C2022
18 1.5VIN_1 1.5VOUT_1 16
19 17 CM1230_02 0.1uF
1.5VIN_2 1.5VOUT_2 R2004 10%
21 3.3VAUX_IN V3.3VAUX_OUT 20
10K
EXPRESS_CPPE#_SF 15 4 SF_GND
EXPRESS_CPUSB#_SF CPPE# STBY# SHDN#_SF
14 CPUSB# SHDN# 3 SF_GND
p
1 NC_1 OC# 23 EXPRESS_CARD_OC#_SF C2003 C2004 +V3.3AUX_EXPRESS
10 NC_2 PERST# 9 EXPRESS_PERST#_SF 0.1uF 0.1uF
12 10% 10%
NC_3
13 NC_4 RCLKEN 22 RCLKEN_SF +V3.3AUX_EXPRESS
24 2 PLT_RST#_SF R2000
Inputs to voltage switch. NC_5 SYSRST# 10K
o
11 GND GND2 25 SF_GND
5
TPS2231_NEWCARD_PWRSW Q2001
t
5
U2002 CLK_EXPCARD_OE#_SF
2 4 RCLKEN#_SF 1
B SF_GND SF_GND 4 CLKREQ#_SF B
CLK_EXPCARD_OE#_SF 2
INVERTER
p
3 74AHC1G08
3 . Overcurrent Shutdown
Circuitry, Resets after
+V3.3A_SF 64
SF_GND SF_GND
card is ejected
la
5
U2001
EXPRESS_CARD_OC#_SF 1
4 SHDN#_SF
+V3.3A_SF 64 2
CPPE#_OC_SF
.
+V1.5S_SF +V3.3S_SF 64 +V3.3A_SF 64 +V1.5S_EXPRESS +V3.3S_EXPRESS +V3.3AUX_EXPRESS 74AHC1G32
3
5
U2000
EXPRESS_CPPE#_SF 1 SF_GND
C2019 C2016 C2015 C2011 C2007 C2006 C2018 C2021 C2017 C2020 C2013 C2012 4
0.1uF 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 10uF 2
10% 10% 10% 10% 10% 10%
w
USB_OC_SF
+V3.3A_SF 64 74AHC1G08
3
+V3.3A_SF 64
5
SF_GND SF_GND SF_GND SF_GND SF_GND SF_GND Q2000 SF_GND
EXPRESS_CARD_OC#_SF 2 4
C2000 C2001 C2002
w
0.1uF 0.1uF 0.1uF
INVERTER 10% 10% 10%
3
SF_GND SF_GND
A A
w
NO_STUFF
Mounting Holes
Title
SkyForest (1 of 2)
MT2001 MT2002 MT2003 MT2004 MT2000
1 1 1 1 1
SF_GND SF_GND SF_GND SF_GND SF_GND
Custom
5 4 3 2 1
5 4 3 2 1
+V3.3S_SF 63
R2008 3.9 LED_A

U2007
o m +V3.3A_SF 63
c
1 LED_A
2 IO_VCC
D C2023 + C2025 C2024 IRDA_TXD 3 D
.
0.1uF 6.8uF 0.1uF TXD_IR
10% 63 IR_RXD_SF 4 RXD
2
10% 10% 5
63 IR_MODE_SF SD
6 CR2000
CIR_TXD VCC BLUE
7 TXD_RC
s
SF_GND 8 GND SHLD 9
R2012 4.7 VCC_HSDL
1
R2009 R2010 HSDL-3021_021 LED_NETDETECT
C2027 + C2028 10K 10K SF_GND
3
6.8uF
it c
0.1uF SF_GND
10%
10% Q2002
BSS138
63 NETDETECT_LED_SF 1
SF_GND SF_GND
100K
SF_GND U2006
2
63 IRDA_CIR_SLT_SF 1 S Y0 6
2 GND VCC 5
63 IR_TXD_SF 3 A Y1 4
R2014
a
NON-INV DMUX C2026
0.1uF
10%
SF_GND
SF_GND SF_GND
m
C C
e
NET_DETECT
SW2001
1 3 +V3.3A_SF 63
h
NETDETECT#_SF 63
2 4 2
Push_Button
63 S3_LED_SF
SMC_LID_SF 1
SF_GND
c
BSS84
2
Q2005
63 SMC_LID_SF 1
3
-s
BSS84
Q2006 LED_BATT_SF_R1
R2011
3LED_S3_R_SF 33
+V3.3A_SF 63
AZ_SPEAKER_R_OUTL_R R2003 10K
3
p
CR2002 LED_BATT_SF_R2
A
AZ_SPEAKER_L_OUTR_R R2001 10K YEL/GREEN
3
+V5S_SF 63 R2015
10K CR2001
A
YEL/GREEN
o
G
Y
C2008 C2005
1
t
B 0.1uF 4.7uF B
G
Y
10% 10% SF_YELLOW_LED_PU
1
EU2003
SF_GND
p
SF_GND12 VDD
8 19 SPEAKER_OUTLP LED_BATT_LOW_SF#
PVDD1 OUTL+ J2000
18 PVDD2
3
17 SPEAKER_OUTLN 1
C2010 1uF AZ_SPEAKER_L_C R2002 8.2K OUTL- 1 Q2004
la
63 AZ_SPEAKER_L_SF 2 2
1 SPEAKER_OUTRP 3 BSS138
INL SPEAKER_OUTRN 3
5 INR OUTR- 9 4 4 63 LED_BATT_LOW_SF 1
C2009 1uF AZ_SPEAKER_R_C R2005 8.2K 7 CON4_HDR
.
63 AZ_SPEAKER_R_SF
2
BIAS_SF OUTR+
2 BIAS
14 SF_GND LED_BATT_FULL_SF#
63 PLT_RST#_SF SHDN#
63 AZ_MUTE_SF 4 MUTE
3
6 10 Q2003
w
PGND1 NC1 BSS138
C2014 11 PGND2 NC2 13
1uF 15 PGND3 NC3 16 63 LED_BATT_FULL_SF 1
20 PGND4 NC4 3
21
2
MECH
w
MAX9710ETP
SF_GND SF_GND
A A
w
Title
SF_GND
SkyForest (2 of 2)
SF_GND
A
5 4 3 2 1

Laptop Schematic Diagram 845 (Merom-Crestline Mobile Platform)

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Laptop Schematic Diagram 845 (Merom-Crestline Mobile Platform)

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5 4 3 2 1

Size Document Number Rev

S4 (Suspend To Disk) /M-Off LOW OFF OFF OFF OFF

S5 (Soft OFF) /M-Off LOW OFF OFF OFF OFF

A Oakmont Form Factor Reference Design Intel Confidential A

Size Document Number Rev

A5 C7 to ICH8 and GMCH without H_D#6 E25 U25 H_D#38

TP_CPU_RSVD05 B2 H25 U22

Merom Ball-out Rev 1a_Oakmont

Size Document Number Rev

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System thermal monitoring

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J20 CFG_8 DMI_RXP[3:0] 22

MCH_CFG_9 C20 AJ47 DMI_RXP0 H32 M45

TP_MCH_CFG_17 M24 K33 Y39 TP_PEG_TX8

J36 E36 0.5% CRESTLINE_1p0_OAKMONT

TP_MCH_NC2 NC_1 CL_PWROK MPWROK 23,47 3.01k 10% 10%

TP_MCH_NC8 BK1 1% R77

TP_MCH_NC10 E1 K36 R90 C117 C499

AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18

M_A_DQ45 AW9 BJ16 M_A_A13 M_B_DQ45 BK10 BG13 M_B_A13

Size Document Number Rev

+V1.05S 3,4,6,10,20,21,24,45,48,54,56 +V3.3S 5,7,10,16..19,22..26,28,30,32..34,38,40,42,44,45,49,50,52,55..58

VCC_SM_14 VCC_AXG_NCTF_39 VCC_NCTF_34

VCC_SM_18 VCC_AXG_NCTF_43 VCC_NCTF_38 VSS_SCB2

VCC AXM NCTF

VCC_AXG_13 VCC_AXG_NCTF_78 VCC_AXM_NCTF_17

VCC_AXG_23 VCC_SM_LF2 VCC_SM_LF3_C 330uF 22uF 22uF 0.1uF

Size Document Number Rev

+ C208 Recommended bulk 10% A33 and B33 J32 U13

180ohm@100MHz 22nF C110 VCCA_CRT_DAC_1 VTT_3 4.7uF 10% 0.47uF 10%

C526 C142 C537 + C527 C112 AH50

1.0uF 4.7uF 22uF C548 22uF 0.1uF VCCDQ_CRT VCC_RXR_DMI_1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

EXTTS#0 & EXTTS#1 connection options table

195 M_A_DQ34 10% 10%

ww Oakmont Form Factor Reference Design Intel Confidential

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ww Oakmont Form Factor Reference Design Intel Confidential

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DDR2 Thermal Sensor So-Dimm 0 & 1

Size Document Number Rev

BSS138 U71 C335

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Size Document Number Rev

9,10,13,14,45,47,56 +V1.8 +V2.5S_3.3S_HDMI

C53 SDAROM 1000pF 0.1uF 1uF

0.1uF U2008 SCLROM GND3 10% 10%

HDMI_SCLROM_U SPVCC_FB FB6

OUT A (SEL LOW)

HDMI_LINT#_R C1P-A HDMI_TX0P_DOCK 45

OUT B (SEL HIGH)

10uF 1000pF 0.1uF 1000pF C370 23 HDMI_TX2P_Q

10% 10% 10% 100pF 22 HDMI_TX2N_Q

PI3V512QE Date: Sheet 18 of 64

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ww Oakmont Form Factor Reference Design Intel Confidential

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