DATE: 9/3/11 ENCODER

Exercise No: 5

Aim
1) To design an 8:3 ENCODER (normal) and 4:2 ENCODER (priority) and To Write a
VHDL Code for it.
2) To generate the Test Bench Waveform and verify it with the design.

8:3 ENCODER

Block Diagram

D0

D1

D2 Y0

D3 Y1
8:3 ENCODER
D4 Y2

D5

D6

D7

Function Table

Input Output
D0 D1 D2 D3 D4 D5 D6 D7 Y0 Y1 Y2
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Theory

Encoder

An encoder is a device, circuit, transducer, software program, algorithm or person that

converts information from one format or code to another, for the purposes of standardization,
speed, secrecy, security, or saving space by shrinking size.

Simple Encoder
A simple encoder circuit can receive a single active input out of 2n input lines generate a
binary code on n parallel output lines. For example a single bit 4 to 2 encoder takes in 4 bits
and outputs 2 bits. The illustrated gate level example implements the simple encoder defined
by the truth table, but it MUST be understood that for all the non explicitly defined input
combinations (i.e. inputs containing 0, 2, 3, or 4 bits) the outputs are treated as don't cares.
VHDL Code

(i) Using Operators

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER1 is
Port ( D : in std_logic_vector(7 downto 0);
X : out std_logic;
Y : out std_logic;
Z : out std_logic);
end ENCODER1;
architecture ENCODER1_operator of ENCODER1 is
begin
X <= D(0) or D(7) or D(4) or D(5);
Y <= D(6) or D(7) or D(2) or D(3);
Z <= D(5) or D(7) or D(1) or D(3);
end ENCODER1_operator;
Test Bench Waveform

(ii) Using Simple When

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER2 is
Port ( D : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(2 downto 0));
end ENCODER2;
architecture ENCODER2_when of ENCODER2 is
begin
Y <= "000" when D <="00000001" else
"001" when D <="00000010" else
"010" when D <="00000100" else
"011" when D <="00001000" else
"100" when D <="00010000" else
"101" when D <="00100000" else
"110" when D <="01000000" else
"111" when D <="00000010";
end ENCODER2_when;
(iii) Using Selected When

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER3 is
Port ( D : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(2 downto 0));
end ENCODER3;
architecture ENCODER3_when of ENCODER3 is
begin
with D select
Y <= "000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when others;
end ENCODER3_when;

(iv) Using IF

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER4 is
Port ( D : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(2 downto 0));
end ENCODER4;
architecture ENCODER4_if of ENCODER4 is
begin
Process(D)
begin
if D(0)='1' then Y <= "000";
elsif D(1)='1' then Y <= "001";
elsif D(2)='1' then Y <= "010";
elsif D(3)='1' then Y <= "011";
elsif D(4)='1' then Y <= "100";
elsif D(5)='1' then Y <= "101";
elsif D(6)='1' then Y <= "110";
else Y <= "111";
end if;
end Process;
end ENCODER4_if;

(v) Using Case

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER5 is
Port ( D : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(2 downto 0));
end ENCODER5;
architecture ENCODER5_case of ENCODER5 is
begin
Process(D)
begin
case D is
when "00000001" => Y <="000";
when "00000010" => Y <="001";
when "00000100" => Y <="010";
 when "00001000" => Y <="011";
when "00010000" => Y <="100";
when "00100000" => Y <="101";
when "01000000" => Y <="110";
when others => Y <="111";
end case;
end Process;
end ENCODER5_case;
*

(vi) Using Components

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ENCODER6 is
Port ( D : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(2 downto 0));
end ENCODER6;
architecture ENCODER6_comp of ENCODER6 is
component OR2 is
Port(A,B:in std_logic;
Y: out std_logic);
end component;
signal W1,W2,W3,W4,W5,W6:std_logic;
begin
C1: OR2 port map(D(4),D(5),W1);
C2: OR2 port map(D(0),D(7),W2);
C3: OR2 port map(W1,W2,Y(2));
C4: OR2 port map(D(2),D(3),W3);
C5: OR2 port map(D(6),D(7),W4);
C6: OR2 port map(W3,W4,Y(1));
C7: OR2 port map(D(1),D(3),W5);
C8: OR2 port map(D(5),D(7),W6);
C9: OR2 port map(W5,W6,Y(0));
end ENCODER6_comp;

Test Bench Waveform

 4:2 Priority Encoder

Block Diagram

D0
4:2 Priority
D1 Y1
Encoder
D2 Y0

D3

Function Table

D3 D2 D1 D0 Y1 Y0

1 X X X 1 1

0 1 X X 1 0

0 0 1 X 0 1

0 0 0 1 0 0

0 0 0 0 Z Z

Theory
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a
smaller number of outputs. The output of a priority encoder is the binary representation of the
ordinal number starting from zero of the most significant input bit. They are often used to
control interrupt requests by acting on the highest priority request. If two or more inputs are
given at the same time, the input having the highest priority will take precedence. An
example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are to the left
and "x" indicates an irrelevant value - i.e. any input value there yields the same output since it
is superseded by higher-priority input. Priority encoders can be easily connected in arrays to
make larger encoders, such as one 16-to-4 encoder made from six 4-to-2 priority encoders -
four 4-to-2 encoders having the signal source connected to their inputs, and the two
remaining encoders take the output of the first four as input. The priority encoder is an
improvement on a simple encoder circuit, in terms of handling all possible input
configurations.

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PRIORITYENCODER is
Port ( D : in std_logic_vector(3 downto 0);
E : in std_logic;
Y : out std_logic_vector(1 downto 0));
end PRIORITYENCODER;
architecture PRIORITYENCODER of PRIORITYENCODER is
begin
Process(E,D)
begin
Y <= "00";
if E='0' then
for j in 3 downto 0 loop
if D(j)='1' then Y <= conv_std_logic_vector(j,2);
exit;
end if;
end loop;
end if;
end Process;
end PRIORITYENCODER;
Test Bench Waveform

Result
The 8:3 Encoder and 4:2 Priority Encoder are designed using VHDL and verified the same by
generating Test bench waveform.