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V Each bitcell requires 1
transisitor and 1
capacitor.
V Needs to be refreshed
every milliseconds to
retain data because
the charge of the
capacitor leaks.
V Memory density is
less.
V Each cell which can
store a single bit
requires 6 transistors.
V Does not need to be
refreshed periodically
as ip op retains the data
V Faster access time
compared to DRAM,
therefore used as caches
mostly.
V Very less memory
density.
THYRISTOR RANDOM ACCESS MEMORY
V Combined strengths of SRAM and DRAM.