Verilog Synthesis Handbook Quad Input NOR gate:

Code: module NOR (in1, in2, in3, in4, out); input in1, in2, in3, in4; output out; nor NOR (out, in1, in2, in3, in4); endmodule

D Flip-Flop using NOR gate:

Code: module DFF (clk,in,Q,QBar); input clk,in; output Q, QBar; wire w1,w2,w3,w4,w5,w6, w0; NOR G1(w4,w2,w0,w0,w1); NOR G2(w1,clk,w0,w0,w2); NOR G3(w2,clk,w4,w0,w3); NOR G4(w3,in,w0,w0,w4); NOR G5(w2,w6,w0,w0,w5); NOR G6(w5,w3,w0,w0,w6); -1-

Verilog Synthesis Handbook

assign w0 = 1'b0; assign Q = w5; assign QBar = w6; endmodule 2:1 MUX:

Code: module MUX(A,x1,x0,x); input A,x1,x0; output x; wire w1,w2,w3; not NOT1(w3,A); and AND1(w1,A,x0); and AND2(w2,w3,x1); or OR1(x,w1,w2); endmodule 4:1 MUX using 2:1 MUX:

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Verilog Synthesis Handbook Code: module MUX4 (A,X,out); input [1:0] A; input [3:0] X; output out; wire w1,w2; MUX G1(A[0],X[3],X[2],w1); MUX G2(A[0],X[1],X[0],w2); MUX G3(A[1],w1,w2,out); endmodule Full Adder:

Code: module adder (a,b,cin,s,cout); input a,b,cin; output s,cout; assign s = a^b^cin; assign cout = (a&b)|(cin&(a|b)); endmodule

8:1 MUX using 4:1 MUX and 2:1 MUX: -3-

Verilog Synthesis Handbook

Code: module MUX8(B,Y,out2); input [2:0] B; input [7:0] Y; output out2; wire w5,w6; MUX4 F1(B[1:0],Y[7:4],w5); MUX4 F2(B[1:0],Y[3:0],w6); MUX F3(B[2],w5,w6,out2); endmodule Octal to Binary Encoder:

Code: module Encoder83 (I[0:7], O[2:0]); input [0:7] I; output [2:0] O; wire w1,w2,w3,w4,w5,w6;

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Verilog Synthesis Handbook

or OR1(w1,I[1],I[3]); or OR2(w2,I[5],I[7]); or OR3(O[0],w1,w2); or OR4(w3,I[2],I[3]); or OR5(w4,I[6],I[7]); or OR6(O[1],w3,w4); or OR7(w5,I[4],I[5]); or OR8(w6,I[6],I[7]); or OR9(O[2],w5,w6); endmodule 4 Bit Comparator:

Code: module comparator (A,B,O); input [3:0] A,B; output [4:0] O; wire [3:0] C; wire [3:0]S; wire [3:0]Y; wire x; wire z; xor XOR1(Y[0],1,B[0]); xor XOR2(Y[1],1,B[1]); xor XOR3(Y[2],1,B[2]); xor XOR4(Y[3],1,B[3]); adder F1(A[0],Y[0],1'b1,S[0],C[0]); adder F2(A[1],Y[1],C[0],S[1],C[1]); adder F3(A[2],Y[2],C[1],S[2],C[2]); adder F4(A[3],Y[3],C[2],S[3],C[3]); xor XOR5 (x,C[3],C[2]); -5-

Verilog Synthesis Handbook

nor NOR1(O[0],x,S[3],S[2],S[1],S[0]); nor NOR2(O[1],O[0],S[3]); not NOT1(O[2],O[1]); not NOT2(O[3],S[3]); not NOT3(z,S[3]); not NOT4(O[4],z); endmodule 4X4 Multiplier:

Code: module FourByFourMultTestbench; reg [3:0] A, B; wire [7:0] P; integer outctr,inctr; integer filout; multiplier4 UUT (A,B,P); // A and B are the inputs // P is the output initial begin filout = $fopen("MulRes.wri"); // Open this file after ending the simulation for (outctr = 0; outctr <= 15; outctr=outctr+1) begin A = outctr; for (inctr = 0; inctr <= 15; inctr=inctr+1)

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Verilog Synthesis Handbook begin #10 B = inctr; #2 $fdisplay(filout," %d * %d = %d ",A,B,P); end end #10 $fclose(filout); $stop; end endmodule 4 Bit SIPO Register:

Code: module SIPO(in1, clk, out); input in1,clk; output [3:0]out; wire w1,w2,w3,w4,w5; DFF D1(clk, in1,w1,w5); DFF D2(clk, w1, w2,w5); DFF D3(clk, w2, w3,w5); DFF D4(clk, w3, w4,w5); assign out[3]=w1; assign out[2]=w2; assign out[1]=w3; assign out[0]=w4; endmodule module dfftest; reg in, clk; wire [3:0]w; sipo test(in, clk, w);

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Verilog Synthesis Handbook initial begin clk =1'b0; forever #1 clk = ~clk; end initial begin #100 $stop; end initial begin in = 1'b1; end initial begin $display (" in out "); $monitor (" %b out[%b]", in, w[3:0]); end endmodule Serial Adder FSM:

Code: module FSMAdder (clk,Reset,in,out); input Reset,clk; input [1:0] in; output out; reg State; reg Nxt_State; reg O;

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Verilog Synthesis Handbook

parameter C0 = 1'b0; parameter C1 = 1'b1; always @(posedge clk or posedge Reset) begin if (Reset == 1'b1) State <= C0; else State <= Nxt_State; end always @(in or State) begin case ({State,in}) 3'b000:begin O = 1'b0; Nxt_State = C0; end 3'b001:begin O = 1; Nxt_State = C0; end 3'b010:begin O = 1; Nxt_State = C0; end 3'b011:begin O = 0; Nxt_State = C1; end 3'b100:begin O = 1; Nxt_State = C0; end 3'b101:begin O = 0; Nxt_State = C1; end 3'b110:begin O = 0; Nxt_State = C1; end 3'b111:begin

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Verilog Synthesis Handbook O = 1; Nxt_State = C1; end default: begin O = 0; Nxt_State = C0; end endcase end assign out = O; endmodule Sequence Detector FSM:

Code: module FSMSeqDet (Reset,clk,in,out); input in,clk; input Reset; output out; reg [1:0] State; reg [1:0] Nxt_State; reg O; parameter A = 2'b00; parameter B = 2'b01; parameter C = 2'b10; - 10 -

Verilog Synthesis Handbook parameter D = 2'b11; always @(posedge clk or posedge Reset) begin if (Reset == 1'b1) State <= A; else begin $display("out : %b",O); State <= Nxt_State; end end always @(in or State) begin case({State,in}) 3'b000: begin O = 1'b0; Nxt_State = B; $display("Out : %b",O); end 3'b001: begin O = 1'b0; Nxt_State = A; $display("Out : %b",O); end 3'b010: begin O = 0; Nxt_State = B; $display("Out : %b",O); end 3'b011: begin O = 0; Nxt_State = C; $display("Out : %b",O); end 3'b100: begin O = 0; Nxt_State = D;

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Verilog Synthesis Handbook $display("Out : %b",O); end 3'b101: begin O = 0; Nxt_State = A; $display("Out : %b",O); end 3'b110: begin O = 0; Nxt_State = B; $display("Out : %b",O); end 3'b111: begin O = 1; Nxt_State = C; $display("Out : %b",O); end default: begin O = 1'b0; Nxt_State = A; end endcase end assign out = O; endmodule

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