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Pertinent Equations
Graphical Solution
ID IDSS
JFET Fixed-bias
VGG
+
VDD RD RG
JFET Self-bias
VDS
RS VDD
VGS VDD
IDRS ID(RD
RS)
Q-point VP V' 0 GS
I'D VGS
R1 R2
RD
VG
R2VDD R1 R2
Q-point VP
RS VDD RD
VDS
JFET Common-gate
RS VSS VDD RD
VDS
VGS VDD
VSS VSS
IDRS ID(RD
RS)
Q-point VP Q-point 0
ID IDSS VGS = 0 V
Q
JFET (VGSQ 0 V)
JFET (RD 0 )
RG
VDD
VGS VD VS VDS
RS
Q-point VP V'GS 0
VDD RD
ID Q-point
RG
IDSS
0 VGG ID Q-point
VGS
R1 R2
RD
VG
R2VDD R1 R2
VG RS IDSS
RS
VDS
VDD RD
VP ID
VG VGS
RG
ID(on)
VDD
R1 R2
RD
VG VGS
R2VDD R1 R2 VG IDRS
VG RS
RS
281
TABLE 8.1 Relative Levels for the Important Parameters of the CE, CB, and CC Transistor Amplifiers Configuration
Fixed-bias: VCC RB RC
Zi
Medium (1 k ) RB re re (RB 10 re) (ro
Zo
Medium (2 k ) RC ro RC 10RC) (ro
Av
High ( 200) (RC ro) re RC re 10RC)
Ai
High (100) RBro RC)(RB
(ro
re)
(ro RB
10RC , 10 re)
Voltage-divider bias: R1
VCC RC
Medium (1 k ) R1 R2 re
Medium (2 k ) RC ro RC
(ro
re)
R2
(ro RE CE
10RC)
VCC RC
High (50) RB Zb
re
RB
RB RE RE (RE re)
Emitterfollower: RB
VCC
Low (20 RE re re
Low (
1)
High ( 50) RB Zb
RE RE re 1
RB
RB RE re)
(RE
re)
Low (20 RE re re
Medium (2 k ) RC
High (200) RC re
Low ( 1) 1
re)
VCC RC
Medium (1 k ) re 1 RC RE 10RC)
High (50) RF RF RF RC RC
(ro
8.12 Troubleshooting
383
gm
TABLE 9.1 Zi, Z0, and Av for various FET configurations Configuration
Fixed-bias [JFET or D-MOSFET]
+VDD
Zi
Zo
Av
Vo Vi
D-MOSFET]
RD C1 Vi Zi RG VGG Zo C2 Vo
RD rd
gm RD
(rd
10 RD)
Medium (2 k )
C2 Vo
-MOSFET]
C1 Vi Zi RG
RD
High (10 M ) RD rd RG
Zo
RD
(rd 10 RD)
gm RD
(rd 10 RD)
RS
CS
d RS -MOSFET]
C1 Vi Zi RG
1
C2 Vo
gmRS gmRS
RS RD rd RS rd RD rd 1
RD
High (10 M ) RG
Zo
gmRD gmRs RD
RS rd
RD
RS
rd
10 RD or rd
gmRD 1 gmRS
[rd 10(Rd RS)]
+VDD
Medium (2 k )
RD C2 Vo Zo
High (10 M ) R1 R2
RD r
RD
(rd 10 RD)
gm RD
(rd 10 RD)
R2
RS
CS
437
gm
TABLE 9.1 (Continued) Configuration
Source-follower [JFET or D-MOSFET] Low ( 1)
Zi
Zo
Av
Vo Vi
-MOSFET]
C1 Vi Zi RG
+VDD
rd RS 1/gm
RG
RS
RS 1/gm
(rd
10 RS)
Zo
gmRS gmRS
(rd 10 R S)
ate -MOSFET]
C1 Vi Q1
+VDD RD
Medium (2 k ) Low (1 k ) RD rd
C2 Vo
RS
rd RD 1 gmrd RD
(rd 10 RD)
Zi
RS RG
CS
Zo
1 RS gm
(rd
10 RD)
gmRD
(rd
10 R S)
back bias T
RF C1 Vi Zi
+VDD RD C2 Vo Zo
RF gmRD
RD
(rd 10 RD)
(RF, rd
10 RD)
gmRD
(RF, rd 10 RD)
ider bias T
+VDD
Medium (2 k )
RD R1 D Zo S C2 Vo
Medium (1 M ) R1 R2
RD rd
C1 Vi Zi
RD
RS
(Rd
10 RD)
gmRD
(rd 10 RD)
R2
438
Chapter 9
Rs /RL
the equations will reveal that the isolation provided by the JFET between the gate and channel by the SiO2 layer results in a series of less complex equations than those encountered for the BJT configurations. The linkage provided by Ib between input and output circuits of the BJT transistor amplifier adds a touch of complexity to some of the equations.
TABLE 10.1 Summary of Transistor Configurations (Av, Zi, Zo) Configuration Av Vo /Vi
RL RC) re
Zi
RB re
Zo
RC
hfe hie (RL RC) Including ro: (RL RC ro) re (RL RC) re
RB hie
RC
RB re
RC ro
R1 R2 re
RC
R1 R2 hie
RC
RE 1
RL RE RE)
Rs RE
Rs R1 R2 Rs re
R1 R2 (re
hie
Rs
re
(RL RC) re hfb hib (RL RC) Including ro: (RL RC ro) re
RE re RE hib
RC RC
RE re
RC ro
477
Rs /RL
TABLE 10.1 Summary of Transistor Configurations (Av, Zi, Zo) (Continued) Configuration
VCC
Av
Vo /Vi
RL RC) RE
Zi
R1 R2 (re RE)
Zo
RC
RC R1 Rs Vi Zo RL Zi R2 RE Vo
(RL RC) RE
R1 R2 (hie
hfeRE)
RC
+
Vs
R1 R2 (re
RE)
RC
VCC
RB (re
RE1)
RC
RC RB Rs Vi Zo Vo
RB (hie
hfeRE1)
RC
+
Vs
Zi
RE1
RE2
CE
RB (re
RE1) RF
RC
VCC RC RF Rs Vi Vo Zo Zi
re
Av
RC
RF hie A v
RC
+
Vs
RL
RF re Av RF RE Av RC RF RC RF ro
VCC RC RF Rs Vi Vo Zo RL Zi RL E
(RL RC) RE
RF hfeRE Av RC RF
+
Vs
478
Chapter 10
Rs /RL
TABLE 10.1 (Continued) Configuration
VDD RD Vo Rsig Vi Zo RL Zi RG RS CS
Av
Vo /Vi
Zi
Zo
gm(RD RL)
RG
RD
+
Vs
VDD RD Vo Rsig Vi Zo RL Zi RG RS
RG
RD gmRS
+
Vs
RG
VDD RD R1 Rsig Vi Zo RL Zi R2 RS CS Vo
gm(RD RL)
R1 R2
RD
+
Vs
VDD
1
RD Rsig Vi
RG
RS 1/gm
+
Vs
Zi
RG RS Zo RL
Vo
RG
RS gmrdRS rd RD
Rsig
Vi RD VDD Zo
Vo RS RL
RS gmRS
RD
+
Vs
Zi
RS gmrdRS rd RD RL
RD rd
479