//module of D_FF //ALU:

module dff(q,qbar,d,clear,clk); module alu(out,in1,in2,control);

output q,qbar; input [3:0] in1,in2; //define 4 bit inputs
input d,clear,clk; input [2:0] control; //define 3bit input control
wire s,sbar,r,rbar,cbar; output [4:0] out;
assign cbar= ~clear; //create complement reg [4:0] out=0; //initialize 5bit output out
// of signal clear always @ (in1,in2,control)
assign sbar= ~(s & rbar), //ff using 3 SR case(control)
s= ~(sbar & cbar & ~clk), // Latches 3'd0:out=in1;
r= ~(s & rbar & ~clk), 3'd1:out=in1+in2;
rbar= ~(r & cbar & d); 3'd2:out=in1-in2;
assign q= ~(s & qbar), 3'd3:out=in1*in2;
qbar= ~(q & cbar & r); 3'd4:out=in1/in2;
endmodule 3'd5:out=in1%4;
3'd6:out=in2%8;
// module of t_flipflop 3'd7:out=in1<<in2;
module tff(q,clk,clear); endcase
output q; endmodule
input clk,clear; module testalu(); //stimulus module
dff df(q, ,~q,clear,clk); reg [3:0] in1,in2;
endmodule reg [2:0] control;
wire [4:0] out;
// 4-bit counter using bottomup approach alu talu(out,in1,in2,control);
module counterbottomup(out,clk,clear); initial in1=2;
output [3:0]out; initial in2=4;
input clk,clear; initial
tff tff0(out[0],clk,clear); //instantiate control=0;
tff tff1(out[1],out[0],clear); //t_flipflops always #5
tff tff2(out[2],out[1],clear); control=control+1;
tff tff3(out[3],out[2],clear); endmodule
endmodule

module tcounterb();//stimulus module //Bcd to 7 Segment Double display

reg clk,clear; module bcd(out,in,clk);
wire [3:0]out;//4 bit output input [3:0] in; //define 4 bit input in
counterbottomup cbu(out,clk,clear); input clk;
initial output [6:0] out;
clear =1;s reg [6:0] out=0; //initialize 7 bit output out
always #100 clear=!clear; always @ (posedge clk)
initial case(in)
clk=0; 4'd0:out=7'b1000000;
always #2 clk=!clk; 4'd1:out=7'b1111001;
endmodule 4'd2:out=7'b0100100;
4'd3:out=7'b0110000;
4'd4:out=7'b0011001;
4'd5:out=7'b0010010;
4'd6:out=7'b0000010;
4'd7:out=7'b1111000;
4'd8:out=7'b0000000;
4'd9:out=7'b0011000;
endcase
always @ (negedge clk) //o/p change at –ve //Mux
case(in) //edge of clk pulse module muxb(out,in1,in2);
4'd0:out=7'b1000000; output out;
4'd1:out=7'b1111001; input in1,in2;
4'd2:out=7'b0100100; reg out;
4'd3:out=7'b0110000; initial
4'd4:out=7'b0011001; out=0;
4'd5:out=7'b0010010; always
4'd6:out=7'b0000010; begin
4'd7:out=7'b1111000; #1 out=in1;
4'd8:out=7'b0000000; #1 out=in2;
4'd9:out=7'b0011000; end
endcase endmodule
endmodule module testmb(); //stimulus module
module testbcd(); //stimulus module wire out;
reg [3:0] in; reg in1,in2;
reg clk; muxb a(out,in1,in2);
wire [6:0] out; initial in1=0;
bcd tbcd(out,in,clk); initial in2=1;
initial clk=0; endmodule
always#2 clk=!clk;
initial in=0;
always#5 //Mux with case statement
in=in+1; module muxc(out,in0,in1,in2,in3,s0,s1);
endmodule input in0,in1,in2,in3,s0,s1;
output out;
//Bcd to 7 Segment reg out;
module bcd(out,in); always @ (in0,in1,in2,in3)
input [3:0] in; //4-bit input begin
output [6:0] out; //7-bit output case({s0,s1})
reg [6:0] out=0; 2'd0: out=in0;
reg com; 2'd1: out=in1;
initial com=1; 2'd2: out=in2;
always @ (in) 2'd3: out=in3;
case(in) endcase
4'd0:out=7'b1000000; end endmodule
4'd1:out=7'b1111001; module tmuxc(); //stimulus module
4'd2:out=7'b0100100; reg in0,in1,in2,in3,s0,s1;
4'd3:out=7'b0110000; wire out;
4'd4:out=7'b0011001; muxc mux(out,in0,in1,in2,in3,s0,s1);
4'd5:out=7'b0010010; initial in0=0;
4'd6:out=7'b0000010; always #5 in0=!in0;
4'd7:out=7'b1111000; initial in1=0;
4'd8:out=7'b0000000; always #10 in1=!in1;
4'd9:out=7'b0011000; initial in2=0;
endcase always #15 in2=!in2;
endmodule initial in3=0;
module testbcd(); //stimulus module always #20 in3=!in3;
reg [3:0] in; initial s0=0;
wire [6:0] out; always #1 s0=!s0;
bcd tbcd(out,in); initial s1=0;
initial in=0; always #2 s1=!s1;
always #1 endmodule
in=in+1;
endmodule
//Positive edge 8 bit UPDown counter //Negative edge 8 bit Up counter
module counter(out,clk,reset,select); module counter(out,clk);
input clk,reset,select; input clk;
output [7:0] out; output [7:0] out;
reg [7:0] out=0; reg [7:0] out=0;
always @ (posedge clk) always @ (negedge clk) //Negative edge
begin out=out+1; // up counter
if (reset==0&&select==0) endmodule
out=out+1; //up counter module testc8(); //stimulus module
else if(reset==0&&select==1) wire [7:0] out;
out=out-1; //down counter reg clk;
else counter c8(out,clk);
out=0; initial
end clk=0;
endmodule always
module testc8(); //stimulus module #1 clk=!clk;
wire [7:0] out; endmodule
reg clk,reset,select;
counter c8(out,clk,reset,select);
initial clk=0; //Positive edge 8 bit down counter
always module counter(out,clk);
#1 clk=!clk; input clk;
initial output [7:0] out;
begin reg [7:0] out=0;
reset=0; always @ (posedge clk)
#5 reset=1; out=out-1;
#10 reset=0; endmodule
end module testc8(); //stimulus module
initial begin wire [7:0] out;
select=0; reg clk;
#15 select=1; counter c8(out,clk);
#20 select=0; initial clk=0;
end always
endmodule #1 clk=!clk;
endmodule

//Positive edge 8 bit Upcounter

module counter(out,clk); //D_ff:
input clk; module dff(q,q0,d,clk,reset);
output [7:0] out; //8-bit output input d,clk,reset;
reg [7:0] out=0; output q,q0;
always @ (posedge clk) reg q,q0;
out=out+1; // up counter always @(negedge clk)
endmodule if (reset==0)
module testc8(); //stimulus module begin
wire [7:0] out; q=d;
reg clk; q0=!d;
counter c8(out,clk); end
initial else begin
clk=0; q=0;
always q0=1;
#1 clk=!clk; end
endmodule endmodule
 initial
reset=0;
module tdff(); //stimulus module always #3 reset=!reset;
reg d,clk,reset; endmodule
wire q,q0;
dff dff0(q,q0,d,clk,reset);
initial
d=0;
always #2 d=!d; // traffic signals
initial module traffic(Ra,Ya,Ga,Rb,Yb,Gb,
clk=0; Rc,Yc,Gc,Rd,Yd,Gd);
always #1 clk=!clk; output reg Ra,Ya,Ga,Rb,Yb,Gb,Rc,
initial Yc,Gc,Rd,Yd,Gd;
reset=0; initial
always #5 reset=!reset; begin //initially all red lights ON
endmodule Ra=1; Rb=1; Rc=1; Rd=1;
Ya=0; Ga=0; Yb=0; Gb=0;
Yc=0; Gc=0; Yd=0; Gd=0;
//T_FF: end
module tff(q,q0,qt1,t,clk,reset); always
input t,clk,reset; begin
output q,q0,qt1; Ra<=#1 0;#1 Ya= 1;
reg q,q0,qt1; Ya<=#1 0;#1 Ga= 1;
initial Ga<=#10 0;#10 Ya=1;
qt1=0; Ra<=#1 1;#1 Ya=0;
always @(negedge clk) Rb<=#0 0;#0 Yb=1;
begin Yb<=#1 0;#1 Gb=1;
if(t==0&&reset==0) Gb<=#10 0;#10 Yb=1;
begin Rb<=#1 1;#1 Yb=0;
q=qt1; Rc<=#0 0;#0 Yc=1;
q0=!q; Yc<=#1 0;#1 Gc=1;
end Gc<=#10 0;#10 Yc=1;
else if(t==1&&reset==0) Rc<=#1 1;#1 Yc=0;
begin Rd<=#0 0;#0 Yd=1;
q=!qt1; Yd<=#1 0;#1 Gd=1;
q0=!q; Gd<=#10 0;#10 Yd=1;
end Rd<=#1 1;#1 Yd=0;
else end
begin endmodule
q=0;
q0=1; module testtraffic(); //stimulus module
end wire Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd;
qt1=q; traffic t (Ra,Ya,Ga,Rb,Yb,Gb,
end Rc,Yc,Gc,Rd,Yd,Gd);
endmodule endmodule
module ttff();
reg t,clk,reset;
wire q,q0,qt1;
tff tff0(q,q0,qt1,t,clk,reset);
initial
clk=0;
always #1 clk=!clk;
initial
t=0;
always #2 t=!t;
// traffic signals with control input
module traffic(Ra,Ya,Ga,Rb,Yb,Gb,
Rc,Yc,Gc,Rd,Yd,Gd,cont);
Output reg Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd;
input cont;
initial
begin //initially all red lights ON
Ra=1; Rb=1; Rc=1; Rd=1;
Ya=0; Ga=0; Yb=0; Gb=0;
Yc=0; Gc=0; Yd=0; Gd=0;
end
always
begin
Ra<=#1 0;#1 Ya= 1;
Ya<=#1 0;#1 Ga= 1;
if(cont==0)
begin Ga<=#10 0;#10 Ya=1; end
if(cont==1)
begin Ga<=#5 0;#5 Ya=1; end
Ra<=#1 1;#1 Ya=0;
Rb<=#0 0;#0 Yb=1;
Yb<=#1 0;#1 Gb=1;
if(cont==0)
begin Gb<=#10 0;#10 Yb=1; end
if(cont==1)
begin Gb<=#5 0;#5 Yb=1; end
Rb<=#1 1;#1 Yb=0;
Rc<=#0 0;#0 Yc=1;
Yc<=#1 0;#1 Gc=1;

if(cont==0)
begin Gc<=#10 0;#10 Yc=1; end
if(cont==1)
begin Gc<=#5 0;#5 Yc=1; end
Rc<=#1 1;#1 Yc=0;
Rd<=#0 0;#0 Yd=1;
Yd<=#1 0;#1 Gd=1;
if(cont==0)
begin Gd<=#10 0;#10 Yd=1; end
if(cont==1)
begin Gd<=#5 0;#5 Yd=1; end
Rd<=#1 1;#1 Yd=0;
end
endmodule
module testtraffic(); //stimulus module
wire Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd;
reg cont;
traffic
t(Ra,Ya,Ga,Rb,Yb,Gb,Rc,Yc,Gc,Rd,Yd,Gd,cont);
initial
cont=0;
always #50 cont=!cont;
endmodule