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  • Lab 6: Traffic Light Controller: 1. Open A New Project by Issuing "File - New Project"

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    Subha Murugan
    43 vizualizări11 pagini
    This document provides instructions for a lab assignment to design a traffic light controller using Verilog and FPGA implementation. The steps include: 1) Creating a new project and modules for the traffic light controller, counter, and clock using Verilog; 2) Checking syntax and generating schematic symbols for the modules; 3) Creating a schematic file to interconnect the modules on an FPGA with appropriate I/O pins.

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    Lab6-2006(Traffic Light Controller)

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    This document provides instructions for a lab assignment to design a traffic light controller using Verilog and FPGA implementation. The steps include: 1) Creating a new project and modules for the traffic light controller, counter, and clock using Verilog; 2) Checking syntax and generating schematic symbols for the modules; 3) Creating a schematic file to interconnect the modules on an FPGA with appropriate I/O pins.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOC, PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    43 vizualizări11 pagini

    Lab 6: Traffic Light Controller: 1. Open A New Project by Issuing "File - New Project"

    Încărcat de

    Subha Murugan
    This document provides instructions for a lab assignment to design a traffic light controller using Verilog and FPGA implementation. The steps include: 1) Creating a new project and modules for the traffic light controller, counter, and clock using Verilog; 2) Checking syntax and generating schematic symbols for the modules; 3) Creating a schematic file to interconnect the modules on an FPGA with appropriate I/O pins.

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca DOC, PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    din 11

    Lab 6: Traffic Light Controller

    , chengys@csie.nctu.edu.tw , jenchieh@csie.nctu.edu.tw 1. EC616 EC616

    Open a new project by issuing File -> New Project.

    i.

    Click

    7-1

    2.

    ii. Click iii. Click iv. Click v. Click Create a new module by issuing Project > New Source Create a verilog file traffic_light.v .

    (You can copy it from the class handout)

    7-2

    3.

    Save the file and issue Synthesis-> Check syntax by doubling click.

    7-3

    4.

    Create the schematic symbol of the module traffic_light.v by doubling click.

    5.

    If no syntax error, create a new verilog module by issuing Project > New Source. Create a verilog file bc_4b_ce_aclr.v

    7-4

    6.

    Start HDL Editor and create macro for a 4-bit binary counter with a clock enable and an asynchronous reset inputs.

    7.

    Save the file and issue Synthesis-> Check syntax by double click.

    7-5

    8.

    Create the schemaric symbol of the module bc_4b_ce_aclr.v by doubling click.

    9.

    Create another module named clk12Hz to generate 11.9 Hz clock, check syntax and then create the symbol of the module clk12Hz.

    7-6

    10. In Project Manager window, issue Project -> New Source. Create a schematic file named trf_ltc.
    7-7

    11. In Schematic Editor window Xilinx ESC, create your design at here.

    7-8

    12. In addition, assign input and output pads to appropriate pins of the FPGA.

    Double click trf_ltc_pin.ucf.

    7-9

    13. Simulate, implement and download your design.

    Requirements:
    A. Design a two-way traffic light controller. G g g ? H G

    7-10

    F B. Refer to the FSM as shown in class-handout. C. Design clock, counter and controller modules using verilog code. D. The top module must implemented in schematic design, cannot use verilog code. (Pin connection:) CAR -> P62 HG -> p5 HY -> p4 HR -> p3 FG- > p9 FY -> p8 FR -> p6

    7-11

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