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DB-25 Connector
and Cable JTAG Header

J3 R1 D2 D1 J2

15
VCC SENSE 1 VCC
100
D ERROR 1N5817 1N5817 D
(WHITE) FPGA Header
J1 Notes:
R13
R14 R8 1 VCC
U2
1K
C5
(1) All resistors
5.1K
100 74HC125 0.01UF 1/8W, 5%, SMT
J3 R2
13
DONE 3 2 J2 unless otherwise
100 2 noted.
SELECT 1 GND
GND
GND J1
(BROWN)

74HC125 2 GND (2) D6, BUSY, and PE


R9 J2
2 3 4
connected at the
TDO
1
100 DB25 end of data
U1 J1
GND
cable.
C1 4 D/P
100PF
C C
J3 R3 (3) U1 and U2 power:
6
PROG
300 GND VDD - pin 14
D4
(BLUE) GND - pin 7
U1
74HC125 J2
J3 R4 R10
2
DIN 5 6
5
300
TDI
D0 4 100
J1 U2
(RED)
C2 5 74HC125
100PF
DIN
J3 R5 5 6
5
CTRL
300 4
D3 GND
(GREEN)
U1 U2
74HC125 74HC125
J2
J3 R6 R11
3
CLK 9 8 3 9 8
300
TCK
B 100 B
D1 10 J1 10
(ORANGE) C3
3 CCLK
100PF U2
74HC125

12 11
GND
13
U1
74HC125 J2
J3 R7 R12 GND
4
TMS_IN 12 11
6
300
TMS
100
D2 13
(YELLOW) J1
C4
6 PROG
J3 100PF
20

GND GND See note (2)


GND
(BLACK) J3
J3
8
D6
A 25 A
J3
11
BUSY Title: JTAG/Parallel Download Cable
SHIELD
Comments:
J3
PC Chassis 12
PE
Ground Date:July 10, 1996 Ver:02
CGND Sheet Size: B Rev:

4 3 2 1

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Xilinx customers. Xilinx Inc. and its employees
shall not be held financially or legally
responsible for any usage or application
of this information.

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