Library IEEE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port( clk,wr,cs,rd,cw: in std_logic;
crm,crl,sr:in std_logic_vector( 7 downto 0);
olm,oll: out std_logic_vector(7 downto 0);
ot: inout std_logic;
gate: in std_logic);
end counter;
architecture Behavioral of counter is
signal s: std_logic;
signal c: std_logic:='1';
signal temp: std_logic_vector(15 downto 0);
signal temp2: std_logic_vector(15 downto 0);
signal lm: std_logic_vector(1 downto 0);
signal mo: std_logic_vector(2 downto 0);
begin
process(clk,wr,cs,gate,cw,rd,sr,crl,crm,c,temp)
variable temp1: std_logic_vector(15 downto 0);
begin
if clk='1' and clk'event then
if cs='0' then
if cw='1' then
mo(2)<= sr(3);
--CHIP SELECT
--FOR CONTROL WORD
--FOR SELECTING THE MODES
mo(1)<= sr(2);
mo(0)<= sr(1);
lm(1)<=sr(5);
--FOR LOADING THE VALUE
lm(0)<=sr(4);
--else
--------------------------------MODE 0-----------------------------------------case mo is
when"000"=>
--MODE SELECTOR
if rd='1' then
case wr is
when '0'=>
case lm is --LOADING OF VALUE
when "01" =>
temp1(7 downto 0):=crl(7 downto 0);
temp1(15 downto 8):="00000000";
ot<= '0';
when "10"=>
temp1(7 downto 0):="00000000";
temp1(15 downto 8):=crm(7 downto 0);
ot<= '0';
when "11" =>
ot<= '0';
when others =>
null;
end case;
when '1' =>--write 1
if sr(0)='0' then
--BINARY COUNTING
case gate is
when '1'=>
--GATE=1
--if clk='1' and clk'event then

if c='1' then
oll(7 downto 0)<=temp1(7 downto 0) ;
olm(7 downto 0)<=temp1(15 downto 8);
else
null;
end if;
temp1:= temp1 - '1';
if temp1="1111111111111111" then
ot<= '1';
end if;
--end if;
when '0'=>
--GATE=0
if c='1' then
else
null;
end if;
when others =>null;
end case;
else
null;
end if;
--BCD COUNTING
when others => null;

end case;
else
case lm is
when "01" =>
--SIMPLE READ OPERATION

olm(7 downto 0)<="00000000";
when "10"
=>
oll(7 downto 0)<="00000000" ;

when "11" =>
when "00" =>
--COUNTER LATCH COMMAND

when others =>
null;
end case;
end if;
------------------------------------------------MODE 1-----------------------------------------------------
when "001"=>
if rd ='1' then
if wr ='0' then
if gate='1' then--and gate'event then
case lm is --LOADING VALUE
when "01" => crl0(7 downto 0) := data;
temp1(7 downto 0):= crl(7 downto 0);
temp1(15 downto 8):="00000000";
when "10"=>crm0(7 downto 0) := data;
temp1(7 downto 0):="00000000";
when "11" =>
when others=>
null;
end case;
if s='1' then
ot<='0';
else
ot<='1' ;
s<='0';
end if;
end if;
if gate='0' then
if sr(0)='0' then --BINARY COUNTING
if clk='1' and clk'event then
temp1:= temp1- '1';
if c='1' then
else
null;
end if;
if s='0' then
ot<= '0';
end if;
if temp1="0000000000000000" then
if c='1' then
else
null;
end if;
ot<= '1';
s<= '1';
end if;
--end if;
else
null;
-- BCD COUNTING
end if;
end if;
else
null;
end if;
else
case lm is
when "01" =>
--SIMPLE READ

olm(7 downto 0)<="00000000";
when "10"
=>
oll(7 downto 0)<="00000000" ;

when "11" =>
when "00" => --COUNTER LATCH COMMAND

when others=>
null;
end case;
end if;
----------------------------------------------MODE 2------------------------------------------------------when "010" | "110"=>
if rd='1' then
if gate ='1' then
case wr is
when '0' =>
ot<= '1';
case lm is
when "01" =>
temp1(15 downto 8):="00000000";
when "10"=>
temp1(7 downto 0):="00000000";
when "11"
=>

when "00" =>
c<='0';
when others=>
null;
end case;
when '1' =>
ot<='1';
if c='1' then
else
null;
end if;
if gate='0' then
if c='1' then
else
null;
end if;
end if;
if temp1="0000000000000000" then
ot<= '0';
case lm is
when "01"
=>

temp1(15 downto 8):="00000000";
when "10"
=>
temp1(7 downto 0):="00000000";

when "11"
=>

when others=>
null;
end case;
end if;
--end if;
end case;
end if;
else
case lm is
when "01" =>

olm(7 downto 0)<="00000000";
when "10"
=>
oll(7 downto 0)<="00000000" ;

when "11" =>oll(7 downto 0)<=temp1(7 downto 0) ;
when "00" =>oll(7 downto 0)<=temp1(7 downto 0) ;
when others=>
null;
end case;
end if;
---------------------------------------------MODE 3-------------------------------------------------------when "011" | "111"=>
if rd='1' then
s<='0';
if gate ='1' then
case wr is
when '0'=>
ot<='1';
case lm is
when "01" =>
temp(7 downto 0)<=crl(7 downto 0);
temp(15 downto 8)<="00000000";
when "10"
=>
temp(7 downto 0)<="00000000";

temp(15 downto 8)<=crm(7 downto 0);
when "11" =>
when "00" =>
c<='0';
end case;
when '1' =>
if sr(0)='0' then -- BINARY COUNTING
case temp(0) is
when '0' =>
--EVEN COUNT

if c='1' then
else
null;
end if;
temp<= temp - "0000000000000010";
if temp="0000000000000010" then
if c='1' then
else
null;
end if;
ot <= not ot;-- after 10 ns;
case lm is
when "01" =>
temp(15 downto 8)<="00000000";
when "10"
=>
temp(7 downto 0)<="00000000";

when "11"
=>

when others=>
null;
end case;
end if;
--end if;
when '1' =>
--ODD COUNT
temp<=temp-"0000000000000001";
if c='1' then
else
null;
end if;
temp<= temp - "0000000000000010";
if temp="0000000000000000" then
s<='1';
if c='1' then
else
null;
end if;
ot <= not ot;-- after 10 ns ;
case lm is
when "01" =>
temp2(7 downto 0)<=crl(7 downto 0);
temp2(15 downto 8)<="00000000";
temp2<=temp2-"0000000000000001";
when "10" =>
temp2(7 downto 0)<="00000000";
temp2(15 downto 8)<=crm(7 downto 0);
temp2<=temp2-"0000000000000001";
when "11" =>
temp2(7 downto 0)<=crl(7 downto 0);
temp2(15 downto 8)<=crm(7 downto 0);
temp2<=temp2-"0000000000000001";
when others=>
null;
end case;
if c='1' then
else
null;
end if;
temp2<= temp2 - "0000000000000010";
if temp2="0000000000000010" then
if c='1' then
else
null;
end if;
ot <= not ot;-- after 50 ns ;
end if;
--end if;
end if;
--end if;
when others=>
null;
end case;
end if;
when others=>
null;
end case;
else
if ot<='0' then
ot<='1';
oll(7 downto 0)<=temp(7 downto 0);
olm(7 downto 0)<=temp(15 downto 8);

else
oll(7 downto 0)<=temp(7 downto 0);
olm(7 downto 0)<=temp(15 downto 8);
end if;
end if;
else
case lm is
when "01" =>
olm(7 downto 0)<="00000000";
when "10"
=>
oll(7 downto 0)<="00000000" ;

when "11" =>
when "00" =>
when others=>
null;
end case;
end if;
---------------------------------------------MODE 4-------------------------------------------------------when "100"=>
if rd='1' then
if gate ='1'then
case wr is
when '0'=>
ot<='1';
case lm is
when "01" =>
temp1(15 downto 8):="00000000";

when "10" =>
temp1(7 downto 0):="00000000";
when "11" =>
when "00" =>
c<='0';
when others =>
null;
end case;
when '1' =>
if sr(0)='0' then ---BINARY COUNTING
ot<='1';
if c='1' then
else
null;
end if;
if temp1="1111111111111111" then
ot<= '0';
end if;
if temp1="0000000000000000" then
ot<= '1';
end if;
--end if;
end if;
when others=>
null;
end case;
else
if wr='1' then
if c='1' then
else
null;
end if;
ot<='1';
case lm is
when "01" =>
temp1(15 downto 8):="00000000";
when "10" =>
temp1(7 downto 0):="00000000";
when "11" =>
when others =>
null;
end case;
end if;
end if;
else
case lm is
when "01" =>
olm(7 downto 0)<="00000000";
when "10"
=>
oll(7 downto 0)<="00000000" ;

when "11" =>

when "00" =>
when others=>
null;
end case;
end if;
----------------------------------------------MODE 5------------------------------------------------------when "101"=>
if rd='1' then
if wr ='0' then
if gate='1' then--and gate'event then
case lm is
when "01" =>
temp1(15 downto 8):="00000000";
when "10"
=>
temp1(7 downto 0):="00000000";

when "11" =>
when "00" =>
c<='0';
when others=>
null;
end case;
ot<='1' ;
end if;
if gate='0' then
if sr(0)='0' then ---BINARY COUNTING
if c='1' then

else
null;
end if;
ot<= '1';
--end if;
if temp1="1111111111111111" then
ot<= '0';
end if;
else
null;
-- BCD COUNTING
end if;
end if;
else
null;
end if;
else
case lm is
when "01" =>
olm(7 downto 0)<="00000000";
when "10" =>
oll(7 downto 0)<="00000000" ;
when "11" =>
when "00" =>
when others=>
null;
end case;
end if;
---------------------------------------------------------------------------------------------------------------when others =>
null;
end case;
end if;
else
null;
end if;
end if;
end process;
end Behavioral;
4.3 VHDL code for timer 8254 main block

library IEEE;
entity timer is
port (dd: inout std_logic_vector(7 downto 0);
clock,rdbar,wrbar,csbar:in std_logic;
aa:in std_logic_vector(1 downto 0);
outt:inout std_logic_vector(2 downto 0);
gate:in std_logic_vector(2 downto 0) );
end timer;
architecture Behavioral of timer is

component rwlo
port (clk,rd,wr,cs:in std_logic;
a:in std_logic_vector(1 downto 0);
z:out std_logic_vector(3 downto 0);
red:out std_logic_vector(2 downto 0);
wri:out std_logic_vector(2 downto 0)
);
end component;
component counter
port(gate:in std_logic;clk,wr,cs,rd,cw:in std_logic;
crm,crl,sr:in std_logic_vector( 7 downto 0);
olm,oll:out std_logic_vector(7 downto 0);
ot:inout std_logic);
end component;
signal ztemp:std_logic_vector(3 downto 0);
signal writemp:std_logic_vector(2 downto 0);
signal redtemp:std_logic_vector(2 downto 0);
signal crmtemp0,crmtemp1,crmtemp2:std_logic_vector (7 downto 0);
signal crltemp0,crltemp1,crltemp2:std_logic_vector (7 downto 0);
signal srtemp0,srtemp1,srtemp2:std_logic_vector (7 downto 0);
signal timer_cs, lsb:std_logic:='0';
signal ctrl_word : std_logic_vector(7 downto 0);
signal sc, rw : std_logic_vector(1 downto 0);
begin
r0:rwlo port map (clk=>clock,rd=>rdbar,wr=>wrbar,cs=>csbar,a=>aa,z=>ztemp,
wri=>writemp,red=>redtemp);
c0:counter port map (gate=>gate(0),clk=>clock,wr=>writemp(0),cs=>ztemp(0),
rd=>redtemp(0),cw=>ztemp(3),crm=>crmtemp0,crl=>crltemp0,
sr=>ctrl_word,ot=>outt(0));
c1:counter port map (gate=>gate(1),clk=>clock,wr=>writemp(1),
cs=>ztemp(1),crm=>crmtemp1,crl=>crltemp1,sr=>ctrl_word,
rd=>redtemp(1),cw=>ztemp(3),ot=>outt(1));
c2:counter port map (gate=>gate(2),clk=>clock,wr=>writemp(2),cs=>
ztemp(2),crm=>crmtemp2,crl=>crltemp2,sr=>ctrl_word,
rd=>redtemp(2),cw=>ztemp(3),ot=>outt(2));
ctrl_word <= dd when aa="11" and rising_edge(clock);
sc <= ctrl_word(7 downto 6);
rw <= ctrl_word(5 downto 4);
process(wrbar, csbar, clock)
begin
if wrbar='0' and csbar='0' and rising_edge(clock) then
if aa="11" then
lsb <= '1';
else
lsb <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if csbar='0' and wrbar='0' then
case aa is
when "00" => --counter0
case rw is
when "01" =>
crltemp0 <= dd;
when "10" =>
crmtemp0 <= dd;
when "11" =>
if lsb='1' then
crltemp0 <= dd;
else
crmtemp0 <= dd;
end if;
when others=>null;
end case;
when "01" => --counter

case rw is
when "01" =>
crltemp1 <= dd;
when "10" =>
crmtemp1 <= dd;
when "11" =>
if lsb='1' then
crltemp1 <= dd;
else
crmtemp1 <= dd;
end if;
when others=>null;
end case;
when "10" => --counter2
case rw is
when "01" =>
crltemp2 <= dd;
when "10" =>
crmtemp2 <= dd;
when "11" =>
if lsb='1' then
crltemp2 <= dd;
else
crmtemp2 <= dd;
end if;
when others=>null;
end case;
when others=>null;
end case;
elsif csbar='0' and rdbar='0' then
null;--fill in read operation code to write olm and oll onto dd
end if;
end if;
end process;
end Behavioral;
4.4 VHDL Code for Bi-directional Buffer

library IEEE;
entity bi_buffer is
Port ( going_out : in STD_LOGIC_VECTOR (7 downto 0);
coming_in : out STD_LOGIC_VECTOR (7 downto 0);
bidir : inout STD_LOGIC_VECTOR (7 downto 0);
ena : in STD_LOGIC);
end bi_buffer;
architecture Behavioral of bi_buffer is
signal hi_impedance:std_logic_vector(bidir'range):=(others=>'Z');
begin
bidir<=std_logic_vector(going_out) when ena='1' else hi_impedance;
coming_in<=std_logic_vector(bidir);
end Behavioral;
4.5 VHDL Code for Uni -Directional Buffer

library IEEE;
entity uni_buffer is
Port ( coming_in : in STD_LOGIC_VECTOR (7 downto 0);
going_out : out STD_LOGIC_VECTOR (7 downto 0);
unidir : inout STD_LOGIC_VECTOR (7 downto 0);
ena1 : in STD_LOGIC);
end uni_buffer;
architecture Behavioral of uni_buffer is
signal hi_impedance:std_logic_vector(unidir'range):=(others=>'Z');
begin
unidir<=std_logic_vector(coming_in) when ena1='0' else hi_impedance;
going_out<=std_logic_vector(unidir);
end Behavioral;
4.6 VHDL Code for Decoder

library IEEE;
entity dec3to8 is
Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
g1,g2a,g2b : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end dec3to8;
architecture Behavioral of dec3to8 is
signal sel:std_logic_vector(7 downto 0);
begin
--sel<=((not_g2a & not_g2b)&g1)&a;
with a select sel<=
"11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others ;
y<=sel when (g1 and not g2a and not g2b)='1' else "11111111";
end Behavioral;

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library IEEE;

--FOR LOADING THE VALUE

--if clk='1' and clk'event then

when others => null;

--SIMPLE READ OPERATION

oll(7 downto 0)<=temp1(7 downto 0) ;

oll(7 downto 0)<="00000000" ;

--COUNTER LATCH COMMAND

oll(7 downto 0)<=temp1(7 downto 0) ;

oll(7 downto 0)<=temp1(7 downto 0) ;

oll(7 downto 0)<="00000000" ;

olm(7 downto 0)<=temp1(15 downto 8);

temp1(7 downto 0):=crl(7 downto 0);

temp1(7 downto 0):=crl(7 downto 0);

temp1(7 downto 0):="00000000";

temp1(7 downto 0):=crl(7 downto 0);

oll(7 downto 0)<=temp1(7 downto 0) ;

oll(7 downto 0)<="00000000" ;

temp(7 downto 0)<="00000000";

--if clk='1' and clk'event then

temp(7 downto 0)<="00000000";

temp(7 downto 0)<=crl(7 downto 0);

olm(7 downto 0)<=temp(15 downto 8);

oll(7 downto 0)<="00000000" ;

temp1(15 downto 8):="00000000";

oll(7 downto 0)<="00000000" ;

olm(7 downto 0)<=temp1(15 downto 8);

temp1(7 downto 0):="00000000";

oll(7 downto 0)<=temp1(7 downto 0) ;

4.3 VHDL code for timer 8254 main block

architecture Behavioral of timer is

when "01" => --counter

4.4 VHDL Code for Bi-directional Buffer

4.5 VHDL Code for Uni -Directional Buffer

4.6 VHDL Code for Decoder

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