Government Engineering College

Thrissur

2004

Seminar Paper on

AC PERFORMANCE OF NANOELECTRONICS

Presented by

SYAM KRISHNAN . V
Roll N0: 01-656
S7 ECE

Department of Electronics and Communication Engineering

 ACKNOWLEDGEMENT

I express my sincere thanks to Prof. K.P.Indira Devi, Head of the Electronics and
Communication Engineering Department at this juncture for her suggestions in the selection
of this topic and the presentation of this seminar.

I also take this opportunity to express my wholehearted gratitude towards Asst.Prof.

MUNEERA C R and Mr. C.D. Anilkumar for their valuable advice and guidance in
completion of this seminar in its pristine form.

I am also thankful to all my friends and classmates who helped me to make this
seminar a grand success.
 ABSTRACT

The phenomenological predictions for the cutoff frequency of carbon nanotube transistors and the
predictions of the effects of parasitic capacitances on AC nanotube transistor performance are
presented. The influence of quantum capacitance, kinetic inductance, and ballistic transport on the
high-frequency properties of nanotube transistors is analyzed. The challenges of impedance
matching for ac nano-electronics in general, and how integrated nanosystems can solve this
challenge, are presented.
 CONTENTS

1.Introduction 1

2.Ballistic Transport- An outline 2

3.Carbon Nanotubes -An overview 9

4.Nanotube Interconnects: quantum Impedances 12

5.Active devices: Nanotube transistors 14

6.Relevant frequency scale 15

7.Small signal equivalent circuit 16

8.Cutoff Frequency 19

9.Noise performance 20

10.Challenges: Impedance matching 21

11.Beyond Microelectronics 22

12.Conclusion 24

13.References 25
 Introduction

Nano electronic devices fall into two classes: tunnel devices and ballistic transport devices. In
Tunnel devices single electron effects occur if the tunnel resistance is larger than h/e″ = 25 KΩ. In
Ballistic devices with cross sectional dimensions in the range of quantum mechanical wavelength of
electrons, the resistance is of order h/e″ = 25 KΩ. This high resistance may seem to restrict the
operational speed of nano electronics in general. However the capacitance values and drain source
spacing are typically small which gives rise to very small RC times and transit times of order of ps
or less. Thus the speed may be very large, up to THz range.

The goal of this seminar is to present the models an performance predictions about the
effects that set the speed limit in carbon nanotube transistors, which form the ideal test bed for
understanding the high frequency properties of Nano electronics because they may behave as ideal

ballistic 1d transistors.

1
BALLISTIC TRANSPORT- AN OUTLINE

When carriers travel through a semiconductor material, they are likely to be scattered by any number
of possible sources, including acoustic and optical phonons, ionized impurities, defects, interfaces,
and other carriers. If, however, the distance traveled by the carrier is smaller than the mean free path,
it is likely not to encounter any scattering events; it can, as a result, move ballistically through the
channel. To the first order, the existence of ballistic transport in a MOSFET depends on the value of
the characteristic scattering length (i.e. mean free path) in relation to channel length of the transistor.
This scattering length, l , can be estimated from the measured carrier mobility

where t is the average scattering time, m* is the carrier effective mass, and vth is the thermal
velocity. Because scattering mechanisms determine the extent of ballistic transport, it is important to
understand how these depend upon operating conditions such as normal electric field and ambient
temperature.

DEPENDENCE ON NORMAL ELECTRIC FIELD

In state-of-the-art MOSFET inversion layers, carrier scattering is dominated by phonons, impurities

(Coulomb interaction), and surface roughness scattering at the Si-SiO2 interface. As shown in Figure
2, the relative importance of each scattering mechanism is dependent on the effective electric field
component normal to the conduction channel. At low fields, impurity scattering dominates due to
strong Coulombic interactions between the carriers and the impurity centers. As the electric field is
increased, acoustic phonons begin to dominate the scattering process. At very high fields, carriers
are pulled closer to the Si-SiO2 gate oxide interface; thus, surface roughness scattering degrades

2
carrier mobility. A universal mobility model has been developed to relate field strength with the

effective carrier mobility due to phonon and surface roughness scattering:

where Vgs is the applied gate voltage, VT is the transistor threshold voltage, Tox is the gate oxide
thickness, and m0 and Ecrit are empirically-derived constants. As predicted by the International
Technology Roadmap for Semiconductors ,device technologies at near ballistic (~30nm) channel
lengths will have power supplies of <0.8V, VT<0.2V, Tox,eq~10Å. This yields an effective electric
field of approximately ~1MV/cm. The actual value may be lower, depending on the actual device
structure and operating conditions. With doping concentrations in the channel region of the
MOSFET expected to be on the order of 1018, from ,we find that the electron mobility is ~230
cm2/Vsec and the hole mobility is ~65 cm2/Vsec at room temperature. This yields scattering lengths
of approximately 5.5nm and 2.4nm.

3
DEPENDENCE ON TEMPERATURE

When the temperature is changed, the relative importance of each of the aforementioned scattering
mechanisms is altered. Phonon scattering becomes less important at very low temperatures. Impurity
scattering, on the other hand, becomes more significant because carriers are moving slower (thermal
velocity is decreased) and thus have more time to interact with impurity centers. Surface roughness
scattering remains the same because it does not depend on temperature. At liquid nitrogen
temperatures (77K) and an effective electric field of 1MV/cm, the electron and hole mobilities are
~700 cm2/Vsec and ~100 cm2/Vsec, respectively. Using the above equations, the scattering lengths
are approximately 17nm and 3.6nm.These scattering lengths can be assumed to be worst-case
scenarios, as large operating voltages (1V) and aggressively scaled gate oxides (10Å) are assumed.
Thus, actual scattering lengths will likely be larger than the calculated values. Further device design
considerations in maximizing this scattering length will be discussed in the last section of this paper.
Still, the values calculated above are certainly in the range of transistor gate lengths currently being
studied in advanced MOSFET research (<50nm). Ballistic carrier transport should thus become
increasingly important as transistor channel lengths are further reduced in size. In addition, it should
be noted that the mean free path of holes is generally smaller than that of electrons. Thus, it should
be expected that ballistic transport in PMOS transistors is more difficult to achieve, since current
conduction occurs through hole transport. Calculation of the mean scattering length, however, can
only be regarded as a first-order estimation of ballistic transport. To accurately determine the extent
of ballistic transport evident in a particular transistor structure, Monte Carlo simulation methods
must be employed .Only by modeling the random trajectory of each carrier traveling through the
channel can we truly assess the extent of ballistic transport in a MOSFET. Comparison of scattering
length with the device channel length can nevertheless provide a useful way of ascertaining whether
ballistic transport effects should be considered.

4
EFFECTS OF BALLISTIC TRANSPORT IN MOSFET’S

If carrier transport in a device can be assumed to be completely ballistic, analysis of MOSFET

currentvoltage characteristics reduces to carrier transmission over the channel potential barrier. As
shown in figure 3, the potential energy distribution in the channel of the transistor has a maximum,
Emax, near the source end of the device. Carriers with a higher energy than Emax can be transmitted
over the barrier through the process of thermionic emission. Carriers with lower energies can travel
from source to drain only by tunneling quantum mechanically through the channel potential barrier.
Such transport phenomena is markedly different from that generally associated with mobility-limited
diffusive transport. As a result, the current-voltage characteristics of MOSFET’s operating in the
ballistic regime will be different.

5
 ACHIEVING BALLISTIC TRANSPORT IN DEEPLY-SCALED MOSFET’S

As evidenced by preceding sections, ballistic transport allows for larger transistor saturation currents
because carriers are experience no scattering. Designing future transistors to maximize the likelihood
of ballistic transport is thus highly desirable. As shown ,simply by shrinking current transistor
designs, a significant step can be taken towards this goal. However, modifications to the operating
conditions or to the device structure itself may help to further induce ballistic transport. Recently,
much interest has been placed on thin body double-gate MOSFET designs (Figure 4) due to its
superior immunity to detrimental short-channel effects. This structure, in particular, lends itself to
the promotion of ballistic carrier transport due to its low-doped channel and dual-gate nature. The
following briefly describes some techniques that may be used in the design of future transistor
technologies to minimize carrier scattering, thus promoting ballistic transport. The primary goal is to
reduce the likelihood of scattering events in the MOSFET inversion layer and increase the mean free
path. Minimizing surface roughness scattering Because of the large electric fields experienced by
carriers in MOSFET inversion layers, scattering is due predominately to interface roughness. To
minimize the impact of this scattering mechanism, the problem can be attacked from two
perspectives: improving the Si-SiO2 interface quality, and decreasing the normal electric field. The
former will indeed reduce surface roughness scattering, but there is little room for improvement as
current semiconductor process technologies are quite mature and yield very clean and smooth
interfaces. Even so, it may be helpful to take precautions during processing to ensure a good
interface; this may include ion implantation through a screen oxide, sacrificial oxidation steps to
clean up surfaces after reactive ion etching, or dry as opposed to wet oxidation techniques.
Decreasing the normal electric field is a more viable option. As mentioned earlier, the normal
electric field can be expressed as:

6
To decrease the normal electric field, either the power supply voltage (which becomes the applied
Vgs) must be scaled down or the oxide thickness must be increased. Lowering of the power supply is
already a widespread trend, mainly due to power dissipation and device reliability concerns.
However, this results in a smaller inversion charge density and thus a smaller current. As such, a
tradeoff in current drive can be observed between minimization of carrier scattering and the decrease
in inversion charge. There is likely an optimum point for the choice of supply voltage. Normally,
gate oxide thickness is decreased in advanced transistor technologies to combat short channel effects
and to improve the ability to “turn off” the transistor. However, a thicker gate oxide may allow for
ballistic transport, which may decrease the effective field, increase current, and result in an overall
advantage. The double-gate MOSFET structure (Figure 4) is particularly attractive for this option
because two gate electrodes exist to help to control channel conductivity, the gate oxide thickness
need not be as thin to achieve small gate lengths. Additionally, in the double-gate MOSFET
structure, because there are two gate electrodes on opposite sides of the conduction channel, it is
reasonable to assume that the two will have a canceling effect on the normal electric field component
in the middle of the silicon body . This should, in turn, reduce surface roughness scattering in the
inversion layer. If indeed the normal electric field component is reduced in double-gate MOSFET’s,
it may be much easier to achieve ballistic-mode transport in these devices.

MINIMIZING PHONON SCATTERING

Phonons resulting from vibrations in the silicon lattice are principally controlled by the ambient
temperature. Decreasing the operating temperature of a transistor reduces phonon scattering and
increases the carrier transmission coefficient and thus the likelihood of ballistic transport.
Transmission coefficients as high as 92% have been obtained at liquid nitrogen temperatures (77K).
However, low temperature operation, while interesting from an academic standpoint, is not attractive

7
for practical applications as the cooling system required to achieve such temperatures is complex and
expensive.

MINIMIZING IMPURITY SCATTERING

In order to alleviate the impact of impurity scattering, the doping concentration in the channel region
needs to be low. In a standard transistor design, because of concerns with the short-channel effect
and threshold voltage control, doping concentrations in the channel need to be very high (~1018 cm-
3). In order to decouple channel doping from these issues, super-steep retrograde doping profiles or
lightlydoped epitaxial channel layers need to be employed. The double-gate MOSFET structure
described in Figure 4, however, already considers the use of a low-doped channel region. Short-
channel effects are controlled using the dual-gate structure, while threshold voltage is dictated by the
workfunction of gate material. Thus, impurity scattering can be minimized with this device structure.
As previously mentioned, in transistors operating near the ballistic regime, carrier scattering will
likely dominated by surface roughness mechanisms. Thus, addressing effective normal electric field
as well as Si-SiO2 interface quality will be of utmost concern in achieving ballistic transport.
Furthermore, additional device design issues will have to be resolved before the full benefits of
ballistic transport are realized. Most importantly, parasitic resistances in the source and drain
terminals of the device due either to shallow source/drain junctions or the thin body region of the
double-gate device will be significant. These may result in resistive voltage drops that are
detrimental to device performance, thus masking any benefits attained from ballistic carrier
transport.

8
 CARBON NANOTUBES – AN OVERVIEW

The remarkable properties of SWNT(single wire nanotube) stems from the unusual electronic
structure of the two dimensional material graphene from which they are constructed. Graphene is a
single atomic layer of graphite which consists of a 2D honey comb structure of sp² bonded carbon
atoms.

Fig 1.the honey comb structure of grapheme

It is sometimes called zero band semiconductors since it is semiconducting in some directions and
metallic in the other directions. In a SWNT,the momentum of the electrons moving around the
circumference of the tube is quantized, reducing the available states to slice through the 2-D band
structure. This shown in fig 2.

9
 fig 2

The CNTFET technology is at an early stage of development. The device physics is Relatively
unexplored: it is not clear that how the device operates or whether devices grown with different
structures and techniques operate in the same way. Most of the times, CNTFETs are categorized in
three types as shown in the fig. 3.

DEPLETION MODE P-CNTFET

In this type, the nanotube is uniformly doped and the contacts at the two endsare ohmic. In
such a device, the on-current would be limited by the ‘source exhaustion’ Id (on) = qplvt, where pl is
the hole density per unit length.

MOSFET LIKE CNTFET

In this type of nanotube transistors, the conductance of channel is controlled by the gate as in a
MOSFET.This is supported by the fact that some long channel CNTFETs Obeys the MOSFET
square law theory and no ambipolar behavior is observed in these Devices. Some recent CNTFETs

10
that behaves as MOSFET like devices, have demonstrated performance that is many orders of
magnitude better than current stateof-the-art MOSFETs .

SCHOTTY BARRIER CNTFETS

Another possibility is that the CNTFET operates as “Schottky barrier transistors” in which
transistor action takes place primarily by varying the contact resistance rather than the channel
conductance. This is supported by the observations of ambipolar behavior in some CNTFETs. The
observation of ambipolar operation in some CNTFETs and the transition of the tube from n-type to
p-type indicate that some CNTFETs operate as unconventional Schottky barrier transistors. In such a
device, the gate modulates the transmission through a Schottky barrier and the transistor action takes
place primarily by varying the contact resistance rather than the channel conductance. In addition,
the electrode geometry is crucial for good device performance.

AMBIPOLAR BEHAVIOR

The CNTFETs measured in air are unipolar with p type characteristics, i.e. the tube conducts
holes upon applying negative gate voltages and they show no evidence of electron conduction even
at very large gate voltages. The origin of this p-type character of semiconducting SWNT is still not
clearly understood. Several proposals have been made to explain this effect including contact
doping, doping introduced by cleaning or handling the nanotube in oxidizing acids, or doping by the
adsorption of atmospheric oxygen.In principle any of the above mechanism can influence the
transistor characteristics. The device is said to be ambipolar when it behaves like n-type or p-type
depending on the applied gate voltage i.e. it shows large conduction for both positive and negative

gate voltages.

11
NANOTUBE INTERCONNECTS: QUANTUM IMPEDANCES

The first step towards understanding the high frequency electronic properties of carbon
nanotubes is to understand the passive ac impedance of a 1d quantum system. In the presence of a
ground plane below the nanotube or top gate above the nanotube, there is electrostatic capacitance
between the nano tube and the metal. Due to quantum properties of 1d systems there are two
additional components to the ac impedance: the quantum capacitance and the kinetic inductance.
Thus the equivalent circuit of a nanotube consists of 3 distributed circuit elements as shown in fig 1
and fig 2.

12
 ELECTROSTATIC CAPACITANCE

The electrostatic capacitance between a wire and a ground plane as shown in fig1 is given
by where the approximation holds good to within 1% for h > 2d. For a typical value if h/d, this
wire length can be approximated numerically as

QUANTUM CAPACITANCE

Because of the finite quantum energy level spacing of electrons in 1d, it costs
energy to add an electron to the system. By equating this energy cost ∆E with an effective Quantum
capacitance, one arrives at the following expression for capacitance per unit length:

Where h is the Planck’s constant and νF is the fermi velocity. The fermi velocity for graphene
and also carbon nano tubes is usually taken as νF = 8x 10ˆ5 m/s, so that numerically,

KINETIC INDUCTANCE

Due to inertia of electrons, the instantaneous velocity lags the instantaneous electric field
in time. This means the current lags the phase, which can be described as a kinetic inductance. For
1d systems we have the following expression for the kinetic energy per unit length:

13
 Numerically,

BAND STRUCTURE, SPIN DEGENERACY

A carbon nanotube, because of its band structure has two propagating Channels. In
addition the electrons can be spin up or spin down. Hence there are four channels. Ta king this to
account, we show that the circuit model in fig 2 is valid if LK -> LK/4 and CQ -> 4CQ.

ACTIVE DEVICES: NANOTUBE TRANSISTORS

A typical nanotube transistor geometry is shown below in fig3.

The fundamental physical mechanism responsible for transistor action in nanotube Transistor
action in nano tube transistors is still not completely understood. One action of the gate may be to
modulate the (Schottky barrier) contact resistance Complicating the issue is the question whether the
transport is diffusive or ballistic Experiments indicate that the mean free path in semi conducting

14
nanotubes at room Temperature is at least 1µm, so that nano tubes shorter than 1µm may behave as
ballistic transistors.

RELEVANT FREQUENCY SCALES

The frequency scales for most important processes : the RC time and the transconductance are
estimated.

RC TIME

The most important effect for high frequency performance is the RC time. For Typical
Nanotube geometry of 0.1µm length ,C is of order 4 aF. R can be as small as 6.25kΩ.Therefore
the RC frequency is given by

This shows that the speed limit due to RC times intrinsic to a nanotube transistor very large
indeed.

TRANSCONDUCTANCE

The transconductance gm over the gate source capacitance Cgs sets another important Frequency.
Using experimentally measured value of 10µS, this gives

The above estimates indicate that a carbon nano tube transistor could be very fast,inspite its
high impedance. For more realistic estimates of device performance a small signal equivalent
circuit is considered

15
SMALL SIGNAL EQUIVALENT CIRCUIT

In fig 4, we show the predicted small signal circuit model for a nano tube transistor

In the following sections we discuss each of the important components

GATE SOURCE CAPACITANCE

The gate source capacitance is given by

The quantum capacitance is multiplied by 4 because of the band structure

degeneracy

16
TRANSCONDUCTANCE

The transconductance is the most critical parameter the underlying mechanism is the least
understood. Transconductances upto 20µS have been measured using aqueous gate geometry.
A transconductance of 60 µS was recently predicted by simulation.

DRAIN RESISTANCE

In Fig. 4, gd represents the output impedance of the device, if it does not appear as an ideal
current source. The gd values from various source for nanotube transistor are 0.03 µS Tans S,
Verschueren A, Dekker C

1 µS Martel R, Schmidt T, Shea HR

0.6 µS Burke P J

SERIES RESISTANCE

In most conventional transistors the series resistance consists of the metallization layer and the
ohmic contact resistance. We argue that, in nanotube transistors, the intrinsic contact resistance
will be of order the resistance quantum because of the 1d Nature of the system. At dc, the lowest
value of resistance possible for a carbon nanotube is h/4e″. This is because there are four channels
for conductance in the Landauer–Buttiker formalism, each contributing h/e″ to the conductance.
To date very little experimental work has been done to measure the ac impedance of ballistic
systems. From a theoretical point of view, Buttiker and Christen have carefully analyzed the
case of a capacitive contact to a ballistic conductor (in his case a 2DEG without scattering) in
contact with one dc electrical lead through a quantum point contact. They found that the ac
impedance from gate to lead includes a real part,equal to half the resistance quantum h/2e″. Based
on this work we argue that a reasonable value for the contact resistance in our small signal model

17
would be h/2e″ per channel. Since there are channels in parallel this a contact resistance of h/8e″.
There will be an additional imaginary contribution to the contact resistance due to kinetic
inductance on the order of a few nH.

PARASITIC CAPACITANCE

The parasitic capacitance is due to fringing electric fields between the electrodes for the source,
drain and gate. While these parasitic capacitance are generally small, they may comparable to
the intrinsic device capacitances and hence must be considered.In order to estimate the order of
magnitude of the parasitic capacitance, we can use known calculations for the capacitance
between two thin metal films, spaced by a distance w, as drawn in Fig. 5. For this geometry,
if w is 1µm, the capacitance is ~ 10^-16 F/lm of electrode length . For a length of 1µm, this
gives rise to ~10^-16 F. Thus, typical parasitic capacitances are of the same order of
magnitude as typical intrinsic capacitances.

18
CUTOFF FREQUENCY

The estimates of the cutoff frequency fT, defined as the frequency at which the current gain falls to
unity are provided in this section . Based on fig 4, fT is given by

here p represent parasitic, Using the experimentally measured transconductance of 10 µs, a

parasitic capacitance value of 10^-16 F, and a Cgs of 4 x 10^-17 F (appropriate for a 1 lm long
tube), we predict a cutoff frequency of 8 GHz. For this value, the parasitic capacitance is the
most important contribution. Thus, minimizing the parasitic capacitance is of prime importance in
increasing fT for nanotube transistors.

PARASITIC CAPACITANCE

While the above calculations show that the parasitic capacitance is important, in principle it
should be possible to significantly reduce the parasitic capacitance by detailed electrode
geometry design. Another (better) way to reduce the parasitic capacitance would be to use the
nanotube itself as an interconnect electrode from one nanotube transistor to another. Then, the
parasitic capacitance would be dramatically smaller than that with lithographically fabricated
electrodes.

SCALING WITH LENGTH

If we assume that the parasitic capacitance can be reduced to negligible Values , the equation
simplifies to

19
 Cgs scales linearly with gate length, and was calculated above. In the ballistic limit, gm
should be independent of gate length. Using the largest measured transconductance to date of
20 µs, this gives rise to the following prediction for fT

In fig 6, we plot the predictions for fT vs gatelength for a nano tube transistor and

Compare it to other technologies.

NOISE PERFORMANCE

One promising potential application is in low-noise analog microwave amplification circuits.

Recent work on noise in mesoscopic systems has been extensive and has shown suppressed noise
due to the Pauli exclusion principle . Since electrons can travel without scattering from source to
drain, and the Pauli exclusion principle suppresses the current noise, it may be possible to
engineer extremely low noise microwave amplifiers using carbon nanotubes, possibly even

approaching the quantum limit of sensitivity.

20
CHALLENGES: IMPEDANCE MATCHING

Nano-devices generally have high resistance values, of order the resistance quantum RQ =
h/e″. At high frequencies, for driving circuits more the one electromagnetic wavelength away
from the device, the load impedance is typically of order of the characteristic impedance of
free space, Zc = ( ∝є )½ .The ratio of ZC /RQ = (1/137) has a special significance in physics
and is called the fine structure constant; it is set by only three fundamental constants of nature:
e, h, and c. For electrical engineering, this means that nanodevices will always need impedance
matching circuits when driving loads more than a few cm away at RF and microwave
frequencies. Integration can provide a solution to this problem. For nano-electronic devices
closely spaced, down to the nano-scale, the capacitive loading from one device to the next can
be minimized. For full effect, the interconnects should be nano-scale as well; lithographically
fabricated interconnects may be too large to realize the full potential of nano-electronics. Our
work on the high frequency electrical properties of active and passive nano-devices provides a
very small step towards achieving this ultimate goal of integrated nanosystems.
BEYOND MICROELECTRONICS
21
Nanoelectronics is not simply a smaller version of microelectronics; things change at the nanoscale.
At the device level, silicon transistors may give way to new materials such as organi molecules or
inorganic nanowires. At the interconnect level, microelectronics uses long, fat wires, but
nanoelectronics seeks to use short nanowires. Finally, fundamentally new architectures will be
needed to make use of simple, locally connected structures that are imperfect and are comprised of
devices whose performance varies widely. I have argued in this paper that 21st century silicon
technology is rapidly evolving into a true nanotechnology. Critical dimensions are already below
100 nm. The materials used in these silicon devices have properties that differ from the bulk.
Nanoscale silicon transistors have higher leakage, lower-drive current, and exhibit more variability
from device to device. New circuits and architectures will need to be developed to accommodate
such devices. It matters little whether the material is silicon or something else, the same issues face
any nanoelectronics technology. It’s likely that many of the advances and breakthroughs at the
circuits and systems levels that will be needed to make nanoelectronics successful will come from
the silicon design community. Given that we have a nanoelectronics technology and that another 20
years of exponential progress in silicon technology can be expected (leading to terascale integration,
why explore radically new technologies? One reason, of course, is that 20 years is not a long time to
develop fundamentally new technologies, so that we need to start now, but there are other reasons.
The most compelling practical reason is that the fabrication and assemblyprocesses and the
materials, device, circuit, and system understanding that we develop by examining radically new
technologies are almost certain to be useful in silicon nanotechnology. Developing an understanding
of how to engineer devices at the nanoscale is a good reason to support nanoscience research.
Another reason is that devices to complement silicon technology might be discovered. For example,
carbon nanotube FETs could be exquisite single molecule detectors, and single electron devices
could be integrated with MOSFETs for high density memory applications. Another possibility is
molecular structures that improve the performance of a CMOS platform. For example, ballistic
CNTs could be high performance interconnects and efficient at heat removal. Nanowire
thermoelectric cooling could lower chip temperature and increase performance. So there are several
good reasons to expect that research on nanoelectronics will prove to be a good investment. The

22
successful development of nanoelectronics will require a partnership between science and
engineering. It was the same for semiconductor technology. The scientific community developed the
understanding of semiconductor materials and physics and the engineering community used this base
to learn how to design devices, circuits, and systems. Figure 5 summarizes this partnership. Science
works in the nanoworld with individual atoms, molecules, nanoscale structures and devices, and
assembly processes. Systems engineers work in the macroworld on complex systems with terascale
device densities. In the middle are the device and circuit engineers. They must learn to think and
work at the nanoscale to build devices and circuits that can connect to the macroworld. Their job is
to hide the complexity of the nanoscale device by packaging it in a form that systems engineers can
use (e.g. a compact circuit model). To turn the promise of nanoscience into practical technologies, it
is essential that the systems engineering community be engaged in the effort.

23
CONCLUSION

The phenomenological predictions for the ac performance of nanotube Transistors were

presented. It was predicted that carbon nanotube transistors may be faster than conventional
semiconductor technologies. There are many Challenges that must be overcome to meet this goal,
which can be best be achieved by the integration of Nanosystems

24
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1. Burke PJ. “An RF circuit model for carbon nanotubes”. IEEE Transactions on

Nanotechnology 2003;2(1):55–8.

2. Burke PJ. “ Luttinger liquid theory as a model of the GHz electrical properties of

carbon nanotubes”. IEEE Transactions on Nanotechnology 2002;1(3):129–44.

3. Nauman Z. Butt, “ Carbon-NanoTube Transistors”

4. McEuen PL, Fuhrer M, Park H. “Single-walled carbon nanotube electronics”. IEEE

Transactions on Nanotechnology 2002;1(1):78-85;

1. Burke PJ. “An RF circuit model for carbon 1. Burke PJ.

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