Addressing Modes

Table 4-10. Instruction Set Summary (Sheet 1 of 8)

Address Mode Source Form
ADC ADC ADC ADC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD ADD #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Operation

Object Code
A9 B9 C9 D9 E9 F9 9E D9 9E E9 AB BB CB DB EB FB 9E DB 9E EB ii dd hh ll ee ff ff ee ff ff ii dd hh ll ee ff ff ee ff ff

Add with Carry A (A) + (M) + (C)

IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM

Cycles
2 3 4 4 3 2 5 4 2 3 4 4 3 2 5 4 2

Affect on CCR Cyc-by-Cyc Details V11H INZC

pp prp pprp pppr ppr pr ppppr pppr pp prp pprp pppr ppr pr ppppr pppr pp

1 1

Add without Carry A (A) + (M)

1 1

AIS #opr8i

Add Immediate Value (Signed) to Stack Pointer SP (SP) + (M) Add Immediate Value (Signed) to Index Register (H:X) H:X (H:X) + (M)

A7 ii

1 1

AIX #opr8i AND AND AND AND AND AND AND AND #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

IMM IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

AF ii A4 B4 C4 D4 E4 F4 9E D4 9E E4 ii dd hh ll ee ff ff ee ff ff

2 2 3 4 4 3 2 5 4 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4

pp pp prp pprp pppr ppr pr ppppr pppr prwp p p pprw prw ppprw prwp p p pprw prw ppprw pdp prwp prwp prwp prwp prwp prwp prwp prwp

1 1

Logical AND A (A) & (M)

0 1 1

ASL opr8a ASLA ASLX ASL oprx8,X ASL ,X ASL oprx8,SP ASR opr8a ASRA ASRX ASR oprx8,X ASR ,X ASR oprx8,SP BCC rel

Arithmetic Shift Left

C b7 b0 0

(Same as LSL) Arithmetic Shift Right

C b7 b0

38 dd 48 58 68 ff 78 9E 68 ff 37 dd 47 57 67 ff 77 9E 67 ff 24 rr 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd

1 1

1 1

Branch if Carry Bit Clear (if C = 0)

1 1

BCLR n,opr8a

Clear Bit n in Memory (Mn 0)

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 50 Freescale Semiconductor

Instruction Set Summary

Table 4-10. Instruction Set Summary (Sheet 2 of 8)

Address Mode Source Form
BCS rel BEQ rel BGE rel BGT rel BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT BIT BIT BIT BIT BIT BIT BIT #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Operation
Branch if Carry Bit Set (if C = 1) (Same as BLO) Branch if Equal (if Z = 1) Branch if Greater Than or Equal To (if N V = 0) (Signed) Branch if Greater Than (if Z | (N V) = 0) (Signed) Branch if Half Carry Bit Clear (if H = 0) Branch if Half Carry Bit Set (if H = 1) Branch if Higher (if C | Z = 0) Branch if Higher or Same (if C = 0) (Same as BCC) Branch if IRQ Pin High (if IRQ pin = 1) Branch if IRQ Pin Low (if IRQ pin = 0)

Object Code

REL REL REL REL REL REL REL REL REL REL IMM DIR EXT IX2 IX1 IX SP2 SP1 REL REL REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL

Cycles
3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 5 4 3 3 3 3 3 3 3 3 3 3

Affect on CCR Cyc-by-Cyc Details V11H INZC

pdp pdp pdp pdp pdp pdp pdp pdp pdp pdp pp prp pprp pppr ppr pr ppppr pppr pdp pdp pdp pdp pdp pdp pdp pdp pdp pdp prpdp prpdp prpdp prpdp prpdp prpdp prpdp prpdp pdp 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

25 rr 27 rr 90 rr 92 rr 28 rr 29 rr 22 rr 24 rr 2F rr 2E rr A5 B5 C5 D5 E5 F5 9E D5 9E E5 ii dd hh ll ee ff ff ee ff ff

Bit Test (A) & (M) (CCR Updated but Operands Not Changed)

0 1 1

BLE rel BLO rel BLS rel BLT rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel

Branch if Less Than or Equal To (if Z | (N V) = 1) (Signed) Branch if Lower (if C = 1) (Same as BCS) Branch if Lower or Same (if C | Z = 1) Branch if Less Than (if N V = 1) (Signed) Branch if Interrupt Mask Clear (if I = 0) Branch if Minus (if N = 1) Branch if Interrupt Mask Set (if I = 1) Branch if Not Equal (if Z = 0) Branch if Plus (if N = 0) Branch Always (if I = 1)

93 rr 25 rr 23 rr 91 rr 2C rr 2B rr 2D rr 26 rr 2A rr 20 rr 01 03 05 07 09 0B 0D 0F dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BRCLR n,opr8a,rel

Branch if Bit n in Memory Clear (if (Mn) = 0)

5 5 5 5 5 5 5 5 3

1 1

BRN rel

Branch Never (if I = 0)

21 rr

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 Freescale Semiconductor 51

Addressing Modes

Table 4-10. Instruction Set Summary (Sheet 3 of 8)

Address Mode Source Form Operation Object Code
00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr

BRSET n,opr8a,rel

Branch if Bit n in Memory Set (if (Mn) = 1)

DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)

Cycles
5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4

Affect on CCR Cyc-by-Cyc Details V11H INZC

prpdp prpdp prpdp prpdp prpdp prpdp prpdp prpdp prwp prwp prwp prwp prwp prwp prwp prwp

1 1

BSET n,opr8a

Set Bit n in Memory (Mn 1)

1 1

BSR rel

Branch to Subroutine PC (PC) + $0002 push (PCL); SP (SP) $0001 push (PCH); SP (SP) $0001 PC (PC) + rel Compare and... Branch if (A) = (M) Branch if (A) = (M) Branch if (X) = (M) Branch if (A) = (M) Branch if (A) = (M) Branch if (A) = (M)

REL

AD rr

pssp

1 1

CBEQ opr8a,rel CBEQA #opr8i,rel CBEQX #opr8i,rel CBEQ oprx8,X+,rel CBEQ ,X+,rel CBEQ oprx8,SP,rel CLC CLI CLR opr8a CLRA CLRX CLRH CLR oprx8,X CLR ,X CLR oprx8,SP CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

DIR IMM IMM IX1+ IX+ SP1 INH INH DIR INH INH INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 IMM DIR

31 41 51 61 71 9E 61 98 9A

dd ii ii ff rr ff

rr rr rr rr rr

5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 2 3 4 4 3 2 5 4 4 1 1 4 3 5 3 4

pprdp ppdp ppdp pprdp prdp ppprdp p pd pwp p p p ppw pw pppw pp prp pprp pppr ppr pr ppppr pppr prwp p p pprw prw ppprw ppp prrp

1 1

Clear Carry Bit (C 0) Clear Interrupt Mask Bit (I 0) Clear M $00 A $00 X $00 H $00 M $00 M $00 M $00

1 1 0 1 1 0

3F dd 4F 5F 8C 6F ff 7F 9E 6F ff A1 B1 C1 D1 E1 F1 9E D1 9E E1 ii dd hh ll ee ff ff ee ff ff

0 1 1 0 1

Compare Accumulator with Memory AM (CCR Updated But Operands Not Changed)

1 1

COM opr8a COMA COMX COM oprx8,X COM ,X COM oprx8,SP CPHX #opr CPHX opr

Complement M (M)= $FF (M) (Ones Complement) A (A) = $FF (A) X (X) = $FF (X) M (M) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) Compare Index Register (H:X) with Memory (H:X) (M:M + $0001) (CCR Updated But Operands Not Changed)

33 dd 43 53 63 ff 73 9E 63 ff 65 ii jj 75 dd

0 1 1

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 52 Freescale Semiconductor

Instruction Set Summary

Table 4-10. Instruction Set Summary (Sheet 4 of 8)

Address Mode Source Form
CPX CPX CPX CPX CPX CPX CPX CPX DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP DIV EOR EOR EOR EOR EOR EOR EOR EOR #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Operation

Object Code
A3 B3 C3 D3 E3 F3 9E D3 9E E3 72 3B 4B 5B 6B 7B 9E 6B dd rr rr rr ff rr rr ff rr ii dd hh ll ee ff ff ee ff ff

IMM DIR EXT Compare X (Index Register Low) with Memory IX2 XM IX1 (CCR Updated But Operands Not Changed) IX SP2 SP1 Decimal Adjust Accumulator After ADD or ADC of BCD Values INH

Cycles
2 3 4 4 3 2 5 4 2 5 3 3 5 4 6 4 1 1 4 3 5 7

Affect on CCR Cyc-by-Cyc Details V11H INZC

pp prp pprp pppr ppr pr ppppr pppr pp pprwp pdp pdp pprwp prwp ppprwp prwp p p pprw prw ppprw pdpdddd pp prp pprp pppr ppr pr ppppr pppr prwp p p pprw prw ppprw pp ppp ppdp pdp pp pssp ppssp ppssdp pssdp pssp

1 1

U 1 1

DIR INH Decrement A, X, or M and Branch if Not Zero INH (if (result) 0) IX1 DBNZX Affects X Not H IX SP1 Decrement M (M) $01 A (A) $01 X (X) $01 M (M) $01 M (M) $01 M (M) $01 DIR INH INH IX1 IX SP1 INH IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX

1 1

3A dd 4A 5A 6A ff 7A 9E 6A ff 52 A8 B8 C8 D8 E8 F8 9E D8 9E E8 ii dd hh ll ee ff ff ee ff ff

1 1

Divide A (H:A)(X); H Remainder Exclusive OR Memory with Accumulator A (A M)

1 1

2 3 4 4 3 2 5 4 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4

0 1 1

INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP JMP JMP JMP JMP JMP JSR JSR JSR JSR JSR opr8a opr16a oprx16,X oprx8,X ,X opr8a opr16a oprx16,X oprx8,X ,X

Increment

M (M) + $01 A (A) + $01 X (X) + $01 M (M) + $01 M (M) + $01 M (M) + $01

3C dd 4C 5C 6C ff 7C 9E 6C ff BC CC DC EC FC BD CD DD ED FD dd hh ll ee ff ff dd hh ll ee ff ff

1 1

Jump PC Jump Address

1 1

Jump to Subroutine PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) $0001 Push (PCH); SP (SP) $0001 PC Unconditional Address

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 Freescale Semiconductor 53

Addressing Modes

Table 4-10. Instruction Set Summary (Sheet 5 of 8)

Address Mode Source Form
LDA LDA LDA LDA LDA LDA LDA LDA #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Operation

Object Code
A6 B6 C6 D6 E6 F6 9E D6 9E E6 ii dd hh ll ee ff ff ee ff ff

Load Accumulator from Memory A (M)

IMM DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR IMM DIR EXT IX2 IX1 IX SP2 SP1 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 DIR/DIR DIR/IX+ IMM/DIR IX+/DIR INH DIR INH INH IX1 IX SP1 INH INH IMM DIR EXT IX2 IX1 IX SP2 SP1

Cycles
2 3 4 4 3 2 5 4 3 4 2 3 4 4 3 2 5 4 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3

Affect on CCR Cyc-by-Cyc Details V11H INZC

pp prp pprp pppr ppr pr ppppr pppr ppp prrp pp prp pprp pppr ppr pr ppppr pppr prwp p p pprw prw ppprw prwp p p pprw prw ppprw prpwp prwp ppwp prwp ppddd prwp p p pprw prw ppprw p ppd pp prp pprp pppr ppr pr ppppr pppr

0 1 1

LDHX #opr LDHX opr LDX LDX LDX LDX LDX LDX LDX LDX #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Load Index Register (H:X) H:X (M:M + $0001)

45 ii jj 55 dd AE BE CE DE EE FE 9E DE 9E EE ii dd hh ll ee ff ff ee ff ff

0 1 1

Load X (Index Register Low) from Memory X (M)

0 1 1

LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a MUL NEG opr8a NEGA NEGX NEG oprx8,X NEG ,X NEG oprx8,SP NOP NSA ORA ORA ORA ORA ORA ORA ORA ORA #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Logical Shift Left

C b7 b0 0

(Same as ASL) Logical Shift Right

0 b7 b0 C

38 dd 48 58 68 ff 78 9E 68 ff 34 dd 44 54 64 ff 74 9E 64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E 60 ff 9D 62 AA BA CA DA EA FA 9E DA 9E EA ii dd hh ll ee ff ff ee ff ff dd dd dd ii dd dd

1 1

1 1 0

Move (M)destination (M)source In IX+/DIR and DIR/IX+ Modes, H:X (H:X) + $0001 Unsigned multiply X:A (X) (A) Negate M (M) = $00 (M) (Twos Complement) A (A) = $00 (A) X (X) = $00 (X) M (M) = $00 (M) M (M) = $00 (M) M (M) = $00 (M) No Operation Uses 1 Bus Cycle Nibble Swap Accumulator A (A[3:0]:A[7:4])

0 1 1

1 1 0 0

1 1

1 1 1 1

Inclusive OR Accumulator and Memory A (A) | (M)

2 3 4 4 3 2 5 4

0 1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 54 Freescale Semiconductor

Instruction Set Summary

Table 4-10. Instruction Set Summary (Sheet 6 of 8)

Address Mode Source Form
PSHA PSHH PSHX PULA PULH PULX ROL opr8a ROLA ROLX ROL oprx8,X ROL ,X ROL oprx8,SP ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP RSP

Operation
Push Accumulator onto Stack Push (A); SP (SP) $0001 Push H (Index Register High) onto Stack Push (H); SP (SP) $0001 Push X (Index Register Low) onto Stack Push (X); SP (SP) $0001 Pull Accumulator from Stack SP (SP + $0001); Pull (A) Pull H (Index Register High) from Stack SP (SP + $0001); Pull (H) Pull X (Index Register Low) from Stack SP (SP + $0001); Pull (X) Rotate Left through Carry
C b7 b0

Object Code

INH INH INH INH INH INH DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 INH

Cycles
2 2 2 2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1

Affect on CCR Cyc-by-Cyc Details V11H INZC

ps ps ps pu pu pu prwp p p pprw prw ppprw prwp p p pprw prw ppprw p 1 1 1 1 1 1 1 1 1 1 1 1

87 8B 89 86 8A 88 39 dd 49 59 69 ff 79 9E 69 ff 36 dd 46 56 66 ff 76 9E 66 ff 9C

1 1

Rotate Right through Carry

C b7 b0

1 1

Reset Stack Pointer (Low Byte) SPL $FF (High Byte Not Affected) Return from Interrupt SP (SP) + $0001; SP (SP) + $0001; SP (SP) + $0001; SP (SP) + $0001; SP (SP) + $0001; Pull (CCR) Pull (A) Pull (X) Pull (PCH) Pull (PCL)

1 1

RTI

INH

80

puuuuup

1 1

RTS SBC SBC SBC SBC SBC SBC SBC SBC SEC SEI #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Return from Subroutine SP SP + $0001; Pull (PCH) SP SP + $0001; Pull (PCL)

INH IMM DIR EXT IX2 IX1 IX SP2 SP1 INH INH

81 A2 B2 C2 D2 E2 F2 9E D2 9E E2 99 9B ii dd hh ll ee ff ff ee ff ff

4 2 3 4 4 3 2 5 4 1 2

puup pp prp pprp pppr ppr pr ppppr pppr p pd

1 1

Subtract with Carry A (A) (M) (C)

1 1

Set Carry Bit (C 1) Set Interrupt Mask Bit (I 1)

1 1 1 1 1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 Freescale Semiconductor 55

Addressing Modes

Table 4-10. Instruction Set Summary (Sheet 7 of 8)

Address Mode Source Form
STA STA STA STA STA STA STA opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

Operation

Object Code
B7 C7 D7 E7 F7 9E D7 9E E7 dd hh ll ee ff ff ee ff ff

Store Accumulator in Memory M (A)

DIR EXT IX2 IX1 IX SP2 SP1 DIR

Cycles
3 4 4 3 2 5 4 4

Affect on CCR Cyc-by-Cyc Details V11H INZC

pwp ppwp pppw ppw pw ppppw pppw pwwp

0 1 1

STHX opr

Store H:X (Index Reg.) (M:M + $0001) (H:X) Enable Interrupts: Stop Processing Refer to MCU Documentation I bit 0; Stop Processing

35 dd

0 1 1

STOP STX STX STX STX STX STX STX SUB SUB SUB SUB SUB SUB SUB SUB opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP

INH DIR EXT IX2 IX1 IX SP2 SP1 IMM DIR EXT IX2 IX1 IX SP2 SP1

8E BF CF DF EF FF 9E DF 9E EF A0 B0 C0 D0 E0 F0 9E D0 9E E0 dd hh ll ee ff ff ee ff ff ii dd hh ll ee ff ff ee ff ff

1 3 4 4 3 2 5 4 2 3 4 4 3 2 5 4

p pwp ppwp pppw ppw pw ppppw pppw pp prp pprp pppr ppr pr ppppr pppr

1 1 0

Store X (Low 8 Bits of Index Register) in Memory M (X)

0 1 1

Subtract A (A) (M)

1 1

SWI

Software Interrupt PC (PC) + $0001 Push (PCL); SP (SP) $0001 Push (PCH); SP (SP) $0001 Push (X); SP (SP) $0001 Push (A); SP (SP) $0001 Push (CCR); SP (SP) $0001 I 1; PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte Transfer Accumulator to CCR CCR (A) Transfer Accumulator to X (Index Register Low) X (A) Transfer CCR to Accumulator A (CCR) Test for Negative or Zero (M) $00 (A) $00 (X) $00 (M) $00 (M) $00 (M) $00

INH

83

psssssvvp

1 1 1

TAP

INH

84

pd

1 1

TAX

INH

97

1 1

TPA TST opr8a TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP TSX

INH DIR INH INH IX1 IX SP1 INH

85 3D dd 4D 5D 6D ff 7D 9E 6D ff 95

1 3 1 1 3 2 4 2

p prp p p ppr pr pppr pp

1 1

0 1 1

Transfer SP to Index Reg. H:X (SP) + $0001

1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 56 Freescale Semiconductor

Opcode Map

Table 4-10. Instruction Set Summary (Sheet 8 of 8)

Address Mode Source Form
TXA TXS WAIT

Operation
Transfer X (Index Reg. Low) to Accumulator A (X) Transfer Index Reg. to SP SP (H:X) $0001 Enable Interrupts; Wait for Interrupt I bit 0; Halt CPU

Object Code

INH INH INH

Cycles
1 2 1

Affect on CCR Cyc-by-Cyc Details V11H INZC

p pp p 1 1 1 1 1 1 0

9F 94 8F

Object Code: dd Direct address of operand ee ff High and low bytes of offset in indexed, 16-bit offset addressing ff Offset byte in indexed, 8-bit offset addressing hh ll High and low bytes of operand address in extended addressing ii Immediate operand byte ii jj 16-bit immediate operand for H:X rr Relative program counter offset byte Addressing Modes: DIR Direct addressing mode EXT Extended addressing mode IMM Immediate addressing mode INH Inherent addressing mode IX Indexed, no offset addressing mode IX1 Indexed, 8-bit offset addressing mode IX2 Indexed, 16-bit offset addressing mode IX+ Indexed, no offset, post increment addressing mode IX1+ Indexed, 8-bit offset, post increment addressing mode REL Relative addressing mode SP1 Stack pointer, 8-bit offset addressing mode SP2 Stack pointer 16-bit offset addressing mode

Operation Symbols: A Accumulator CCR Condition code register H Index register high byte M Memory location n Any bit opr Operand (one or two bytes) PC Program counter PCH Program counter high byte PCL Program counter low byte rel Relative program counter offset byte SP Stack pointer SPH Most significant byte of stack pointer SPL Least significant byte of stack pointer X Index register low byte & Logical AND | Logical OR Logical EXCLUSIVE OR () Contents of ( ) Negation (twos complement) # Immediate value Sign extend Loaded with ? If : Concatenated with Cycle-by-Cycle Codes: d Dummy duplicate of the previous p, r, or s cycle. d is always a read cycle so sd is a stack write followed by a read of the address pointed to by the updated stack pointer p Program fetch; read from next consecutive location in program memory r Read 8-bit operand s Push (write) eight bits onto stack u Pop (read) eight bits from stack v Read vector from $FFxx (high byte first) w Write 8-bit operand

CCR Bits, Effects: V Overflow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit Set or cleared Not affected U Undefined

4.4 Opcode Map

The opcode map is provided in Table 4-11.

CPU08 Central Processor Unit Reference Manual, Rev. 4 Freescale Semiconductor 57

58

Addressing Modes

Table 4-11. Opcode Map

Bit-Manipulation DIR DIR HIGH Branch REL DIR INH Read-Modify-Write INH IX1 Control SP1 IX INH INH IMM DIR EXT Register/Memory IX2 SP2 IX1 SP1 IX

0
LOW 5

1
4

2
3

3
4

4
1

5
1

6
4

9E6
5

7
3

8
7

9
3

A
2

B
3

C
4

D
4

9ED
5

E
3

9EE
4

F
2

0 1 2

BRSET0
3 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR 5 DIR

BSET0
2 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2 4 DIR 2

BRA
REL 2 3

NEG
DIR 1 5

NEGA
INH 1 4 IMM 3 5

NEGX
INH 2 4 IMM 3 7

NEG
IX1 3 5

NEG
SP1 1 6

NEG
IX 1 4

RTI
INH 2 4

BGE
REL 2 3

SUB
IMM 2 2

SUB
DIR 3 3

SUB
EXT 3 4

SUB
IX2 4 4

SUB
SP2 2 5

SUB
IX1 3 3

SUB
SP1 1 4

SUB
IX 2

BRCLR0 BCLR0
3 2

BRN
REL 3 3

CBEQ

CBEQA MUL
1

CBEQX DIV
INH 1 1

CBEQ
IX1+ 4 3

CBEQ
SP1 2

CBEQ
IX+ 1 2

RTS
INH 2

BLT
REL 2 3

CMP
IMM 2 2

CMP
DIR 3 3

CMP
EXT 3 4

CMP
IX2 4 4

CMP
SP2 2 5

CMP
IX1 3 3

CMP
SP1 1 4

CMP
IX 2

DIR 3

BRSET1
3

BSET1
2

BHI
REL 3 4

NSA
INH 4 1 5

DAA
INH 3 2 9

BGT
REL 2 3

SBC
IMM 2 2

SBC
DIR 3 3

SBC
EXT 3 4

SBC
IX2 4 4

SBC
SP2 2 5

SBC
IX1 3 3

SBC
SP1 1 4

SBC
IX 2

INH 1 1

CPU08 Central Processor Unit Reference Manual, Rev. 4 Freescale Semiconductor

3 4 5 6 7 8 9 A B C D E F

BRCLR1 BCLR1
3 2

BLS
REL 2 3

COM
DIR 1 4

COMA
INH 1 1

COMX
INH 2 1

COM
IX1 3 4

COM
SP1 1 5

COM
IX 1 3

SWI
INH 2 2

BLE
REL 2 2

CPX
IMM 2 2

CPX
DIR 3 3

CPX
EXT 3 4

CPX
IX2 4 4

CPX
SP2 2 5

CPX
IX1 3 3

CPX
SP1 1 4

CPX
IX 2

BRSET2
3

BSET2
2

BCC
REL 2 3

LSR
DIR 1 4

LSRA
INH 1 3

LSRX
INH 2 4

LSR
IX1 3 3

LSR
SP1 1

LSR
IX 1 4

TAP
INH 1 1

TXS
INH 2 2

AND
IMM 2 2

AND
DIR 3 3

AND
EXT 3 4

AND
IX2 4 4

AND
SP2 2 5

AND
IX1 3 3

AND
SP1 1 4

AND
IX 2

BRCLR2 BCLR2
3 2

BCS
REL 2 3

STHX
DIR 3 4

LDHX
IMM 2 1

LDHX
DIR 3 1

CPHX
IMM 4 2 5

CPHX
DIR 1 3

TPA
INH 1 2

TSX
INH 2

BIT
IMM 2 2

BIT
DIR 3 3

BIT
EXT 3 4

BIT
IX2 4 4

BIT
SP2 2 5

BIT
IX1 3 3

BIT
SP1 1 4

BIT
IX 2

BRSET3
3

BSET3
2

BNE
REL 2 3

ROR
DIR 1 4

RORA
INH 1 1

RORX
INH 2 1

ROR
IX1 3 4

ROR
SP1 1 5

ROR
IX 1 3

PULA
INH 2 2 1

LDA
IMM 2 2

LDA
DIR 3 3

LDA
EXT 3 4

LDA
IX2 4 4

LDA
SP2 2 5

LDA
IX1 3 3

LDA
SP1 1 4

LDA
IX 2

BRCLR3 BCLR3
3 2

BEQ
REL 2 3

ASR
DIR 1 4

ASRA
INH 1 1

ASRX
INH 2 1

ASR
IX1 3 4

ASR
SP1 1 5

ASR
IX 1 3

PSHA
INH 1 2

TAX
INH 2 1

AIS
IMM 2 2

STA
DIR 3 3

STA
EXT 3 4

STA
IX2 4 4

STA
SP2 2 5

STA
IX1 3 3

STA
SP1 1 4

STA
IX 2

BRSET4
3

BSET4
2

BHCC
REL 2 3

LSL
DIR 1 4

LSLA
INH 1 1

LSLX
INH 2 1

LSL
IX1 3 4

LSL
SP1 1 5

LSL
IX 1 3

PULX
INH 1 2

CLC
INH 2 1

EOR
IMM 2 2

EOR
DIR 3 3

EOR
EXT 3 4

EOR
IX2 4 4

EOR
SP2 2 5

EOR
IX1 3 3

EOR
SP1 1 4

EOR
IX 2

BRCLR4 BCLR4
3 2

BHCS
REL 2 3

ROL
DIR 1 4

ROLA
INH 1 1

ROLX
INH 2 1

ROL
IX1 3 4

ROL
SP1 1 5

ROL
IX 1 3

PSHX
INH 1 2

SEC
INH 2 2

ADC
IMM 2 2

ADC
DIR 3 3

ADC
EXT 3 4

ADC
IX2 4 4

ADC
SP2 2 5

ADC
IX1 3 3

ADC
SP1 1 4

ADC
IX 2

BRSET5
3

BSET5
2

BPL
REL 2 3

DEC
DIR 1 5

DECA
INH 1 3 INH 2 1

DECX
INH 2 3 INH 3 1

DEC
IX1 3 5

DEC
SP1 1 6

DEC
IX 1 4

PULH
INH 1 2

CLI
INH 2 2

ORA
IMM 2 2

ORA
DIR 3 3

ORA
EXT 3 4

ORA
IX2 4 4

ORA
SP2 2 5

ORA
IX1 3 3

ORA
SP1 1 4

ORA
IX 2

BRCLR5 BCLR5
3 2

BMI
REL 3 3

DBNZ INC

DBNZA INCA

DBNZX INCX
INH 2 1

DBNZ
IX1 4 4

DBNZ
SP1 2 5

DBNZ
IX 1 3

PSHH
INH 1 1

SEI
INH 2 1

ADD
IMM 2

ADD
DIR 3 2

ADD
EXT 3 3

ADD
IX2 4 4

ADD
SP2 2

ADD
IX1 3 3

ADD
SP1 1

ADD
IX 2

DIR 2 4 DIR 1 3

BRSET6
3

BSET6
2

BMC
REL 2 3

INC
IX1 3 3

INC
SP1 1 4

INC
IX 1 2

CLRH
INH 1

RSP
INH 1 2 4

JMP
DIR 3 4

JMP
EXT 3 5

JMP
IX2 6 2

JMP
IX1 5 1

JMP
IX 4

INH 1 1

BRCLR6 BCLR6
3 2

BMS
REL 2 3

TST
DIR 1

TSTA
INH 1 5

TSTX
INH 2 4

TST
IX1 3 4

TST
SP1 1

TST
IX 4 1 1

NOP
INH 2

BSR
REL 2 2

JSR
DIR 3 3

JSR
EXT 3 4

JSR
IX2 4 2 5

JSR
IX1 3 1 4

JSR
IX 2

BRSET7
3

BSET7
2

BIL
REL 3 3 3

MOV
DD 2 1

MOV
DIX+ 3 1

MOV
IMD 3 2 4

MOV
IX+D 1 2

STOP
INH 1

*
1

LDX
2 IMM 2 2

LDX
DIR 3 3

LDX
EXT 3 4

LDX
IX2 4 4

LDX
SP2 2 5

LDX
IX1 3 3

LDX
SP1 1 4

LDX
IX 2

BRCLR7 BCLR7
3 2

BIH
REL 2

CLR
DIR 1

CLRA
INH 1 SP1 SP2 IX+ IX1+

CLRX
INH 2

CLR
IX1 3

CLR
SP1 1

CLR
IX 1

WAIT
INH 1

TXA
INH 2

AIX
IMM 2

STX
DIR 3

STX
EXT 3

STX
IX2 4

STX
SP2 2

STX
IX1 3

STX
SP1 1

STX
IX

INH IMM DIR EXT DD IX+D

Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset DIR/DIR IMD IMM/DIR IX+/DIR DIX+ DIR/IX+ *Pre-byte for stack pointer indexed instructions

Stack Pointer, 8-Bit Offset Stack Pointer, 16-Bit Offset Indexed, No Offset with Post Increment Indexed, 1-Byte Offset with Post Increment

High Byte of Opcode in Hexadecimal

F SUB
1 2 HC08 Cycles Opcode Mnemonic IX Number of Bytes / Addressing Mode

Low Byte of Opcode in Hexadecimal