13. (a) (i) Give a verilog structural gate level description of a bit comparator.
(ii) Give a brief account of timing control and delay in verilog.
OR (b) (i) Give a verilog structural gate level description of a ripple carry adder. (ii) Write a brief note on the conditional statements available in verilog.
) (l) uerlve expresslons for Lhe draln Lo source currenL ln Lhe nonsaLuraLed and saLuraLed reglons of operaLlon of an nMCS LranslsLor (ll) ueflne and derlve Lhe LransconducLance of nMCS LranslsLor C8 (b) (l) ulscuss Lhe small slgnal model of an nMCS LranslsLor (ll) Lxplaln Lhe CMCS lnverLer uC characLerlsLlcs What are the advantages of SOI CMOS process? What is meant by continuous assignment statement in Verilog HDL? 6. What is a task in Verilog?