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8051 AND ADVANCED PROCESSOR ARCHITECTURES

Lesson-4: Serial Data Communication Input/Output

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

Serial Interface SI
programmable for half duplex synchronous serial or full duplex asynchronous UART mode

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

Two 8-bit SFRs


SBUF (8 serial received bits or transmission bits register depending upon instruction is using SBUF as source or destination) SCON (8-serial modes cum control bits register) and SFR PCON.7 bit

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

SBUF
Single SFR address for transmit and received byte buffers when the serial output or input is sent. 0x99 the address of SI buffers. SFR holds the SI transmission 8-bits when it is written. MOV 0x99, A instruction writes A into transmission buffer from A register MOV R1, 0x99 instruction read R1s register from the receive buffer
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 4

SCON
SFR to control the SI interface. Three upper bits programs the modes as 0 or 1 or 2 or 3. Mode 0 is half duplex synchronous. Modes 1 or 2 or 3 are full duplex asynchronous modes. Bit SCON.4 enables or disables SI receiver functions.
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 5

SCON
Two bits SCON.3 and SCON.2 specify the 8th bit to be transmitted and 8th bit received when the mode is 2 or 3. A bit SCON.1 enables or disables SI transmitter interrupts (TI) on completion of transmission. Bit SCON.0 enables or disables SI receiver interrupts (RI) on completion of transmission.
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 6

Mode 0 functions Input or output


Depends upon instruction using SBUF as source or destination Synchronous serial mode data and clock inputs, or Synchronous serial mode data and clock outputs Mode 0 when SCON bits 7 and 6 (mode-bits) are 00

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

Mode 1 Input or output


10 bit (start plus 8- serial data plus stop total 10 bits) UART mode serial input or output Input or output whether SBUF used for read or write in instruction Baud rate programmable using T1 or T0 timers (T2 in 8052) Mode 1 when SCON bits 7 and 6 are 01

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

Mode 2 Input or Output


Eleven bit (start plus 8- serial data plus RB8 or TB8 bit plus stop total 11 bits) UART mode serial input and output Input or output whether SBUF used for read or write in instruction Fixed baud rate of (f/32) 12 or (f/64) 12 Mbaud/s where f = crystal frequency depending upon PCON 7 bit SMOD = 1 or 0, respectively Mode 2 when SCON bits 7 and 6 are 10
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 9

Mode 3 Input or Output


11 bit (start plus 8- serial data plus RB8 or TB8 bit plus stop total 11 bits) UART mode serial input and output Input or output whether SBUF used for read or write in instruction Baud rate with programmable using T1 or T0 timers (T2 in 8052) Mode 3 when SCON bits 7 and 6 are 1,1
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

2008

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SI Full duplex signals Mode 1, 2 or 3


SBUF Serial TxD/CLK, RxD/Data pins transmit/receive data buffer At receiver input from a transmitter output TxD RxD Processor Processor TxD RxD UART
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 11

At transmitter output for a receiver input UART Processor TxD RxD

SI Half duplex signals Mode 0


TxD/CLK, RxD/Data Pins SBUF Serial transmit/receive data buffer From a transmitter Processor output at receiver input CLK Data Processor Processor CLK synchronous Data At transmitter output for a receiver Processor input Processor CLK Data

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

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8051 SI signals at Port P3.1 and P3.0


TxD/CLK, RxD/Data Pins Programmed as per mode selected and SBUF read or write instruction executed P3.1 P3.0 P3 SBUF Serial transmit/receive data buffer TxD/CLK RxD/Data

8051 SI Features
1. Mode 0 Half- duplex synchronous mode of operation 2. T8 and R8 for the inter-processor communication in 11bit format 3. Mode 1 or 2 or 3 Full- duplex asynchronous serial communication 4. Signals not programmable for RxD or TxD no DDR in Architecture, Programming 2008 8051 Chapter-2 L4: "Embedded Systems -McGraw-Hill Education and Design", Raj Kamal, Publs.:

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Summary

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

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We learnt
Serial Interface functions
Half duplex synchronous serial mode 0 or Full duplex asynchronous UART mode 1, 2 or 3 SBUF SCON

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

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End of Lesson 4 of Chapter 2

2008

Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education

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