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2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
Serial Interface SI
programmable for half duplex synchronous serial or full duplex asynchronous UART mode
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
SBUF
Single SFR address for transmit and received byte buffers when the serial output or input is sent. 0x99 the address of SI buffers. SFR holds the SI transmission 8-bits when it is written. MOV 0x99, A instruction writes A into transmission buffer from A register MOV R1, 0x99 instruction read R1s register from the receive buffer
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 4
SCON
SFR to control the SI interface. Three upper bits programs the modes as 0 or 1 or 2 or 3. Mode 0 is half duplex synchronous. Modes 1 or 2 or 3 are full duplex asynchronous modes. Bit SCON.4 enables or disables SI receiver functions.
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 5
SCON
Two bits SCON.3 and SCON.2 specify the 8th bit to be transmitted and 8th bit received when the mode is 2 or 3. A bit SCON.1 enables or disables SI transmitter interrupts (TI) on completion of transmission. Bit SCON.0 enables or disables SI receiver interrupts (RI) on completion of transmission.
2008 Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 6
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
2008
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2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
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8051 SI Features
1. Mode 0 Half- duplex synchronous mode of operation 2. T8 and R8 for the inter-processor communication in 11bit format 3. Mode 1 or 2 or 3 Full- duplex asynchronous serial communication 4. Signals not programmable for RxD or TxD no DDR in Architecture, Programming 2008 8051 Chapter-2 L4: "Embedded Systems -McGraw-Hill Education and Design", Raj Kamal, Publs.:
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Summary
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
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We learnt
Serial Interface functions
Half duplex synchronous serial mode 0 or Full duplex asynchronous UART mode 1, 2 or 3 SBUF SCON
2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
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2008
Chapter-2 L4: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education
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