VHDLCODEFORALU

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityaluis
Port(A:inSTD_LOGIC;B:inSTD_LOGIC;
sel:inSTD_LOGIC_VECTOR(2downto0);
fnl_out:outSTD_LOGIC;cout:outSTD_LOGIC);
endalu;
architectureBehavioralofaluis
componentha
port(A,B:inSTD_LOGIC;sum,cout:outSTD_LOGIC);
endcomponent;
componentha_sub
port(A,B:inSTD_LOGIC;pgt,gnt:outSTD_LOGIC);
endcomponent;
componentDEC
port(A:inSTD_LOGIC;BD:outSTD_LOGIC_VECTOR(1downto0));
endcomponent;
componentINC
port(A:inSTD_LOGIC;CS:outSTD_LOGIC_VECTOR(1downto0));
endcomponent;
componentOR_2
port(A,B:inSTD_LOGIC;Z:outSTD_LOGIC);
endcomponent;
componentAND_2
port(A,B:inSTD_LOGIC;Z:outSTD_LOGIC);
endcomponent;
componentXOR_2
port(A,B:inSTD_LOGIC;Z:outSTD_LOGIC);
endcomponent;
componentNOR_2
port(A,B:inSTD_LOGIC;Z:outSTD_LOGIC);
endcomponent;
componentMUX
port(I:inSTD_LOGIC_VECTOR(1to8);
sel:inSTD_LOGIC_VECTOR(2downto0);
fnl_out:outSTD_LOGIC);
endcomponent;
componentOR_4
port(A,B,C,D:inSTD_LOGIC;Z:outSTD_LOGIC);
endcomponent;
signalI:std_logic_vector(1to8);
signalC:std_logic_vector(1to4);

begin
UUT1:haportmap(A,B,I(1),C(1));
UUT2:ha_subportmap(A,B,I(2),C(2));
UUT3:INCportmap(A,CS(1)=>I(3),CS(0)=>C(3));
UUT4:DECportmap(A,BD(1)=>I(4),BD(0)=>C(4));
UUT5:OR_2portmap(A,B,I(5));
UUT6:AND_2portmap(A,B,I(6));
UUT7:XOR_2portmap(A,B,I(7));
UUT8:NOR_2portmap(A,B,I(8));
UUT9:MUXportmap(I,sel,fnl_out);
cout<=C(1)whensel<="000"else
C(2)whensel<="001"else
C(3)whensel<="010"else
C(4)whensel<="011"else'Z';
endBehavioral;
Halfadder:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityhais
Port(A:inSTD_LOGIC;B:inSTD_LOGIC;
sum:outSTD_LOGIC;cout:outSTD_LOGIC);
endha;
architectureBehavioralofhais
begin
sum<=AXORB;
cout<=AANDB;
endBehavioral;
Subtracter:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityha_subis
Port(A:inSTD_LOGIC;B:inSTD_LOGIC;
pgt:outSTD_LOGIC;gnt:outSTD_LOGIC);
endha_sub;
architectureBehavioralofha_subis
begin
pgt<=AXORB;
gnt<=AAND(notB);

endBehavioral;
Incrementer:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityincis
Port(A:inSTD_LOGIC;CS:outSTD_LOGIC_VECTOR(1downto0));
endinc;
architectureBehavioralofincis
signalcnt:std_logic_vector(1downto0):="00";
begin
process(A)begin
ifA'eventandA='1'then
cnt<=cnt+1;
else
cnt<=cnt;
endif;
CS<=cnt;
endprocess;
endBehavioral;
Multiplexer:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitymuxis
Port(I:inSTD_LOGIC_VECTOR(1to8);
sel:inSTD_LOGIC_VECTOR(2downto0);
fnl_out:outSTD_LOGIC);
endmux;
architectureBehavioralofmuxis
begin
fnl_out<=I(1)whensel="000"else
I(2)whensel="001"else
I(3)whensel="010"else
I(4)whensel="011"else
I(5)whensel="100"else
I(6)whensel="101"else
I(7)whensel="110"else
I(8)whensel="111"else'Z';
endBehavioral;

Decrementer:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydecis
Port(A:inSTD_LOGIC;
BD:outSTD_LOGIC_VECTOR(1downto0));
enddec;
architectureBehavioralofdecis
signalcnt:std_logic_vector(1downto0):="00";
begin
process(A)begin
ifA'eventandA='1'then
cnt<=cnt1;
else
cnt<=cnt;
endif;
BD<=cnt;
endprocess;
endBehavioral;
2InputNOR:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityNOR_2is
Port(A:inSTD_LOGIC;B:inSTD_LOGIC;
Z:outSTD_LOGIC);
endNOR_2;
architectureBehavioralofNOR_2is
begin
Z<=not(AORB);
endBehavioral;
2InputOR:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityOR_2is
Port(A:inSTD_LOGIC;B:inSTD_LOGIC;
Z:outSTD_LOGIC);
endOR_2;
architectureBehavioralofOR_2is

begin
Z<=AORB;
endBehavioral;
4InputOR:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityOR_4is
Port(A:inSTD_LOGIC;
B,C,D:inSTD_LOGIC;
Z:outSTD_LOGIC);
endOR_4;
architectureBehavioralofOR_4is
begin
Z<=AORBORCORD;
endBehavioral;
2InputXOR:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityXOR_2is
Port(A:inSTD_LOGIC;
B:inSTD_LOGIC;
Z:outSTD_LOGIC);
endXOR_2;
architectureBehavioralofXOR_2is
begin
Z<=AXORB;
endBehavioral;

ALUOUTPUT

VHDLCODEFOR2BITARRAYMULTIPLIER

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entityarray_multis
Port(a:inSTD_LOGIC_VECTOR(1downto0);
b:inSTD_LOGIC_VECTOR(1downto0);
c:outSTD_LOGIC_VECTOR(3downto0));
endarray_mult;
architectureBehavioralofarray_multis
componenthalfadder
Port(a:inSTD_LOGIC;
b:inSTD_LOGIC;
s:outSTD_LOGIC;
cy:outSTD_LOGIC);
endcomponent;
SIGNALt:std_logic_vector(3downto0);
begin
c(0)<=a(0)andb(0);
t(0)<=a(0)andb(1);
t(1)<=a(1)andb(0);
t(2)<=a(1)andb(1);
L1:halfadderportmap(t(0),t(1),c(1),t(3));
L2:halfadderportmap(t(2),t(3),c(2),c(3));
endBehavioral;

ARRAYMULTIPLIEROUTPUT

VHDLCODEFOR4BITEVENSEQUENCECOUNTER

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entityeven_counteris
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
opt:outSTD_LOGIC_VECTOR(3downto0));
endeven_counter;
architectureBehavioralofeven_counteris
componentD_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);
endcomponent;
signald1,d2,d3:std_logic_vector(3downto0):=(others=>'0');
begin
L0:D_ffportmap(clk,rst,d1(0),d2(0),d3(0));
L1:D_ffportmap(clk,rst,d1(1),d2(1),d3(1));
L2:D_ffportmap(clk,rst,d1(2),d2(2),d3(2));
L3:D_ffportmap(clk,rst,d1(3),d2(3),d3(3));
d1(0)<=(d2(0)and(d3(1)ord3(2)))or(d3(0)andd2(1)andd2(2));
d1(1)<=d2(1)xord2(2);
d1(2)<=d3(2);
d1(3)<='0';
opt<=(d1(0)&d1(1)&d1(2)&d1(3));
endBehavioral;

EVENSEQUENCECOUNTEROUTPUT

VHDLCODEFOR4BITJOHNSONCOUNTER
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entityjohnis
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
count:outSTD_LOGIC_vector(3downto0));
endjohn;
architectureBehavioralofjohnis
signaldvr:std_logic_vector(7downto0);
componentD_ff
port(clk,rst,Din:instd_logic;
q,qbar:outstd_logic);
endcomponent;
begin
U1:D_ffportmap(clk,rst,dvr(7),dvr(0),dvr(1));
U2:D_ffportmap(clk,rst,dvr(0),dvr(2),dvr(3));
U3:D_ffportmap(clk,rst,dvr(2),dvr(4),dvr(5));
U4:D_ffportmap(clk,rst,dvr(4),dvr(6),dvr(7));
count<=(dvr(0)&dvr(2)&dvr(4)&dvr(6));
endBehavioral;

VHDLCODEFOR4BITRINGCOUNTER
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityringis
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
count:outSTD_LOGIC_vector(3downto0));
endring;
architectureBehavioralofringis
signaldvr:std_logic_vector(7downto0);
componentD_ff
port(clk,rst,Din:instd_logic;
q,qbar:outstd_logic);
endcomponent;
componentD_ff_w
port(clk,rst,Dinput:instd_logic;
qout,qbar:outstd_logic);
endcomponent;

begin
U1:D_ff_wportmap(clk,rst,dvr(6),dvr(0),dvr(1));
U2:D_ffportmap(clk,rst,dvr(0),dvr(2),dvr(3));
U3:D_ffportmap(clk,rst,dvr(2),dvr(4),dvr(5));
U4:D_ffportmap(clk,rst,dvr(4),dvr(6),dvr(7));
count<=(dvr(0)&dvr(2)&dvr(4)&dvr(6));
endBehavioral;
D_wflipflop:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityD_ff_wis
port(clk,rst,Dinput:instd_logic;
qout,qbar:outstd_logic);
endD_ff_w;
architectureBehavioralofD_ff_wis
begin
process(clk,rst)begin
ifrst='1'then
qout<='1';qbar<='0';
elsifclk'eventandclk='1'then
qout<=Dinput;
qbar<=not(Dinput);
endif;
endprocess;
endBehavioral;

JOHNSONCOUNTEROUTPUT

RINGCOUNTEROUTPUT

VHDLCODEFOR4BITODDSEQUENCECOUNTER

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityodd_counteris
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
opt:outSTD_LOGIC_VECTOR(3downto0));
endodd_counter;
architectureBehavioralofodd_counteris
componentD_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);
endcomponent;
signald1,d2,d3:std_logic_vector(3downto0):=(others=>'0');
begin
L0:D_ffportmap(clk,rst,d1(0),d2(0),d3(0));
L1:D_ffportmap(clk,rst,d1(1),d2(1),d3(1));
L2:D_ffportmap(clk,rst,d1(2),d2(2),d3(2));
L3:D_ffportmap(clk,rst,d1(3),d2(3),d3(3));
d1(0)<=(d2(0)and(d3(1)ord3(2)))or(d3(0)andd2(1)andd2(2));
d1(1)<=d2(1)xord2(2);
d1(2)<=d3(2);
d1(3)<='1';
opt<=(d1(0)&d1(1)&d1(2)&d1(3));
endBehavioral;

ODDSEQUENCECOUNTEROUTPUT

VHDLCODEFOR4BITPISOSHIFTREGISTER
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entitypisois
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
ctl:instd_logic;
pi:inSTD_LOGIC_VECTOR(3downto0);
so:outSTD_LOGIC);
endpiso;
architectureBehavioralofpisois
componentD_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);
endcomponent;
signald1,d2,d3:std_logic_vector(3downto0):=(others=>'0');
begin
L1:D_ffportmap(clk,rst,d1(0),d2(0),d3(0));
L2:D_ffportmap(clk,rst,d1(1),d2(1),d3(1));
L3:D_ffportmap(clk,rst,d1(2),d2(2),d3(2));
L4:D_ffportmap(clk,rst,d1(3),d2(3),d3(3));
d1(0)<=pi(0);
d1(1)<=(pi(1)and(notctl))or(d2(0)andctl);
d1(2)<=(pi(2)and(notctl))or(d2(1)andctl);
d1(3)<=(pi(3)and(notctl))or(d2(2)andctl);
so<=d2(3)whenctl='1'else'0';
endBehavioral;

VHDLCODEFOR4BITPIPOSHIFTREGISTER:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitypipois
Port(clk,rst:inSTD_LOGIC;
pi:inSTD_LOGIC_vector(3downto0);
po:outSTD_LOGIC_vector(3downto0));
endpipo;

architectureBehavioralofpipois
componentD_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);
endcomponent;
signald1:std_logic_vector(3downto0):=(others=>'0');
begin
L1:D_ffportmap(clk,rst,pi(0),po(0),d1(0));
L2:D_ffportmap(clk,rst,pi(1),po(1),d1(1));
L3:D_ffportmap(clk,rst,pi(2),po(2),d1(2));
L4:D_ffportmap(clk,rst,pi(3),po(3),d1(3));
endBehavioral;
DFlipflop:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityD_ffis
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);
endD_ff;
architectureBehavioralofD_ffis
begin
process(clk,rst)
begin
ifrst='1'then
q<='0';
qbar<='0';
elsifclk'eventandclk='1'then
q<=din;
qbar<=notdin;
endif;
endprocess;
endBehavioral;

PISOSHIFTREGISTEROUTPUT

PIPOSHIFTREGISTEROUTPUT

VHDLCODEFOR4BITRIPPLECARRYADDER

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityripple_adderis
Port(a:inSTD_LOGIC_vector(3downto0);
b:inSTD_LOGIC_vector(3downto0);
y:outSTD_LOGIC_vector(3downto0);
cout:outSTD_LOGIC);
endripple_adder;
architectureBehavioralofripple_adderis
componentfulladderis
port(a,b,cin:instd_logic;
s,cy:outstd_logic);
endcomponent;
signalt:std_logic_vector(4downto0):=(others=>'0');
begin
L1:foriin1to4generate
F1:fulladderportmap(a(i1),b(i1),t(i1),y(i1),t(i));
endgenerate;
cout<=t(4);

endBehavioral;

RIPPLECARRYADDEROUTPUT

VHDLCODEFOR4BITSISOSHIFTREGISTER
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

entitysisois
Port(clk,rst:inSTD_LOGIC;
si:inSTD_LOGIC;
so:outSTD_LOGIC);
endsiso;
architectureBehavioralofsisois
componentD_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);
endcomponent;
signald1,d:std_logic_vector(3downto0):=(others=>'0');
begin
L1:D_ffportmap(clk,rst,si,d(0),d1(0));
L2:D_ffportmap(clk,rst,d(0),d(1),d1(1));
L3:D_ffportmap(clk,rst,d(1),d(2),d1(2));
L4:D_ffportmap(clk,rst,d(2),so,d1(3));
endBehavioral;

VHDLCODEFOR4BITSIPOSHIFTREGISTER
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entitysipois
Port(clk,rst:inSTD_LOGIC;
si:inSTD_LOGIC;
so:outSTD_LOGIC_vector(3downto0));
endsipo;
architectureBehavioralofsipois
componentD_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
din:inSTD_LOGIC;
q:outSTD_LOGIC;
qbar:outSTD_LOGIC);

endcomponent;
signald1,d:std_logic_vector(3downto0):=(others=>'0');
begin
L1:D_ffportmap(clk,rst,si,d(0),d1(0));
L2:D_ffportmap(clk,rst,d(0),d(1),d1(1));
L3:D_ffportmap(clk,rst,d(1),d(2),d1(2));
L4:D_ffportmap(clk,rst,d(2),d(3),d1(3));
so<=(d(0)&d(1)&d(2)&d(3));
endBehavioral;

SISOSHIFTREGISTEROUTPUT

SIPOSHIFTREGISTEROUTPUT

VHDLCODEFOR4BITUP/DOWNSEQUENCECOUNTER

libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entityup_down_counteris
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
ctl:inSTD_LOGIC;
opt:outSTD_LOGIC_VECTOR(3downto0));
endup_down_counter;

architectureBehavioralofup_down_counteris
componentJK_ff
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
j:inSTD_LOGIC;
k:inSTD_LOGIC;
q:outSTD_LOGIC);
endcomponent;
signald1:std_logic_vector(3downto0):=(others=>'0');
signald3:std_logic_vector(3downto0):=(others=>'0');
signals1,s2,s3,s4,s5,s6:std_logic;
begin

L1:JK_ffportmap(clk,rst,d1(0),d1(0),d3(0));
L2:JK_ffportmap(clk,rst,d1(1),d1(1),d3(1));
L3:JK_ffportmap(clk,rst,d1(2),d1(2),d3(2));
L4:JK_ffportmap(clk,rst,d1(3),d1(3),d3(3));
d1(0)<='1';
d1(1)<=s1ors2;
d1(2)<=s3ors4;
d1(3)<=s5ors6;
s1<=(d3(0)andctl);
s2<=(not(d3(0))and(notctl));
s3<=s1andd3(1);
s4<=s2and(not(d3(1)));
s5<=s3andd3(2);
s6<=s4and(notd3(2));
opt<=(d3(3)&d3(2)&d3(1)&d3(0));
endBehavioral;
JKflipflop:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityJK_ffis
Port(clk:inSTD_LOGIC;
rst:inSTD_LOGIC;
j:inSTD_LOGIC;
k:inSTD_LOGIC;
q:outSTD_LOGIC);
endJK_ff;
architectureBehavioralofJK_ffis
begin
process(clk,rst)
variableprs:std_logic;
begin
ifrst='1'then
prs:='0';q<='0';
elsifclk='1'andclk'eventthen
ifj='0'andk='0'then
q<=prs;
prs:=prs;
elsifj='0'andk='1'then
q<='0';
prs:='0';
elsifj='1'andk='0'then
q<='1';
prs:='1';
else
q<=notprs;
prs:=notprs;
endif;
endif;
endprocess;
endBehavioral;

UP/DOWNSEQUENCECOUNTEROUTPUT