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light generator.
2) Write down a VHDL Program, testbench; simulate and download it on FPGA/CPLD kit Ior a
RAM.
3) Write down a VHDL Program, testbench; simulate and download it on FPGACPLD Kit Ior
generating ramp waveIorm at the output oI DAC.
4) Write down a VHDL Program, testbench; simulate and download it on FPGACPLD Kit Ior time
period measurement oI any signal.
5) Design a layout and simulate it Ior a invertor oI 1GHz Irequency and 0.1 PF output capacitance.
6) Design a layout and simulate it Ior
a) 2 i/p NAND Gate
b) 2 i/p NOR Gate
7) Design a layout and simulate it Ior YABCD
) Design a 2:1 multiplexer using conventional method.
9) Design a 2:1 multiplexer using transmission Gates.
10)Design a layout and simulate it Ior YABCD
11)Design a layout and simulate it Ior Y ABCD.