1. Full substractur using structural modelling library ieee; use ieee.std_logic_1164.

all; entity not1 is port(x:in bit;y:out bit); end not1; architecture df of not1 is begin y<=not x; end df; Library ieee; use ieee.std_logic_1164.all; entity xor2 is port(a,b:in bit;y:out bit); end xor2; architecture xor2 of xor2 is begin y<=a xor b ; end xor2; Library ieee; use ieee.std_logic_1164.all; entity or2 is port(a,b:in bit;y:out bit); end or2; architecture or2 of or2 is begin y<=a or b; end or2; Library ieee; use ieee.std_logic_1164.all; entity and2 is port(a,b:in bit;y:out bit); end and2; architecture and2 of and2 is begin y <= a and b; end and2; MAIN PROGRAM Library ieee; use ieee.std_logic_1164.all; entity fulsub is port(A,B,C:in bit;D,Bo:out bit); end fulsub;

architecture struct of fulsub is component and2 is port(a,b:in bit;y:out bit); end component; component xor2 is port(a,b:in bit;y:out bit); end component; component or2 is port(a,b:in bit;c:out bit); end component; component not1 is port(a:in bit;y:out bit); end component; signal S0,S1,S2,S3,S4,S5:bit; Begin X1:xor1 port map(A,B,S1); X2:xor1 port map(S1,C,D); X3:not1 port map(A,S0); X4:and1 port map(S0,B,S2); X5:and1 port map(S0,C,S3); X6:or1 port map(S2,S3,S5); X7:and1 port map(B,C,S4); X8:or1 port map(S5,S4,Bo); end struct; 2. Code for 4 bit magnitude compartor (Behaviriol style)
LIBRARY IEEE;//standard library USE IEEE.STD_LOGIC_1164.ALL;//importing the library. //entity declaration. ENTITY comp4b IS PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0); F1,F2,F3:OUT BIT);//inputs and outputs. END ENTITY; //end of entity declaration. ARCHITECTURE behav OF comp4b IS BEGIN PROCESS(A,B)//sensitivity list. BEGIN IF(A(3)='0' AND B(3)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(3)='1' AND B(3)='0')THEN F1<='1';F2<='0';F3<='0';

ELSE IF(A(2)='0' AND B(2)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(2)='1' AND B(2)='0')THEN F1<='1';F2<='0';F3<='0';

ELSE IF(A(1)='0' AND B(1)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(1)='1' AND B(1)='0')THEN F1<='1';F2<='0';F3<='0'; ELSE IF(A(0)='0' AND B(0)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(0)='1' AND B(0)='0')THEN F1<='1';F2<='0';F3<='0'; ELSE F2<='1';F1<='0';F3<='0'; END IF; END IF; END IF; END IF; END PROCESS; END behav;//end of architecture.
3. Code for 16:1 Mux using 4:1 LIBRARY IEEE;//standard library. USE IEEE.STD_LOGIC_1164.ALL;//importing standard library. USE IEEE.STD_LOGIC_ARITH.ALL; //entity declaration ENTITY 4mux1 IS PORT(A,B,C,D:IN STD_LOGIC; S0,S1: IN STD_LOGIC; Q:OUT STD_LOGIC); END 4mux1; //end of entity declaration ARCHITECTURE behave OF 4mux1 IS BEGINPROCESS(A,B,C,D,S0,S1)//sensitivity list. BEGINIF S0='0' AND S1='0' THEN Q<='A'; ELSIF SO='1' AND S1='0' THEN Q<='B'; ELSIF SO='0' AND S1='1' THEN Q<='C'; ELSE Q<='D'; END IF; END PROCESS; END behave;//end of architecture

M a i n pr ogr a m LI BRARY I EEE; USE IEEE. STD_LOGI C_1164. A LL; USE IEEE. STD_LOGI C_ ARI TH. A LL; / / St a n da r d li br a r y p a c k a g e s ENTI TY M UX161s I S PORT( A: I N STD_LOGI C_VE CTO R( 1 5 DOW NT O 0) ; S: I N STD_LOGI C_ VECT OR( 3 DOW NTO 0 ); Z: OUT STD_LOGI C) ; / /i nput a n d o ut p u t d e c la r a ti o n END M UX161s ; ARCHI TE CTU RE st r uc OF M UX1 6 1 s I S SI GNAL Z1, Z2, Z3, Z4: STD_LOGI C; COM PON ENT m ux41b I S// Ba s i c c o m p o ne n t PORT( A, B, C, D, S0, S1: I N STD_ LOGI C; Q: OUT STD_LOGI C) ; END COM PONEN T; BEGIN M 1:m ux41b M 2:m ux41b M 3:m ux41b M 4:m ux41b M 5:m ux41b END st r uc PORT PORT PORT PORT PORT M AP( A( 0) , A( 1) , A( 2 ), A( 3 ), S( 0 ), S( 1 ), Z1 ) ; M AP( A( 4) , A( 5) , A( 6 ), A( 7 ), S( 0 ), S( 1 ), Z2 ) ; M AP( A( 8) , A( 9) , A( 1 0 ), A( 1 1 ), S( 0 ), S( 1 ), Z3 ) ; M AP( A( 12) , A( 1 3) , A( 1 4 ), A( 1 5 ), S( 0 ), S( 1 ), Z4 ) ; M AP( Z1, Z2 , Z3, Z4 , S( 2 ), S( 3 ), Z) ;/ /m a p p i n g

Gray code to binary conversion structutral Library ieee; use ieee.std_logic_1164.all; entity xor2 is port(a,b:in bit;y:out bit); end xor2; architecture xor2 of xor2 is begin y<=a xor b ; end xor2;

MAIN program library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity g_to_bi is port(b:in std_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end g_to bi; architecture struct_g_B of g_to_bi is component xor2 is port(a,b:in bit;y:out bit); end component; begin g(3)<=b(3); Ga : portmap xor2 (b(3),b(2),g(2)); Ga : portmap xor2 (b(2),b(1),g(1)); Ga : portmap xor2 (b(1),b(0),g(0)); End struct_g_B;