HDL Lab Manual APSCE

INTERFACING PROGRAMS HEX KEY PAD library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TKHKY1 is Port ( pkeyret : in std_logic_vector(3 downto 0); pkeyscn : out std_logic_vector(3 downto 0); pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pledind : out std_logic_vector (7 downto 0); pclk100K : in std_logic ); end TKHKY1; architecture behavioral of TKHKY1 is signal skeyval : integer range 0 to 15; signal skeyhit : std_logic; signal skeyscn : std_logic_vector(3 downto 0); signal sclkdiv : std_logic_vector(7 downto 0); signal skeyclk : std_logic; begin -- process keypress process(pkeyret) begin case pkeyret is when "1110" => skeyhit <= '1'; when "1101" => skeyhit <= '1'; when "1011" => skeyhit <= '1'; when "0111" => skeyhit <= '1'; when others => skeyhit <= '0'; end case; end process; -- process keyval process(skeyhit) begin if( rising_edge(skeyhit)) then if(skeyscn = "1110" and pkeyret = "1110")

HDL Lab Manual APSCE

then skeyval <= 0; elsif(skeyscn = "1110" and pkeyret = "1101") then skeyval <= 1; elsif(skeyscn = "1110" and pkeyret = "1011") then skeyval <= 2; elsif(skeyscn = "1110" and pkeyret = "0111") then skeyval <= 3; elsif(skeyscn = "1101" and pkeyret = "1110") then skeyval <= 4; elsif(skeyscn = "1101" and pkeyret = "1101") then skeyval <= 5; elsif(skeyscn = "1101" and pkeyret = "1011") then skeyval <= 6; elsif(skeyscn = "1101" and pkeyret = "0111") then skeyval <= 7; elsif(skeyscn = "1011" and pkeyret = "1110") then skeyval <= 8; elsif(skeyscn = "1011" and pkeyret = "1101") then skeyval <= 9; elsif(skeyscn = "1011" and pkeyret = "1011") then skeyval <= 10; elsif(skeyscn = "1011" and pkeyret = "0111") then skeyval <= 11; elsif(skeyscn = "0111" and pkeyret = "1110") then skeyval <= 12; elsif(skeyscn = "0111" and pkeyret = "1101") then skeyval <= 13; elsif(skeyscn = "0111" and pkeyret = "1011") then skeyval <= 14; elsif(skeyscn = "0111" and pkeyret = "0111") then skeyval <= 15; end if; end if; end process; -- process clk divider -process(pclk100k) begin if( rising_edge(pclk100k)) then sclkdiv <= sclkdiv+1; end if; skeyclk <= sclkdiv(6); end process;

HDL Lab Manual APSCE

-- process for key scan clkscan process(skeyclk) begin if(rising_edge(skeyclk)) then if skeyscn = "1110" then skeyscn <= "1101"; elsif skeyscn = "1101" then skeyscn <= "1011"; elsif skeyscn = "1011" then skeyscn <= "0111"; elsif skeyscn = "0111" then skeyscn <= "1110"; else skeyscn <= "1110"; end if; end if; pkeyscn <= skeyscn; end process; -- process display 7seg process(skeyval) type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0); constant segval : tseg7 := ("0111111","0000110","1011011","1001111","1100110","1101101","1111101", "0000111","1111111","1101111","1110111","1111100","1011000","1011110", "1111001","1110001"); begin pdspseg <= segval(skeyval); pdspmux <= "1110"; end process; -- process display ledind process(skeyval) type tled8 is array(0 to 15) of std_logic_vector (7 downto 0); constant led8val : tled8 := ("00000000","00000001","00000010","00000100", "00001000","00010000","00100000","01000000", "10000000","00001001","00001010","00001011", "00001100","00001101","00001110","00001111"); begin pledind <= led8val(skeyval); end process; end behavioral; ELEVATOR library IEEE; use IEEE.STD_LOGIC_1164.ALL;

HDL Lab Manual APSCE

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TKBELE1 is Port ( pkeyret : in std_logic_vector(3 downto 0); pkeyscn : out std_logic_vector(3 downto 0); pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pclk100K : in std_logic ); end TKBELE1; architecture behavioral of TKBELE1 is signal scurflr,snxtflr,skeyflr : integer range 0 to 15; signal sdir, skeyhit : std_logic; signal skeyscn : std_logic_vector(3 downto 0); signal lkeyscn : std_logic_vector(3 downto 0); signal lkeyret : std_logic_vector(3 downto 0); signal sclkdiv : std_logic_vector(15 downto 0); signal sflrclk,skeyclk : std_logic; begin -- process keypress process(pkeyret) begin case pkeyret is when "1110" => skeyhit <= '1'; when "1101" => skeyhit <= '1'; when "1011" => skeyhit <= '1'; when "0111" => skeyhit <= '1'; when others => skeyhit <= '0'; end case; end process; process(skeyhit) begin if( rising_edge(skeyhit)) then lkeyscn <= skeyscn; lkeyret <= pkeyret; end if; end process; -- process keyval process(skeyhit)

HDL Lab Manual APSCE

begin if( rising_edge(skeyhit)) then if(lkeyscn = "1110" and lkeyret = "1110") then skeyflr <= 0; elsif(lkeyscn = "1110" and lkeyret = "1101") then skeyflr <= 1; elsif(lkeyscn = "1110" and lkeyret = "1011") then skeyflr <= 2; elsif(lkeyscn = "1110" and lkeyret = "0111") then skeyflr <= 3; elsif(lkeyscn = "1101" and lkeyret = "1110") then skeyflr <= 4; elsif(lkeyscn = "1101" and lkeyret = "1101") then skeyflr <= 5; elsif(lkeyscn = "1101" and lkeyret = "1011") then skeyflr <= 6; elsif(lkeyscn = "1101" and lkeyret = "0111") then skeyflr <= 7; elsif(lkeyscn = "1011" and lkeyret = "1110") then skeyflr <= 8; elsif(lkeyscn = "1011" and lkeyret = "1101") then skeyflr <= 9; elsif(lkeyscn = "1011" and lkeyret = "1011") then skeyflr <= 10; elsif(lkeyscn = "1011" and lkeyret = "0111") then skeyflr <= 11; elsif(lkeyscn = "0111" and lkeyret = "1110") then skeyflr <= 12; elsif(lkeyscn = "0111" and lkeyret = "1101") then skeyflr <= 13; elsif(lkeyscn = "0111" and lkeyret = "1011") then skeyflr <= 14; elsif(lkeyscn = "0111" and lkeyret = "0111") then skeyflr <= 15; end if; end if; end process; -- process clk divider -process(pclk100k) begin if( rising_edge(pclk100k)) then sclkdiv <= sclkdiv+1; end if;

HDL Lab Manual APSCE

skeyclk <= sclkdiv(6); sflrclk <= sclkdiv(15); end process; -- process for key scan clkscan process(skeyclk) begin if(rising_edge(skeyclk)) then if skeyscn = "1110" then skeyscn <= "1101"; elsif skeyscn = "1101" then skeyscn <= "1011"; elsif skeyscn = "1011" then skeyscn <= "0111"; elsif skeyscn = "0111" then skeyscn <= "1110"; else skeyscn <= "1110"; end if; end if; pkeyscn <= skeyscn; end process; -- process floor motion process(sflrclk) begin if(rising_edge(sflrclk)) then if(not (skeyflr = scurflr) ) then if(skeyflr > scurflr) then scurflr <= scurflr+1; else scurflr <= scurflr-1; end if; end if; end if; end process; -- process display 7seg process(scurflr) type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0); constant segval : tseg7 := ("0111111","0000110","1011011","1001111","1100110","1101101","1111101", "0000111","1111111","1101111","1110111","1111100","1011000","1011110", "1111001","1110001"); begin pdspseg <= segval(scurflr); pdspmux <= "1110"; end process; end behavioral;

HDL Lab Manual APSCE

MOVING DISPLAY library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TKBMDSP is Port ( pdspseg : out std_logic_vector (6 downto 0); pdspmux : out std_logic_vector (3 downto 0); pclk100K : in std_logic ); end TKBMDSP; architecture behavioral of TKBMDSP is signal sclkdiv : std_logic_vector(15 downto 0); signal sdspnum : integer range 0 to 15; signal sblkdly : integer range 0 to 2; signal sdspseq : std_logic_vector(2 downto 0); signal sdspmux : std_logic_vector(3 downto 0); signal smuxclk,sdspstp : std_logic; begin -- process clk divider -process(pclk100k) begin if( rising_edge(pclk100k)) then sclkdiv <= sclkdiv+1; end if; smuxclk <= sclkdiv(0); sdspseq(0) <= sclkdiv(1); sdspseq(1) <= sclkdiv(2); sdspseq(2) <= sclkdiv(3); sdspstp <= sclkdiv(15); end process; -- process dspno process(sdspstp) begin if(rising_edge(sdspstp)) then if(sdspnum = 4 or sdspnum = 8 ) then sblkdly <= sblkdly+1; if(sblkdly = 2) then sdspnum <= sdspnum+1; end if;

HDL Lab Manual APSCE

else sdspnum <= sdspnum+1; sblkdly <= 0; end if; end if; end process; -- process pdspmux process(sdspseq) begin if(sdspseq = "000") then sdspmux <= "1110"; elsif(sdspseq = "010") then sdspmux <= "1101"; elsif(sdspseq = "100") then sdspmux <= "1011"; elsif(sdspseq = "110") then sdspmux <= "0111"; else sdspmux <= "1111"; end if; pdspmux <= sdspmux; end process; -- process muxdisp process(sdspmux) type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0); constant segval : tseg7 := ("0000000","0000000","0000000","0000000", "1110001","1110011","1111101","1110111", "1011011","1101101","1011100","1011100", "0111001","1110011","0111000","1011110", "1101111","1101101","0000111","1011011", "0000000","0000000","0000000","0000000"); begin if(sdspmux = "1110") then pdspseg <= segval(sdspnum); elsif(sdspmux = "1101") then pdspseg <= segval(sdspnum+1); elsif(sdspmux = "1011") then pdspseg <= segval(sdspnum+2); elsif(sdspmux = "0111") then pdspseg <= segval(sdspnum+3); else pdspseg <= "0000000"; end if; end process;

---

end behavioral; DC MOTOR -- ALS NIFC37 DC motor -- connect J4-pin 26 to GND -- connect J4-pin 25 to +5V -- connect J4-pin 5 to CPLD pin 9 (pdcm)

HDL Lab Manual APSCE

-- connect tkbase clk 500khz to CPLD pin 20 -- CPLD Pin 1,2,3 as SW 0,1,2; -- sw0 sw1 sw2 -- 0 0 0 = 500rpm -- 1 0 0 = 800rpm -0 1 0 --- 1 1 1 = 2500rpm library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TKBDCM is Port ( psw : in std_logic_vector(2 downto 0); pdcm : out std_logic; p100k : in std_logic ); end TKBDCM; architecture behavioral of TKBDCM is signal sclkdiv : std_logic_vector(11 downto 0); begin -- count upto 3000 process(p100k) begin if( rising_edge(p100k)) then sclkdiv <= sclkdiv+1; end if; if(sclkdiv = "101110111000") then sclkdiv <= "000000000000"; end if; end process; process(psw,sclkdiv) variable vdcm : bit; begin if(sclkdiv = "000000000000") then vdcm := '1';

HDL Lab Manual APSCE

end if; -- 1f4,320,44c,578,6a4,7d0,8fc,9c4 if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0'; elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0'; elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0'; elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0'; elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0'; elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0'; elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0'; elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0'; end if; if(vdcm = '1') then pdcm <= '1'; else pdcm <= '0'; end if; end process; end behavioral; LCD DISPLAY use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity lcd1 is library IEEE; Port ( plcddat : out std_logic_vector (7 downto 0); plcdrs,plcdrw,plcden : out std_logic; pclk100K : in std_logic ); end lcd1; architecture behavioral of lcd1 is signal sclkdiv : std_logic_vector(15 downto 0); signal sdspclk : std_logic; signal tchr1 : character; constant mystr : string := "HELP FIRE";

HDL Lab Manual APSCE

begin -- clkdivider process(pclk100k) begin if( rising_edge(pclk100k)) then sclkdiv <= sclkdiv+1; end if; sdspclk <= sclkdiv(15); plcden <= sclkdiv(15); end process; -- display process(sdspclk) variable vdspseq : integer range 0 to 15; variable vdspnum : integer range 0 to 15; variable i1 : integer; type tlcdtyp is array(0 to 15) of std_logic_vector (7 downto 0); constant tlcddat : tlcdtyp := ("00111000","00001110","00000010","00000001", "01000001","01000100","01001101","00100000", "01000001","01000100","01001101","00100000", "01000001","01000100","01001101","00100000" ); begin if(falling_edge(sdspclk) ) then vdspseq := vdspseq+1; end if; if(falling_edge(sdspclk) ) then if(vdspseq > 3) then vdspnum := vdspnum+1; end if; end if; if(vdspseq < 4) then plcddat <= tlcddat(vdspseq); vdspnum := 0; else -plcddat <= tlcddat(vdspseq);

HDL Lab Manual APSCE

tchr1 <= mystr(vdspnum); plcddat <= std_logic_vector(to_unsigned(character'pos(tchr1),8)); end if; plcdrw <= '0'; if(vdspseq < 4) then plcdrs <= '0'; else plcdrs <= '1'; end if; end process; end behavioral; DAC-SQUARE WAVE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity sqdac1 is Port ( din : out std_logic_vector(7 downto 0); clk : in std_logic); end sqdac1; architecture Behavioral of sqdac1 is signal count:std_logic_vector(4 downto 0):="00000"; begin process(clk) begin if clk'event and clk='1' then if count<"10000" then count<=count+'1'; din <="10000000"; elsif

HDL Lab Manual APSCE

count >="10000" then count<=count+'1'; din <="00000000"; end if; end if; end process; end Behavioral; DAC-TRIANGULAR WAVE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dac_tri is Port ( din : out std_logic_vector(7 downto 0); clk : in std_logic); end dac_tri ; architecture Behavioral of dac_tri is signal cnt:std_logic_vector(8 downto 0):="000000000"; signal cnt1:std_logic_vector(7 downto 0):="00000000"; begin process(clk) begin if clk'event and clk='1' then if cnt<"100000000" then cnt<=cnt+'1'; cnt1<=cnt1+'1'; din <=cnt1; elsif cnt<"111111111" then cnt<=cnt+'1'; cnt1<=cnt1-'1'; din <=cnt1; elsif cnt="111111111" then cnt<="000000000"; cnt1<="00000000"; din <=cnt1;

HDL Lab Manual APSCE

end if; end if; end process; -- din <=count; end Behavioral; DAC-SAWTOOTH library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dac_saw is Port ( din : out std_logic_vector(7 downto 0); clk : in std_logic); end dac_saw ; architecture Behavioral of dac_saw is signal cnt:std_logic_vector(7 downto 0):="00000000"; -- signal cnt1:std_logic_vector(7 downto 0):="00000000"; begin process(clk) begin if clk'event and clk='1' then if cnt<"11111111" then cnt<=cnt+'1'; din <=cnt; elsif cnt="11111111" then cnt<="00000000"; din <=cnt; end if; end if; end process; -- din <=count; end Behavioral; RELAY library IEEE; use IEEE.STD_LOGIC_1164.ALL;

HDL Lab Manual APSCE

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity relay is Port ( a : in std_logic; c : out std_logic); end relay; architecture Behavioral of relay is begin process(a) begin if a = '1' then c <= a; else c <= '0'; end if; end process; end Behavioral; STEPPER MOTOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TKBSTP is Port ( pkeycol : in std_logic_vector (3 downto 0); pkeyrow : out std_logic_vector (3 downto 0); pstpsig : out std_logic_vector(3 downto 0); pclk100K : in std_logic ); end TKBSTP; architecture behavioral of TKBSTP is signal sclkdiv : std_logic_vector(20 downto 0);

HDL Lab Manual APSCE

signal sstpcnt : std_logic_vector(1 downto 0); signal sstpclk,skeyhit : std_logic; signal skeysts :std_logic_vector (3 downto 0); begin -- clkdivider process(pclk100k) begin if( rising_edge(pclk100k)) then sclkdiv <= sclkdiv+1; end if; sstpclk <= sclkdiv(10); end process; -- key process -- out key row = 0 check key col pkeyrow <= "0000"; process(pkeycol) begin if(pkeycol(0) = '0' or pkeycol(1) = '0' or pkeycol(2) = '0' or pkeycol(3) = '0' ) then skeyhit <= '0'; else skeyhit <= '1'; end if; end process; -- latch key press process(skeyhit) begin if( falling_edge(skeyhit)) then skeysts <= pkeycol; end if; end process; -- 4 step counter process(sstpclk) begin if(rising_edge(sstpclk)) then if(skeysts(0) = '0') then sstpcnt <= sstpcnt+1; elsif(skeysts(1) = '0') then sstpcnt <= sstpcnt-1;

HDL Lab Manual APSCE

end if; end if; end process; -- outputs signal pstpsig = D, C, B & A for stepper motor -- TKBase from ucf file = 14,13,12, 11 -- als stepper controller = 4, 6, 3 & 5 process(sstpcnt) begin if (sstpcnt = "00") then pstpsig <= "0001"; elsif(sstpcnt = "01") then pstpsig <= "0111"; elsif(sstpcnt = "10") then pstpsig <= "1110"; elsif(sstpcnt = "11") then pstpsig <= "1000"; end if; end process; end behavioral; Sine Wave: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY dacsine IS PORT (clk: IN std_logic; douta : OUT std_logic_vector(7 downto 0); doutb : OUT std_logic_vector(7 downto 0)); END dacsine; ARCHITECTURE Behavioral OF dacsine IS --signal S:std_logic_vector(22 downto 0); --signal user_clk:std_logic; signal count:integer range 0 to 48:=0; type lute is array (0 to 48) of std_logic_vector(7 downto 0); signal table:lute:=("10000000","10010000","10100001","10110001","11000000", "11001101",11011010","11100101","11101110","11110110","11111011", "11111110","11111111","11111110","11111011","11110110","11101110", "11100101","11011010","11001101","11000000", "10110001", "10100001", "10010000","10000000","01110000","01011111","01001111","01000000", "00110011","00100110","00011011","00010010","00001010","00000101", "00000010","00000000","00000010","00000101","00001010","00010010",

HDL Lab Manual APSCE

"00011011","00100110","00110011","01000000","01001111","01011111", "01110000","10000000"); BEGIN process (clk) begin if clk'event and clk ='1' then count <= count +1; IF count = 48 THEN count <= 0; END IF; END IF; END PROCESS ; --process (count) --begin douta <= table(count); doutb <= table(count); --end process; END Behavioral;