Jtag Intro

Intro to IEEE 1149.
1 Boundary-Scan (JTAG)
David Lavo lavo@soe.ucsc.edu UC Santa Cruz January 27, 2005
Outline
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
David Lavo
Intro To Boundary-Scan
IEEE 1149.1 Boundary-Scan

Facilitates board testing Provides an on-chip means of controlling and testing pads Boundary-scan components can also be used for other test purposes:
Logic and RAM BIST control Scan chain control Scan wrapper config., test modes, etc.
David Lavo Intro To Boundary-Scan
3
Board Test
David Lavo
Pad & Parametric Test

1149.1 can be used to control and exercise pads independent of the chip core Leakage on tri-state outputs Measure voltage and current for output pads driving 0 or 1 Test logic levels captured by input pads at various voltages
5
Outline
David Lavo
1149.1 Hardware
Test Access Port: 5 pins TAP Controller
Finite State Machine Internal registers (Bypass, Instruction, etc.) Test control logic
Boundary-Scan Register Chain Internal Data Registers (Optional)

7
Boundary-Scan Components
I
TMS TDI TCK TDO TRST_N TAP Controller
Chip Core
David Lavo
TAP Controller Components

SI SO
TDI
TMS TCK TRST_N TDO
Bypass Reg.
Instruction Register
Finite State Machine
Instruction Decode
Various TAP Outputs: UpdateDR, CaptureDR, TriState, Etc.
David Lavo
TAP Controller State Diagram

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
BYPASS Instruction
A mandatory instruction The default instruction for TAPs with no IDCODE register Short scan path: 1 bit between TDI and TDO Usually loaded in chips that are idle while other chips on the board are being tested
11
BYPASS Data Path

SI SO
TDI
TMS TCK TRST_N TDO
Bypass Reg.
Instruction Decode
David Lavo
12
EXTEST & SAMPLE/PRELOAD

EXTEST is the workhorse JTAG instruction
Sample (Capture) & Drive (Update) output signals Sample & optionally drive input signals
Data is first loaded into boundary register chain with SAMPLE/PRELOAD instruction
Samples inputs and outputs, pass-through Loads boundary register with data
David Lavo
13
SAMPLE/PRELOAD: Start
SAMPLE/ PRELOAD TMS TDI TCK TDO TRST_N TAP Controller BYPASS
Chip Core
David Lavo
14

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
Instruction Register Data Path

SI SO
TDI
TMS TCK TRST_N TDO
Bypass Reg.
Instruction Decode
David Lavo
16

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
SAMPLE/PRELOAD: UpdateIR
SAMPLE/ DATA PRELOAD
TMS TDI TC K TDO TRST_N

TAP Controller SMP/PRLD BYPASS
Chip Core
David Lavo
18

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
SAMPLE/PRELOAD: CaptureDR
Capture (sample) 0
DATA
Mode=0 0 TAP Controller SMP/PRLD 0

Chip Core
TMS TDI TC K TDO TRST_N

0 1 0 1
David Lavo
20

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
SAMPLE/PRELOAD: ShiftDR
0 1 DATA TMS TDI TCK TDO TRST_N 1 0 1 0
David Lavo
0 1
1 0
1 0
0 1 TAP Controller SMP/PRLD 1 0 1 0 0 1
Chip Core
0 1
0 1
1 0
22

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
SAMPLE/PRELOAD: UpdateDR
1 Mode=0 TMS TDI TCK TDO TRST_N 1 0 TAP Controller SMP/PRLD 1 1
Chip Core
David Lavo
24

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
EXTEST: UpdateIR
1 EXTEST TMS TDI TCK TDO TRST_N 1 0 TAP Controller EXTEST Mode=1 1 0 1 0
Chip Core
David Lavo
26

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
EXTEST: CaptureDR
Capture (sample) 1 DATA TMS TDI TCK TDO TRST_N TAP Controller EXTEST 1 0 1 1 0 1
Chip Core
0 1
0 1
1 0
David Lavo
28

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
EXTEST: ShiftDR
0 1 DATA TMS TDI TCK TDO TRST_N 1 1 1 1
David Lavo
0 1
0 1
0 1
0 1 TAP Controller EXTEST 0 1 0 1 0 1
Chip Core
0 1
0 1
0 1
30

Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0 1
0
Capture-DR
0 1 0
Capture-IR
0
Shift-DR
0
Shift-IR
1
Exit1-DR
1
Exit1-IR
0
Pause-DR
0
Pause-IR
1 0
Exit2-DR
1 0
Exit2-IR
1
Update-DR
1
Update-IR
EXTEST: UpdateDR
0 DATA TMS TDI TCK TDO TRST_N 0 0 TAP Controller EXTEST Mode=1 0 0 0 0
Chip Core
David Lavo
32
Outline
David Lavo
33
Boundary-Scan Documentation
IEEE Standard:
IEEE Std 1149.1-1990 & 1149.1a-1993: IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1b-1994: Supplement to IEEE Std 1149.1-1990 . (BDSL) IEEE Std 1149.1-2001
The Boundary-Scan Handbook, Second Edition (1998), by Ken Parker

34
Outline
David Lavo
35
Why JTAG is Cool

Adds a lot of test functionality with a small amount of effort
Board test Pad/parametric test Enhanced debug and diagnosis Control of TAP-based tests (BIST, clocks)
Functionally simple Ultra low performance: 5 to 10 MHz!

36
Lots of Uses Besides Board Test

On-chip access to BIST, programmable logic & EEPROMs, system and circuit test System configuration & maintenance:
David Lavo
37
Why JTAG is a Pain

Messes with chip timing! Complicates placement and routing Obtuse rules, motivations, language and documentation Requires some manual data entry or massaging No automated debugging tools
38
1149.1 Timing Impact

JTAG adds a mux, and sometimes a gate, into the data path
Insert JTAG early in design process!
The impact can be reduced to just a load by using a read-only cell

Intended only for clocks and other sensitive inputs Some test capability is lost
39
JTAG Input Cell/Macro
Data Path Capture Path Scan Path Update Path

40
JTAG Read-Only Input Cell/Macro

41
JTAG Output Cell/Macro

42
JTAG Output-Enable Cell/Macro

43
1149.1 Place & Route Impact

Boundary-scan register cells should be placed near associated pads
Best location is routing track next to pads Avoid long wires from registers to pads
TAP signals can cause routing congestion

From 3 to 5 global signals from TAP to each boundary-register cell (all around chip) Need to budget for this early
44
Placement of Boundary Registers

Good
Core
Bad
David Lavo
45
Global Routing Congestion
David Lavo
46
Outline
David Lavo
47
Beyond Board-Test: Extending the TAP Controller

The TAP Controller runs the show for boundary-scan and other TAP-based tests Some TAP-based test functions have become increasingly complex & specialized
Test signal control BIST control and capture Scan shifting
Most functions are based on TAP registers

48
Static Register: IDCODE

32 Bits predefined in internal register:
Version (4 bits) Part Number (16 bits) Manufacturer (11 bits) LSB is set to 1
1 X 0 X 1 X 0 X V P M 1 TDI 0 TDO 1 V 0 P 1 M 0 0 1
Scan out through TDO during IDCODE instruction

David Lavo
Instruction: BYPASS IDCODE
49
Update-Only: User Register

General-purpose bits User defines and connects signals Scan in a value (through TDI) to set Used for test modes, configurable logic, etc. No capture capability
David Lavo
1 0 1 1
TAP State: UpdateDR 0 1 0 0 0 1 0 1 0 0 0 1 0 1 1
TDI
TDO 0 0 0 0
Instruction: SELUSER
50
Capture/Update Register: RAMBIST

Capture and update capability User-defined signals:
Drive RAMBIST enable Read RAMBIST results
1 1 1 0
R0 TDI 1 0 1 X 1 1 1 1 0 R1 R2 X 4 R3 TAP State: ScanDR UpdateDR RunTest CaptureDR ScanDR
Scan in a value (through TDI) to set Scan out results through TDO
David Lavo
TDO 1 0 1 X
Instruction: SELRAMBIST RUNRAMBIST
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Jtag Intro

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Intro to IEEE 1149.

IEEE 1149.1 Boundary-Scan

Pad & Parametric Test

Boundary-Scan Register Chain Internal Data Registers (Optional)

TMS TDI TCK TDO TRST_N TAP Controller

TAP Controller Components

Finite State Machine

Various TAP Outputs: UpdateDR, CaptureDR, TriState, Etc.

TAP Controller State Diagram

BYPASS Data Path

Finite State Machine

EXTEST & SAMPLE/PRELOAD

TAP Controller State Diagram

Instruction Register Data Path

Finite State Machine

TAP Controller State Diagram

TMS TDI TC K TDO TRST_N

TAP Controller State Diagram

Mode=0 0 TAP Controller SMP/PRLD 0

TMS TDI TC K TDO TRST_N

TAP Controller State Diagram

0 1 TAP Controller SMP/PRLD 1 0 1 0 0 1

TAP Controller State Diagram

TAP Controller State Diagram

TAP Controller State Diagram

TAP Controller State Diagram

0 1 TAP Controller EXTEST 0 1 0 1 0 1

TAP Controller State Diagram

The Boundary-Scan Handbook, Second Edition (1998), by Ken Parker

Why JTAG is Cool

Functionally simple Ultra low performance: 5 to 10 MHz!

Lots of Uses Besides Board Test

Why JTAG is a Pain

1149.1 Timing Impact

The impact can be reduced to just a load by using a read-only cell

JTAG Input Cell/Macro

Data Path Capture Path Scan Path Update Path

JTAG Read-Only Input Cell/Macro

Data Path Capture Path Scan Path Update Path

JTAG Output Cell/Macro

Data Path Capture Path Scan Path Update Path

JTAG Output-Enable Cell/Macro

Data Path Capture Path Scan Path Update Path

1149.1 Place & Route Impact

TAP signals can cause routing congestion

Placement of Boundary Registers

Global Routing Congestion

Beyond Board-Test: Extending the TAP Controller

Most functions are based on TAP registers

Static Register: IDCODE

Scan out through TDO during IDCODE instruction

Instruction: BYPASS IDCODE

Update-Only: User Register

TAP State: UpdateDR 0 1 0 0 0 1 0 1 0 0 0 1 0 1 1

Capture/Update Register: RAMBIST

Instruction: SELRAMBIST RUNRAMBIST

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