SRAM MABL
FPGA and CPLD
Architectures: A Tutorial
Recenthy, [he development of
ew types of sophisticated field-
programmable devices (FPDs) has
‘dramatically changed the process
of designing digital hardware.
Unlike. previous generations of
hardware technology in which
board level designs included large
‘humbers of SSI (Smallscale inte-
gration) chips containing basic
gates, vntualy every digital design
produced today consists mostly of
high-density devices, This is tue
notonly ofcustom devices such as
processors and memory but also
‘of logic circuits such as state ma-
chine controllers, counters, regis
ters, and decoders. When such
citeuits are destined for high-vol-
ume systems, designers integrate
them into high-density gate arays.
However, the high nonrecurring
engineering costs and long manulac-
‘uring time of gate arrays make them
‘unsuitable for prototyping oroter low
volume scenarios. Therefore, most pro
totypes and many production designs
now use FPDs. The most compelling
advantages of FPDs are low startup
cost, jow financial risk, and, because
the end user programs the device,
‘quick manufacturing turnaround and
easy design changes.
a
STEPHEN BROWN,
JONATHAN ROSE
University of oronto
‘The FPD matket has grown over the
past decade to the point where there is
now a wide assortment of devices to
‘choose from. To choose a product, de
signers face the daunting task of re
searching the best uses of the various
chips and leaming the intricacies of
vendorspecific software, Adding tothe
dlifficulty isthe complexity ofthe more
sophisticated devices. To help sort out
the contusion, we providean overview
ovarersbotosene act
‘of the various FPD architectures
and discuss the most: important
‘commercial products.emphasiz-
Inglevices with relatively high loge
iccapaciy
Evolution of FPDs
The fist userprogrammable
chip that could implement logic civ
‘cuits was the programmable read=
‘only memory (PROM), in which
address lines serve as lage cieuit
inputs and-data lines as outputs.
Logie functions, however rarely re
‘quite more than’a few product
terms, and a PROM contains a fll
decoder for its address inputs.
PROMs are thus ineficient for veal
izing logic circuits, so designers
rarely use them for that purpose.
‘The first device developed
specifically for implementing log
ie circuits was the field;prograimmable
logie aray, or simply PLA for short. A
PLA consists oft Tevelsof louie gates:
‘a programmable, wived-AND plane fo:
lowed by-a programmable, wired OR
plane. A PLA's structure allows any of
its inputs (or their complements) to be
ANDed togetferin the AND plane; each
AND plane output can thas correspond
to any product terin of the-inputs
Similarly, users can configure each OR
REE DESION & TEST OF COMPUTERSplane output to produce the logical
sum ofany AND plane output. With tis
structure, PLAS are well-suited for im-
plementing logic functions in sum-of-
products form. They ate also quite
versatile, since both the AND and OR
terms can have many inputs (product,
literature often calls this feature “wide
AND and OR gates).
‘When Philips inoduced PLAsin the
early 1970s, theirmain drawbacks were
expense of manufacturing and some-
what poor speed performance. Both
disadvantages arose from the two lew-
‘ls of configurable logic; programma
ble logic planes were dificult to
‘manufacture and introduced significant
propagation delays. To overcome these
‘weaknesses, Monolithic Memories
(MM, later merged with Advanced
Micro Devices) developed PAL devices.
As Figure | shows, PAL feature only a
single level of programmability a pro-
grammable, wired AND plane that
feeds fixed OR gates. To compensate
forthelack of generality incurred by the
fixed-OR plane, PALs come in variants
with different numbers of inputs and.
‘outputs and various sizes of OR gates.
Toimplement sequential circuits, PALS
‘usually contain flipflops connected t0
the OR gate outputs.
‘The introduction of PAL devices pro-
foundly affected digital hardware de-
sign, and they are the basis of some of,
the newer, more sophisticated archi-
summer 1995
I i
rescmolne vl
AGSEEER TE
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| E Se cia ae
seplppueti da teh at
tectures that we will describe hori. | FPDs, including PLA, PAL, and PAL<
Variants of the basic PAL architecture | lke devices, into the single category of
appear in several products known by | simple programmablelogic devices
various acronyms. We group all small | (SPLDs), whose most important char
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Figure 3. FPD logic capactos.
acteristics are low cost and very high
pinsopin speed performance.
Advances in technology have pro:
‘duced devices with higher capacities
than SPLDs. The difficulty with inereas-
ing a strict SPLD architecture's capaci
O00 00 00
tyisthatthe programmablelogie plane
structure growstoo quickly asthe nur
ber of inputs increases. The only feast
ble way to provide largecapacity
devices based on SPLD architectaresis
to programmably interconnnect mult-
ple-SPLDs on a single chip. Many FPD
produols on therharket today havethis
basic structure and are known as com
plex programmablelogic devices.
Altera pioneered CPLDS, ist in thele
(Classic EPLD chips, anid then in the Max
5000, 700, and 9000 series. Because of
arepidly growing market for large FPDs,
other manufacturers develoged CPLD
dovices, and many choices ‘are now
available. CPLDs provide loge eapaci=
{yup tothe equivalent of about 50 yp
cal SPLD devices, but extending these
architectures to higher densities is dite
cult Buildiig FPDs with very igh logic
capacity requires a different approach,
‘The highest capacity general purpose
logic chips available today are the trae
ditional gate anys sometimes referred
to as mask:programunable gate-anrass.
An MPGA consists of an array-ol pre-
fabricated transistors customized forthe
users logic circuit by means of wie con
nections, Becaise the silicon foundry
perlonriseustomization during chip ab
‘ication,the manvlacturingiime istong,
and the uso’ setup casts high
Although MPGAs are early. not
FPDs, we mention them here because
they motivated thet design of tie fic
programimable equivalent, FPGAS Like
MPGAs, an FPGA consist ofan arayot
‘uncommitted circuit elements Clogic
blocks} and interconriect resoiniees,
but the end user configures the FPGA
through programming, Fiqure2showsa
typical FPGA archtecture