----------------------------------APB ----------------------------------1. How should AHB to APB bridges handle accesses that are not 32-bits?

The bridge should simply pass the entire 32-bit data bus through the bri dge. Please note that when transfers less than 32-bits are performed to an AP B slave it is important to ensure that the peripheral is located on the appropriate bits of the APB data bus. 2. e. Having this simple design makes it much easier to connect new APB periph erals and makes the analysis of the system performance easier to calculate. Although many APB peripherals are slow devices, such as UARTs, they are normally accessed via control registers. Typically the driver software will first access a status register to determine that data is available and only then acce ss the data register. Both of these accesses are possible without the addition of wait states and therefore the peripheral can easily be accessed as an APB dev ice. Peripherals which do require wait states can be designed as AHB slaves a nd in the rare case that a design does include a large number of these peri pherals then a secondary stub AHB can be used to reduce the loading on the main syste m bus. 3. How many clock cycles should the reset signal in an AMBA system be asser ted for? It is recommended that master and slave components should clearly state \ if they have a reset requirement greater than 1 or 2 cycles. It is also recommended that the system design should hold reset asserted for at least 16 cycles, unless it is known that a master or slave component has a longer reset r equirement. ----------------------------------AHB ----------------------------------http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ki1hk8p7dqPG1c. html 1. 2. 3. Why is there no wait signal on the APB? The APB has been designed to implement as simple an interface as possibl

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----------------------------------AXI ----------------------------------http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/kiSB3Z3GRT6S1Y. html 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.