Birzeit University - Faculty of Information Technology Computer Systems Engineering Department - ENCS234 Digital Systems - 2nd semester - 2011/12

HDL Project Due: May 5, 2012 Instructors: Dr. Ahmad Afaneh, Dr. Hanna Bullata We would like to design a circuit in HDL language that behaves as follows: 1. Adds two three-bit unsigned binary numbers found in registers A and B and place the result back in register A. Initially, the 2 registers contain zeros. 2. Includes a ag to determine when an overow occurs. 3. Includes a ag indicating whether the resulting sum is even or odd. You are required to build a Quartus project in groups of 2 students per group and that responds to the above specications. In case you need sequential elements in your design, you should choose JK ip-ops. In addition to building the Quartus project, you need to write down one report for each group that includes the following items: A. State diagram. B. Design. C. Verilog code. D. Simulation results showing timing diagrams. You should also create a test bench and test your design by completing the sums below: 000 + 000 010 + 001 011 + 011 111 + 001 Your inputs and outputs should be dened as follows: A2, A1, A0 B2, B1, B0: Represent your binary inputs where 0 denes least signicant bit. O represents the overow ag, no overow = 0. P represents the even/odd ag, even = 0.