Ex.

No : 5
Date :

Page No :
Roll No :

IMPLEMENTATION OF 7/4 BIT ARRAY DIVIDER IN FPGA

PROGRAM
----------------------------fulladd------------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port(
a,b,c:in std_logic;
sum,carry:out std_logic);
end fulladd;
architecture data of fulladd is
begin
sum<=a xor b xor c;
carry<=(a and b) or (b and c) or (a and c);
end data;
----------------------------xor2g-----------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity xor2g is
port(
a,b:in std_logic;
y:out std_logic);
end xor2g;
architecture data of xor2g is
begin
y<=a xor b;
end data;
-------------------------------cell-----------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity cell is
port(
a,b,t,cin:in std_logic;
r,q:out std_logic);
end cell;
architecture str of cell is
signal x:std_logic;
component fulladd is
port(
a,b,c:in std_logic;
sum,carry:out std_logic);

end component;
component xor2g is
port(
a,b:in std_logic;
y:out std_logic);
end component;
begin
v0:xor2g port map(b,t,x);
v1:fulladd port map(a,x,cin,r,q);
end str;
---------------------------------divider-----------------------------------------library ieee;
use ieee.std_logic_1164.all;
entity divider is
port(
a:in std_logic_vector(6 downto 0);
b:in std_logic_vector(3 downto 0);
ans:out std_logic_vector(3 downto 0);
r:out std_logic_vector(3 downto 0));
end divider;
architecture str of divider is
signal t:std_logic_vector(0 to 11);
signal c:std_logic_vector(0 to 11);
signal q:std_logic_vector(3 downto 0);
signal x:std_logic:='1';
component cell is
port(
a,b,t,cin:in std_logic;
r,q:out std_logic);
end component;
begin
v0:cell port map(a(3),b(0),x,x,t(0),c(0));
v1:cell port map(a(4),b(1),x,c(0),t(1),c(1));
v2:cell port map(a(5),b(2),x,c(1),t(2),c(2));
v3:cell port map(a(6),b(3),x,c(2),t(3),q(3));
v4:cell port map(a(2),b(0),q(3),q(3),t(4),c(3));
v5:cell port map(t(0),b(1),q(3),c(3),t(5),c(4));
v6:cell port map(t(1),b(2),q(3),c(4),t(6),c(5));
v7:cell port map(t(2),b(3),q(3),c(5),t(7),q(2));
v8:cell port map(a(1),b(0),q(2),q(2),t(8),c(6));
v9:cell port map(t(4),b(1),q(2),c(6),t(9),c(7));
v10:cell port map(t(5),b(2),q(2),c(7),t(10),c(8));
v11:cell port map(t(6),b(3),q(2),c(8),t(11),q(1));
v12:cell port map(a(0),b(0),q(1),q(1),r(0),c(9));
v13:cell port map(t(8),b(1),q(1),c(9),r(1),c(10));
v14:cell port map(t(9),b(2),q(1),c(10),r(2),c(11));
v15:cell port map(t(10),b(3),q(1),c(11),r(3),q(0));
ans<=q;

end str;

OUTPUT
IMPLEMENTATION OF 7/4 BIT ARRAY DIVIDER IN FPGA

Ex. No : 1
Date :

Page No :
Roll No :
IMPLENTATION OF 8 BIT ALU IN FPGA

PROGRAM
///////////////////////////////arthimeticicunit///////////////////////////////
module arith(c,a,b,s);
input [1:8]a,b;
input [2:0]s;
output [1:8]c;
reg[1:8]c;
always@(a or b or s)
begin
if(s==3'b000)
c=a+1;
if(s==3'b001)
c=a-1;
if(s==3'b010)
c=a+b;
if(s==3'b011)
c=a-b;
if(s==3'b100)
c=b+1;
if(s==3'b101)
c=b-1;
if(s==3'b110)
c=a[1:4]*b[1:4];
if(s==3'b111)

c=a[5:8]*b[5:8];
end
endmodule
///////////////////////////////logicunit///////////////////////////////
module logic(d,a,b,s);
input [1:8]a,b;
input [2:0]s;
output [1:8]d;
reg[1:8]d;
always@(a or b or s)
begin
if(s==3'b000)
d=a&b;
if(s==3'b001)
d=a|b;
if(s==3'b010)
d=~a;
if(s==3'b011)
d=~b;
if(s==3'b100)
d=~(a&b);
if(s==3'b101)
d=~(a|b);
if(s==3'b110)
d=a^b;
else
d=~(a^b);
end

endmodule
///////////////////////////////mux///////////////////////////////
module mux(y,c,d,s);
input [1:8]c,d;
input s;
output [1:8]y;
reg[1:8]y;
always@(c or d or s)
begin
if (s==1'b0)
y=c;
else
y=d;
end
endmodule
///////////////////////////////alu///////////////////////////////
module alu(y,a,b,s);
input [1:8]a,b;
input [3:0]s;
output [1:8]y;
wire [1:8]c,d;
arith v0(c,a,b,s[2:0]);
logic v1(d,a,b,s[2:0]);
mux v3(y,c,d,s[3]);
endmodule
///////////////////////////////////////////////////////////////////////

OUTPUT:
IMPLENTATION OF 8 BIT ALU IN FPGA

Ex. No : 3
Date :

Page No :
Roll No :

IMPLEMENTATION OF 8 BIT ADDER AND SUBTRACTOR

PROGRAM
//////////////////////xor2g/////////////////////////
module xor2g(y,a,b);
input a,b;
output y;
assign y=(a ^ b);
endmodule
//////////////////////and2g///////////////////////
module and2g(y,a,b);
input a,b;
output y;
assign y=a & b;
endmodule
/////////////////////////xor3g////////////////////
module xor3g(y,a,b,c);
input a,b,c;
output y;
assign y=a ^ b ^ c;
endmodule
///////////////////////or3g////////////////////////////
module or3g(y,a,b,c);
input a,b,c;
output y;

assign y=a | b | c;
endmodule
/////////////////////////fa/////////////////////////////
module fa(s,cy,a,b,c);
input a,b,c;
output s,cy;
wire [1:3]t;
xor3g g1(s,a,b,c);
and2g g2(t[1],a,b);
and2g g3(t[2],b,c);
and2g g4(t[3],a,c);
or3g g5(cy,t[1],t[2],t[3]);
endmodule
///////////////////////////addsub///////////////////////
module addsub(s,cout,a,b,m);
input [7:0] a,b;
input m;
output [7:0] s;
output cout;
wire [0:6]c;
wire [0:7]t;
xor2g x1(t[0],m,b[0]);
xor2g x2(t[1],m,b[1]);
xor2g x3(t[2],m,b[2]);
xor2g x4(t[3],m,b[3]);
xor2g x5(t[4],m,b[4]);
xor2g x6(t[5],m,b[5]);
xor2g x7(t[6],m,b[6]);

fa x9(s[0],c[0],a[0],t[0],m);
fa x10(s[1],c[1],a[1],t[1],c[0]);
fa x11(s[2],c[2],a[2],t[2],c[1]);
fa x12(s[3],c[3],a[3],t[3],c[2]);
fa x13(s[4],c[4],a[4],t[4],c[3]);
fa x14(s[5],c[5],a[5],t[5],c[4]);
fa x15(s[6],c[6],a[6],t[6],c[5]);
fa x16(s[7],cout,a[7],t[7],c[6]);
endmodule
////////////////////////////////////////////////////////////////
OUTPUT:

IMPLEMENTATION OF 8 BIT ADDER AND SUBTRACTOR

Ex. No : 2
Date :

Page No :
Roll No :

IMPLENTATION OF 4 BIT SLICED (ALU) PROCESSOR IN FPGA

PROGRAM
///////////////////////////////mux///////////////////////////////
module mux(y,c,d,e,f,s);
input c,d,e,f;
input [1:0]s;
output y;
reg y;
always@(c or d or e or f or s)
begin
if (s==2'b00)
y=c;
if(s==2'b01)
y=d;
if(s==2'b10)
y=e;
if(s==2'b11)
y=f;
end
endmodule
/////////////////////////////and2g////////////////////////////////
module and2g(y,a,b);
input a,b;
output y;
assign y = a & b;
endmodule
//////////////////////////or3g///////////////////////////////////

module or3g(y,a,b,c);
input a,b,c;
output y;
assign y = a | b | c;
endmodule
//////////////////////////////////////fa4g////////////////////////////////////
module fa4g(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire t1,t2,t3,t4;
ex2g g1(t1,a,b);
ex2g g2(sum,t1,cin);
and2g g3(t2,a,b);
and2g g4(t3,b,cin);
and2g g5(t4,a,cin);
or3g g6(cout,t2,t3,t4);
endmodule
////////////////////////////////ex2g////////////////////
module ex2g(y,a,b);
input a,b;
output y;
assign y = -( a ^ b );
endmodule
/////////////////////////not5g////////////////////////////////////
module not5g(y,a);
input a;
output y;
assign y = ~ a;
endmodule

//////////////////////////or6g///////////////////////////////////
module or6g(y,a,b);
input a,b;
output y;
assign y = a | b;
endmodule
//////////////////////////alu///////////////////////////////////
module alu(y,z,a,b,cin,s);
output y,z;
input a,b,cin;
input [1:0]s;
wire c,d,e,f;
and2g g1(c,a,b);
or6g g2(d,a,b);
not5g g4(e,b);
fa4g g3(f,z,a,b,cin);
mux g5(y,c,d,e,f,s);
endmodule
////////////////////////salu//////////////////////////////////
module salu(y,z,a,b,cin,s);
output [3:0]y;
output z;
input [3:0]a,b;
input [1:0]s;
input cin;
wire t[2:0];
alu g6(y[0],t[0],a[0],b[0],cin,s[1:0]);
alu g7(y[1],t[1],a[1],b[1],t[0],s[1:0]);
alu g8(y[2],t[2],a[2],b[2],t[1],s[1:0]);

alu g9(y[3],z,a[3],b[3],t[2],s[1:0]);
endmodule
///////////////////////////////////////////////////////////////

OUTPUT :
IMPLENTATION OF 4 BIT SLICED (ALU) PROCESSOR IN FPGA

Ex. No : 4
Date :

Page No :
Roll No :

IMPLEMENTATION OF 4 BIT PARALLEL MULTIPLIER IN FPGA

/////////////////////////////////////////and2g////////////////////////////////////
module and2g(y,a,b);
input a,b;
output y;
assign y=a & b;
endmodule
/////////////////////////////////////////full adder///////////////////////////////
module fulladder(sum,carry,a,b,c);
input a,b,c;
output sum,carry;
assign sum=(a^b^c);
assign carry=(a&b)|(b&c)|(c&a);
endmodule
//////////////////////////////////////////pmultiplier///////////////////////////////////////
module pmultiplier(p,a,b,z);
input [3:0]a,b;
input z;
output [8:1]p;
wire t[1:15];
wire c[1:17];
and2g v0(p[1],a[0],b[0]);
and2g v1(t[1],a[1],b[0]);
and2g v2(t[2],a[2],b[0]);
and2g v3(t[3],a[3],b[0]);
and2g v4(t[4],a[0],b[1]);
and2g v5(t[5],a[1],b[1]);
and2g v6(t[6],a[2],b[1]);
and2g v7(t[7],a[3],b[1]);
and2g v8(t[8],a[0],b[2]);

and2g v9(t[9],a[1],b[2]);
and2g v10(t[10],a[2],b[2]);
and2g v11(t[11],a[3],b[2]);
and2g v12(t[12],a[0],b[3]);
and2g v13(t[13],a[1],b[3]);
and2g v14(t[14],a[2],b[3]);
and2g v15(t[15],a[3],b[3]);
fulladder v16(p[2],c[1],t[1],t[4],z);
fulladder v17(c[3],c[2],t[2],t[5],z);
fulladder v18(p[3],c[4],c[1],c[3],t[8]);
fulladder v19(c[6],c[5],t[3],t[6],z);
fulladder v20(c[8],c[7],c[2],c[6],t[9]);
fulladder v21(p[4],c[9],c[4],c[8],t[12]);
fulladder v22(c[11],c[10],t[7],t[10],c[5]);
fulladder v23(c[13],c[12],c[7],c[11],t[13]);
fulladder v24(p[5],c[14],c[9],c[13],z);
fulladder v25(c[16],c[15],t[11],c[10],t[14]);
fulladder v26(p[6],c[17],c[14],c[16],c[12]);
fulladder v27(p[7],p[8],t[15],c[15],c[17]);
endmodule
/////////////////////////////////////////////////////////////////////////////////////////////

OUTPUT:
IMPLEMENTATION OF 4 BIT PARALLEL MULTIPLIER IN FPGA

Ex. No : 7
Date :

Page No :
Roll No :
FM TRACKING APPLICATION USING PLL

%% PLL IN FM TRACKING APPLICATION:%%

clear all;
close all;
f=1000;
fs=100000;
N=5000;
Ts=1/fs;
t=(0:Ts:(N*Ts)-Ts);
f1=100;
msg=sin(2*pi*f1*t);
kf=.0628;
signal=exp(j*(2*pi*f*t+2*pi*kf*cumsum(msg)));
signal1=exp(j*(2*pi*f*t));
phi_hat(1)=30;
e(1)=0;
phd_output(1)=0;
vco(1)=0;
kp=0.15;
ki=0.1;
for n=2:length(signal)
vco(n)=conj(exp(j*(2*pi*n*f/fs+phi_hat(n-1))));
phd_output(n)=imag(signal(n)*vco(n));
%signal input
e(n)=e(n-1)+((kp+ki)*phd_output(n))-(ki*phd_output(n-1));
phi_hat(n)=phi_hat(n-1)+e(n);
end;
startplot=1;
endplot=1000;

figure(1);
subplot(3,2,1);
plot(t(startplot:endplot),msg(startplot:endplot));
title('100 Hz message signal');
%xlabel('time(seconds)');
ylabel('Amplitude');
grid;
figure(1);
subplot(3,2,2);
plot(t(startplot:endplot),real(signal(startplot:endplot)));
title('FM(1KHz carrier modulated with a 100Hz message signal)');
%xlabel('time(seconds)');
ylabel('Amplitude');
grid;
figure(1);
subplot(3,2,3);
plot(t(startplot:endplot),e(startplot:endplot));
title('PLL Loop filter/Integrator output');
%xlabel('time(seconds)');
ylabel('Amplitude');
grid;
subplot(3,2,4);
plot(t(startplot:endplot),real(vco(startplot:endplot)));
title('VCO Output(PLL tracking the input signal)');
%xlabel('time(seconds)');
ylabel('Amplitude');
grid;
subplot(3,2,5);
plot(t(startplot:endplot),phd_output(startplot:endplot));
title('Phase detector output');
xlabel('time(seconds)');
ylabel('Amplitude');

grid;
subplot(3,2,6);
plot(t(startplot:endplot),real(signal1(startplot:endplot)));
title('Unmodulated carrier');
xlabel('time(seconds)');
ylabel('Amplitude');
grid;

OUTPUT:
FM TRACKING APPLICATION USING PLL

Ex. No : 6
Date :

Page No :
Roll No :

FM MODULATION AND DEMODULATION USING PLL

%%CODE FOR FM MODULATION AND DEMODULATION USING PLL:%%
%%
clear all;
close all;
t0=0.15;
ts=0.0005;
fc=200;
kf=50;
fs=1/ts;
t=(0:ts:t0);
df=0.25;
c=cos(2*pi*fc*t);
m=[2*ones(1,t0/(3*ts)),-2*ones(1,t0/(3*ts)),zeros(1,t0/(3*ts)+1)];
int_m(1)=0;
for i=1:length(t)-1
int_m(i+1)=int_m(i)+(m(i)*ts);
end
u=cos(2*pi*fc*t+2*pi*kf*int_m);
figure
subplot(3,1,1)
plot(m(1:300))
title('modulating signal')
grid on;
subplot(3,1,2)
plot(c(1:300))
title('carrier signal')
grid on;
subplot(3,1,3)

plot(u(1:300))
title('frequency modulated signal')
grid on;
t=(0:ts:ts*(length(u)-1));
x=hilbert(u);
z=x.*exp(-j*2*pi*250*t);
phi=angle(z);
phi=unwrap(phi);
dem=(1/(2*pi*kf))*(diff(phi)/ts);
figure
subplot(3,1,1)
plot(c(1:300))
title('carrier signal')
grid on;
subplot(3,1,2)
plot(u(1:300))
title('frequency modulated signal')
grid on;
subplot(3,1,3)
dem=smooth(dem,7)+1;
plot(dem(1:300))
axis([0 300 -2 2]);
title('demodulated signal')
grid on;

OUTPUT:

FM MODULATION AND DEMODULATION USING PLL