Advanced Debug With Questa

Chuck Seeley Verification Technologist DVT

Agenda
Introduction Debug Enhancements for Traditional Languages Debugging Constraints Debugging Assertions Debugging Dynamic Objects

Todays Verification
Designs grow ~2x every 18 months

Moores law still applies 2x more logic and complexity to verify Higher quality verification demanded

Verification requirements grow faster

Companies with the highest verification productivity

Get new products to market faster Take maximum advantage of Moores law Build the most competitive products

Debug - A Big Challenge

Designs continue to include Verilog/VHDL/SystemC and now SystemVerilog Transition to HVL improve verification productivity at the price of debug productivity
Introduces

new debug paradigm

OVM delivering advanced techniques to everyone Ability to create unknown out-of-body code experiences
Language and methodology are the starting point

Questa - Advancing Productivity

6.0 6.1 6.2 April 06 6.3 May 07 6.4 June 08 6.5 Q1 09 Aug 04 June 05

SV Testbench/AVM 1.x SVA and PSL Functional coverage VOPT Verilog TLM support

Verification Management SV OVM 1.0 Power-Aware Simulation SV&SC Transaction View Assertion Thread View Post-Sim Debug

Window Manager Hyperlinked navigation FSM Viewing VHDL Hierarchical References VHDL Encryption Lossless Cover Merge

SystemC SystemVerilog VHDL and Verilog Modernized GUI

SV Testbench/AVM 2.x Unified Coverage Database VOPT SV, VHDL & SystemC Full SystemC TLM FSM extraction Source Code Annotation

Class browsing & wave viewing SV/SystemC thread debugging UPF Power-Aware SystemC TLM 2.0 Time to next simulation improvements

Questa The Most Advanced Functional Verification Platform

Leader in mixed language interoperability Highest performance for gate-level, RTL and TLM Fastest, highest capacity Unified Coverage Data Base (UCDB) Powerful Verification Management tools to reach coverage closure faster Unified debug for all languages and abstraction levels

Proven Technology

Agenda
Introduction Debugging Enhancements for Traditional Languages Debugging Constraints Debugging Assertions Debugging Dynamic Objects

Easing Processes Debug

Toggle between viewing modes View all processes together regardless of language

All Windows linked to process window

Integral with SystemC Debug Interface

Message Viewer

Source Code Annotation

Linked to cursor location in wave window Linked to dataflow window

Textual Dataflow: Tracing Signals

Find reader of strb_r

Select Signal then RMB

Textual Dataflow: Tracing Signals

Find driver(s) of prdy_r

Select Signal then RMB

Drop Source To Waveform

Wave Window: Signal Grouping

Group signals under user defined name

Drag & drop signals into and out of group Drag & drop group as one object Collapse & expand group as needed

Wave Window: Expanded Time

Expand the Wave Window to view all transitions during a single time step.
Blue background indicates expanded section

Indicates multiple transitions

Delta-time steps

Easing Causality Tracing Source Code Hyperlinking

Optional source code hyperlinking

Hyperlinked variables

16

Easing Causality Tracing Source Code Hyperlinking

Jump to source window and highlight variable declaration

17

Comprehensive FSM Debug Solution

Select FSM from list State diagram animation linked to active wave cursor

State variables identified with FSM icon

FSM Debug with transition expressions

Control display of: * Transition counts * State counts * Conditional paths * Balloon popups * Wave cursor linking

FSM states: * Brown - Reset state * Yellow - Previous state * Green - Present state * Blue - Not one of the above

Agenda
Introduction Debugging Enhancements for Traditional Languages Debugging Constraints Debugging Assertions Debugging Dynamic Objects

Failures during Randomization

Error reported for failed randomization of a class object

Debugging Constraint Solver

On randomize() failure, display the minimum set of constraints that caused failure
Default

is off Setting SolveFailDebug in the modelsim.ini file

SolveFailDebug = 1

Using Using

-solvefaildebug on vsim command line verilog attribute in source code

vsim solvefaildebug

randomize (* solvefaildebug=1 *) (a, b) with {a > b; a < b;};

Debugging Failures in Constraint Solver

Derived class constraint contains a conflict
c0
class TFoo; rand bit [5:0] a, constraint c1 { a constraint c2 { b constraint c3 { a constraint c4 { b constraint c5 { c endclass b, c; < b; } < c; } < 23; } > 12; } == 20; }

in child c1 and c2 in parent

class TBar extends TFoo; constraint c0 { a == c; } endclass TBar f = new; int status; $display("status = f.randomize();");

vsim solvefaildebug Simulator output:

# test.v(22): randomize() failed due to conflicts between the following constraints: # test.v(5): ((f.a)<(f.b)) # test.v(6): ((f.b)<(f.c)) # test.v(13): ((f.a)==(f.c))

Constraint Solver Performance

Adjusting performance for certain types of constraints
May improve

or decrease performance Command line: -solveflags=<flags> modelsim.ini file: SolveFlags = <flags>

Valid flags are:

i = disable bit interleaving for >, >=, <, <= constraints n = disable bit interleaving for all constraints r = reverse bit interleaving

Getting more information about what solver is doing

Command line: solveverbose [1 or 2] Verbose messaging typically requires interpretation by R&D

Agenda
Introduction Debugging Enhancements for Traditional Languages Debugging Constraints Debugging Assertions Debugging Dynamic Objects

Simulation With Assertion

Questa ABV added value
Advance

Debug capabilities for PSL & SVA

Integrated Assertion Browser View assertions in wave window Assertion Thread Viewer
Best

root cause analysis

Analysis Window

Capacity Details Analysis Window

Pinpoint effects of Assertions on Performance & Memory Usage

Effects of Cover Directives Effects of Covergroups

Viewing Assertions in the Wave

Green mid-line indicates assertion is active Green triangle indicates assertion passed Red inverted triangle indicates assertion failure

Blue low-line indicates assertion is inactive Simply D&D Assertions from Assertion Browser into Wave Window to view assertions Assertions can be expanded to view all signals associated with the assertion

Multiple Threads in Wave Window

Blue box above thread indicates start of new thread RMC on start of thread box invokes ATV

Automatic Thread count integer Expand to see individual thread

Advanced Assertion Debug with ATV

Expanded assertion Red dot indicates expression is false

Green dot indicates expression is true

Redundant failure: individual spawned thread failed but other threads still active
Yellow dot indicates additional thread spawned

Local variable pane

ATV and Local Variables

Annotation of local variable on selected thread Blue boxes indicate local variable sampling

Toggle Local Variable Pane

Wave Window: Signal Grouping

Group signals under user defined name

Drag & drop signals into and out of group Drag & drop group as one object Collapse & expand group as needed

Agenda
Introduction Debugging Enhancements for Traditional Languages Debugging Constraints Debugging Assertions Debugging Dynamic Objects

Viewing/Debugging SV Class Objects

Information about SV class objects available in several forms:
Objects/Locals

Windows Watch Window Class Tree/Class Graph Structure Window

SV testbench structure for AVM/OVM
Wave

Window

Transaction Viewing and Classes objects

Debugging Dynamic Objects

View class contents and property values

Useful when setting breakpoints & single stepping

Enhanced Watch Window

Display values for signals & variables

View dynamic and static objects together

arrange objects independently object grouping quickly scroll window with mouse panning
Highlight selected relationship

Understand class relationships See class member values

Class Tree Window

Classes can be organized by extended class

View parent/child relationship

Classes can also be organized by base class

View all methods & properties within a class

Class Graph Window

Zoom out to see entire hierarchy Hover cursor over block to see name Graph window shows all methods & properties

Default view organized by extended class, can also be viewed by base class

Transaction Viewing: The Wave Window

OVM/AVM stimulus are transactions in streams of data Questa SV Transaction API enables viewing of any SV transactions View and debug at the
transaction level

OVM/AVM Classes and Questa

Questa extracts SV TB structure from OVM/AVM class based environment

OVM/AVM source code instrumented with Questa specific PLI calls

TB extraction occurs automatically only when using pre-compiled OVM/AVM package or source code (Closed kit)

OVM/AVM static component classes are converted into design scopes

Includes ovm_components, analysis/tlm_fifoss, ovm_subscriber Object window contents are filtered to show only user added members Visible in sim tab of Workspace after run 0 (after OVMs end_of_elab phase) OVM ENV OVM ENV

DUT DUT

Workspace Instances
Module based hierarchy created by vopt/vsim elaboration
module cpu_wb_environment; cpu_wb_agent wb_agent(); eth_mii_rx_agent rx_agent(); eth_mii_tx_agent tx_agent(); endmodule

Workspace Instances
Component hierarchy created at runtime
class cpu_wb_environment extends ovm_env; cpu_wb_agent wb_agent; eth_mii_rx_agent rx_agent; eth_mii_tx_agent tx_agent; function new() endfunction function void build; wb_agent = new("wb_agent",this); rx_agent = new("rx_agent",this); tx_agent = new("tx_agent",this); endfunction // new endclass module top; cpu_wb_environment env; initial begin env = new(env); env.run_test(); end endmodule

Other Windows and OVM TB Class

scenario_base is not an ovm_component Environment Class converted to a scope Sub-Env components converted to scopes

Wave window name reflects static class hierarchy scenario_base class reference can be added to and viewed in the wave window

Object Window contents are filtered to show only user added members

@333 is the value assigned to scenario_bases class variable

Class Objects in Wave Window

Class variable value assigned by simulator

View a class object by adding specific class variable to wave window

Summary
Questas debug features which will increase your verification productivity

industry leading integrated and interactive debugging features supporting mixed languages in single environment

Questas debug features will increase verification productivity of traditional languages and techniques

Verilog, VHDL, and SystemC

Questas supports advanced debug features required by todays advanced verification languages and methodologies

SV based verification methodologies

OVM/AVM/VMM

Dynamic object support

SV/SC Transaction and Class viewing

Assertion Based Verification

SVA and PSL