A Comparative study and Design of Full Adder cells using Carbon Nano Tube FET Dr.V.Malleswararao1, P.H.S.TejoMurthy2, V.

Nooka Raju3 1 Professor,GITAM University,Visakhapatnam,India. 2 ,3 Assistant Professor, GITAM University,Visakhapatnam,India. Abstract Adders are the core elements of the complex arithmetic operations. These are the essential component which limits the speed of the operation of the overall systems like DSP Processors, Microprocessors etc. In this paper, we are proposing a new full adder based on FTL Logic using Carbon Nano Tube FETs which are suitable for biomedical sensor applications. The proposed method significantly reduces the problem of Threshold voltage loss. The results are compared with 8-T, 10-T and 16-T full adders using CMOS and Carbon Nano tube FETs. I Introduction The basic building blocks of full adders are XOR, XNOR and AND gates. In the literature, various XOR, XNOR have been proposed which are motivated by three design goals viz. Minimizing the Transistor Count, Minimizing the Power Consumption and Increasing the Speed of the system. Therefore the low power design is of the major consideration. The conventional adder requires 28-Transistors are implemented in CMOS technology and it has full rail to rail voltage. But the problem with 28-Transistor full adder is the more dynamic power consumption and large area requirement. These problems are avoided by various full adders proposed in the literature. These low power full adders have the problem of threshold voltage loss thus produce weak 0 and weak 1 However; these are very useful in many applications like Multipliers etc. In the following section we shall discuss elaborately about the advantages and disadvantages of these gates. II 4-Transistor XOR and XNOR Gates The 4-Transistor XOR and XNOR Gates are shown in the figure (). The XNOR gate uses pass transistor logic. The pull down network is built in such a way that, the input of one transistor is used as source to another transistor. A is always compared with B and vice versa. If both are same then only the transistors will be ON and creates the discharging path.

Fig1:XNOR

Fig2: XNOR Using CNFET

Fig3: XNOR Using 50nm technology As shown in the above figure it is shown that there is significant threshold loss. It is implemented both with CMOS 50nm technology and Carbon Nano Tube FETs. The advantage of using CNFET here is it increases the speed of operation with out threshold loss for logic 1.The following table explains the comparison between the two technologies.

A
0 0 1 1

B
0 1 0 1

OUT 50nm
Weak 1 Strong 0 Weak 0 Weak 1

CNFET
Strong 1 Strong 0 Weak 0 Strong 1

Table1: Comparison of XNOR between 50nm and CNFET

Fig4: Full Adder Sum Implementation Using 8-Transistors III Proposed circuit The circuit shown in figure () is based on feed through evaluation concept. It consists of NMOS logic network and a pull down transistor (Td) for discharging the output node to low logic level and a pull up PMOS load transistor (Tp). Td and Tp are operated by a clock signal. The advantages of FTL logic over Dynamic logic are the elimination of cascading problem and charge sharing problem. FTL always resets the out put node during the resetting phase and during the evaluation phase it MP1 is ON and MP2 will be OFF. Irrespective of the input values cascaded gats first rise to Vdd/2 and depending on the input values the output may rise to Vdd or remains same. So there is only a partial transition which increases the speed of operation. It has the advantage of domino type cascaded stages. So FTL speed is high because it reduces both low to high and high to low propagation delays. The below circuit is implemented in such a way that A is given as source to B transistor or vice versa.

Fig5: FTL Based XNOR Gate

Fig6: Waveforms of FTL Based XNOR Gate As shown in the above figure the circuit is operated with V p as clock during the low clock cycle (evaluation period) circuit may produce the logical levels Vdd and Vdd/2. Here Vdd/2 is treated as low logic level and Vdd is treated as high logic level. This logic is suitable for biomedical applications where compact circuit with high speed is required. The circuit is tested for both CNFET and 50nm Technology. The main advantage of FTL based XNOR gate is it always produce Strong logic 1. The circuit is tested for several combinations and functionalities are verified. The following comparison table shows the significant improvement of FTL based circuits over 4-Transistor XOR.

TECHNOLOGY RISE TIME(ps) FALL TIME FTL (50nm) 8.515 7.447 4-T XNOR(50nm) 12.35 11.6 FTL CNFET 6.21 5.34 4-T XNOR CNFET 7.1 6.3 Table2: Comparison of XNOR gate using 50nm and CNFET Technology

Fig 7: FTL based FULL ADDER

Fig 8: Waveforms of FTL based FULL ADDER V Conclusion In this paper, we have compared the performance of FTL based XNOR gates and 4Transistor XNOR gate in 50nm and CNFET technologies. The results are compared first with 2V operation and then with 1V operation. FTL based circuits shows significant

performance improvement over the 4T Xnor gates. The results are verified for full adder also. The maximum propagation delay observed for FTL based circuis observed is 6.31ps. VI References 1) Bardia Bozorgzadeh1, Ehsan Zhian-Tabasy1, and Ali Afzali-Kusha1 Low-Power HighPerformance Logic Style for Low-Voltage CMOS Technologies Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran,Tehran, Iran

2)

Yi WEI, Ji-zhong SHEN Design of a novel low power 8-transistor 1-bit full adder cell
(Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China)

3) Mark Lundstrom Device Physics of Carbon Nanotube FETs Network for Computational Nanotechnology and Purdue University 465 Northwestern Avenue West Lafayette, IN 47907.
4) Mehdi Bagherizadeh1* and Mohammad Eshghi2 Two novel low-power and high-speed
dynamic carbon nanotube full-adder cells

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8