Contents:

Introduction Block Diagram and Pin Description of the 8051 Registers Memory mapping in 8051 Stack in the 8051 I/O Port Programming Timer Interrupt

Why do we need to learn Microprocessors/controllers?

The microprocessor is the core of computer systems. Nowadays many communication, digital entertainment, portable devices, are controlled by them. A designer should know what types of components he needs, ways to reduce production costs and product reliable.

Different aspects of a microprocessor/controller

Hardware :Interface to the real world

Software :order how to deal with inputs

The necessary tools for a microprocessor/controller

CPU: Central Processing Unit I/O: Input /Output Bus: Address bus & Data bus Memory: RAM & ROM Timer Interrupt Serial Port Parallel Port

General-purpose microprocessor
CPU for Computers No RAM, ROM, I/O on CPU chip itself ExampleIntels x86, Motorolas 680x0
Many chips on mothers board

Microprocessors:

CPU GeneralPurpose Microprocessor

Data Bus

RAM

ROM

I/O Port

Timer

Serial COM Port

Address Bus General-Purpose Microprocessor System

Microcontroller :
A smaller computer On-chip RAM, ROM, I/O ports... ExampleMotorolas 6811, Intels 8051, Zilogs Z8 and PIC 16X
CPU I/O Port RAM ROM Serial Timer COM Port

A single chip
Microcontroller

Microprocessor vs. Microcontroller

Microprocessor CPU is stand-alone, RAM, ROM, I/O, timer are separate designer can decide on the amount of ROM, RAM and I/O ports. expansive versatility general-purpose

Microcontroller CPU, RAM, ROM, I/O and timer are all on a single chip fix amount of on-chip ROM, RAM, I/O ports for applications in which cost, power and space are critical single-purpose

Embedded System
Embedded system means the processor is embedded into that application. An embedded product uses a microprocessor or microcontroller to do one task only. In an embedded system, there is only one application software that is typically burned into ROM. Exampleprinter, keyboard, video game player

Three criteria in Choosing a Microcontroller

1.

Meeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit 2. Availability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support 3. Wide availability and reliable sources of the microcontrollers.

Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU Serial Port

OSC

Bus Control

4 I/O Ports

P0 P1 P2 P3

TxD RxD

Address/Data

 89C51 Microcontroller Pin Diagram

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0(RXD) P3.1(TXD) P3.2(INT0) P3.3(INT1) P3.4(T0) P3.5(T1) P3.6(WR) P3.7(RD) XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 +5V P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/(VPP) ALE(PROG) PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

40 PIN DIP

Indian Institute for Production Management

Pins of 80511/4

Vccpin 40 Vcc provides supply voltage to the chip. The voltage source is +5V. GNDpin 20ground XTAL1 and XTAL2pins 19,18

Figure (a). XTAL Connection to 8051

Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin.

Pins of 80512/4

RSTpin 9reset It is an input pin and is active highnormally low. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers

Figure Vcc
+

(b). Power-On RESET Circuit

10 uF 30 pF 11.0592 MHz 30 pF

31 19 18

EA/VPP X1 X2

8.2 K

9 RST

Pins of 80513/4

/EApin 31external access

There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSENpin 29program store enable This is an output pin and is connected to the OE pin of the ROM.

Pins of 80514/4

ALEpin 30address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.

Pins of I/O Port

The 8051 has four I/O ports Port 0 pins 32-39P0P0.0P0.7 Port 1pins 1-8 P1P1.0P1.7 Port 2pins 21-28P2P2.0P2.7 Port 3pins 10-17P3P3.0P3.7 Each port has 8 pins. Named P0.X X=0,1,...,7, P1.X, P2.X, P3.X ExP0.0 is the bit 0LSBof P0 ExP0.7 is the bit 7MSBof P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction).

Hardware Structure of I/O Pin

Each pin of I/O ports Internal CPU buscommunicate with CPU A D latch store the value of this pin D latch is controlled by Write to latch Write to latch1write data into the D latch 2 Tri-state buffer TB1: controlled by Read pin Read pin1really read the data present at the pin TB2: controlled by Read latch Read latch1read value from internal latch A transistor M1 gate Gate=0: open Gate=1: close

D Latch:

A Pin of Port 1
Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch
D Q

P1.X
Clk Q

P1.X pin M1

TB1 Read pin

P0.x
8051 IC

Writing 1 to Output Pin P1.X

Read latch TB2 Vcc Load(L1) 2. output pin is

1. write a 1 to the pin

Internal CPU bus Write to latch
D Q

Vcc

1 0
M1

P1.X
Clk Q

P1.X pin

output 1

TB1 Read pin

8051 IC

Writing 0 to Output Pin P1.X

Read latch TB2 Vcc Load(L1) 2. output pin is

1. write a 0 to the pin

Internal CPU bus Write to latch
D Q

ground
P1.X pin

0 1
M1

P1.X
Clk Q

output 0

TB1 Read pin

8051 IC

Reading High at Input Pin

Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 1 P1.X pin Vcc 2. MOV A,P1 external pin=High

Q
P1.X

Write to latch

Clk

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1

8051 IC

Reading Low at Input Pin

Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 0 Vcc 2. MOV A,P1 external pin=Low

Q
P1.X

P1.X pin

Write to latch

Clk

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1

8051 IC

Other Pins
P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain. P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P0 is open drain. Compare the figures of P1.X and P0.X. However, for a programmer, it is the same to program P0, P1, P2 and P3. All the ports upon RESET are configured as output.

A Pin of Port 0
Read latch TB2

Internal CPU bus Write to latch

P1.X
Clk Q

P0.X pin M1

TB1 Read pin

8051 IC

Port 0 with Pull-Up Resistors

Vcc 10 K

DS5000 8751 8951

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

Port 0

Port 3 Alternate Functions

P3 Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Function RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17

RESET Value of Some 8051 Registers:

Register PC ACC B PSW SP DPTR RAM are all zero.

Reset Value 0000 0000 0000 0000 0007 0000

Registers
A B R0 R1 R2 R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register PC PC DPTR DPH DPL

Memory mapping in 8051

ROM memory map in 8051 family
4k
0000H 0000H

8k
0000H

32k

0FFFH DS5000-32 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH

from Atmel Corporation

from Dallas Semiconductor

 RAM memory space allocation in the 8051

7FH Scratch pad RAM

30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 (Stack) Register Bank 1

Register Bank 0

Stack in the 8051

The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0

Timer :

TMOD Register:

Gate : When set, timer only runs while INT(0,1) is C/T : Counter/Timer select bit. M1 : Mode bit 1. M0 : Mode bit 0.

high.

TCON Register:

TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Timer 0 overflag. TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag.

Interrupt :

Interrupt Enable Register :

EA : Global enable/disable.
--: Undefined.

ET2 :Enable Timer 2 interrupt. ES :Enable Serial port interrupt. ET1 :Enable Timer 1 interrupt. EX1 :Enable External 1 interrupt. ET0 : Enable Timer 0 interrupt. EX0 : Enable External 0 interrupt.