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United

States Patent

Moore et al.

[19]

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

US005530890A

[11]

[45]

Patent

Number:

Date of Patent:

5,530,890

Jun. 25, 1996

[54]

HIGH PERFORMANCE,

LOW COST

MICROPROCESSOR

 

[75]

Inventors:

Charles

H. Moore,

Woodside;

Russell

 

H. Fish, IH, Mt. View, both of Calif.

[73]

Assignee:

Nanotronics

Corporation,

Eagle Point,

 

Oreg.

[21]

Appl. No.: 480,206

 

[22]

Filed:

Jun. 7, 1995

Related

U.S. Application

Data

[62]

Division

of Ser.

No.

389,334, Aug.

3,

1989, Pat.

No.

[51]

5,440,749.

Int. CI.'

G06F

9/22

[52]

U.S. CI

395/800;

364/931; 364/925.6;

364/937.1; 364/965.4; 364/232.8; 364/244.3

[58]

Field of Search

395/375,

500,

 

395/775, 800

[56]

References

Cited

U.S. PATENT DOCUMENTS

3,603,934

9/1971

Heath

395/181

4,003,033

1/1977

Of Keefe et al

395/287

4,037,090

7/1977

Raymond

364/706

4,042,972

8/1977

Grunes

et al

395/375

4,050,058

9/1977

Garlic

395/800

4,067,058

1/1978

Derchak

395/740

4,079,455

3/1978

Ozga

395/800

4,110,822

8/1978

Porter

395/375

4,125,871

11/1978

Martin

395/550

4,128,873

12/1978

Lamiaux

395/183.06

4,253,785

3/1981

Chamberlin

375/375

4,354,228

10/1982

Moore

et al

395/800

4,376,977

3/1983

Brunshorst

395/375

4,382,279

5/1983

Mgon

et al

395/800

4,403,303

9/1983

Howes

395/500

4,450,519

5/1984

Guttag

et al

395/800

4,463,421

7/1984

Laws

395/325

4,538,239

8/1985

Magar

364/759

(List continued

on next page.)

OTHER PUBLICATIONS

C. Whitby Strevans, "The transputer", The 12th Annual International Symposium on Computer Architecture, Con-

ference

Proceeings,

Jun. 17 19, 1985, pp. 292 300.

D. W. Best et al., "An Advanced Architecture

CMOS/SOS

Microprocessor",

11-25.

IEEE Micro,

vol. 2, No. 3, Aug.

1982, pp.

Primary Examiner David Y. Eng Attorney, Agent, or Firm Cooley Godward Castro Huddle-

son & Tatum

[57]

A microprocessor

processing

ABSTRACT

(50) includes

a main

central

unit (CPU) (70) and a separate direct memory access (DiVIA) CPU (72) in a single integrated circuit making up the

(50). The main CPU (70) has a first 16 deep

push

microprocessor

down

stack (74), which

has a top item register

(76) and

a next item register

(78), respectively

connected

to provide

inputs

to an arithmetic

logic unit

(ALU) (80) by lines

(82)

and (84). An output of the ALU (80) is connected to the top

item register (76) by line (86). The

register at (82) is also connected by line (88) to an internal data bus (90). A loop counter (92) is connected to a decre-

of the top item

output

menter

bidirectionally connected to the internal data bus (90) by line

(100). Stack pointer (102), return stack pointer (104), mode

register (106) and instruction

nected to the internal data bus (90) by lines (110), (112),

(94) by lines

(96) and (98). The loop counter

register

(108) are

also

(92) is

con-

(114) and

connected

gate (120) provides

to X register (128), program counter (130) and Y register

(132) of return push down stack (134).The X register (128),

on lines (122), (124), and (126)

(116), respectively.

to memory

controller

inputs

The internal

data bus

(90) is

(118) and to gate (120).The

program

counter

(130) and Y register

(132) provide

outputs

to internal

address bus (136) on lines (138), (140) and (142).

The

internal

address

controller

(118) and

bus

to

provides

inputs

an

incrementer

to

the

memory

(144). The

incre-

menter

counter

Y register

(126). The DiVIA CPU (72) provides

controller

(144) provides

and

inputs

via

to

lines

the

X register,

program

(146), (122), (124) and

inputs

to the memory

controller

(118)

(118) on line (148). The memory

is connected

lines (152).

to a RAM by address/data

bus (150) and control

10 Claims,

19 Drawing

Sheets

ql

/46

R f44

INCREMENT"R

l22

/ tzz

Izlf

X REGISTER

P

~/24

~/26

0 IZD

fzz i

PROGRALI

COUNTER

l42 )

Izz

V REGISTER

RETURN

STACK

6

LOCAL

VARIABLES

I6 DEEP

~GA»

INTERNAL

DATA BUS

~»6

60

70

r/2

X

DNA OPU

!

62 5

f02

I04

/06

I

MEMORV

CONTROLLER

»I

Izz

ADDRESS/

DATA

I 7

CONTROL

LINES

6

TOP OF STACK

NEXT ITEM

PARAIA

STACK

16 DEEP

TER

/-52

COUNTER

STACK

POINTER

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POIIITER

MODE

REGISTER

INSTRUCTIOI'I

REGISTER

M50

50 A

lzz

I

NP

/

I/2

/

llf

/

ff6

/

U.S. PATENT DOCUMENTS

5,530,890

Page 2

4,541,045

9/1985

Kromer

395/375

4,562,537

12/1985

Barnett

et al

395/375

4,577,282

3/1986

Candel

et al

395/800

4,607,332

8/1986

Goldberg

et al

395/375

4,626,988

12/1986

George

395/375

4,649,471

3/1987

Briggs

395/325

4,665,495

5/1987

Thaden

345/185

4,709,329

11/1987

Hecker

395/275

4,713,749

12/1987

Magar

et al

395/375

4,714,994

12/1987

Oklobdzija

et al

395/375

4,720,812

1/1988

Kao et al.

4,772,888

9/1988

Kimura

4,777,591

10/1988

Chang

et al

4,787,032

11/1988

Culley

et al

4,803,621

2/1989

Kelly

4,860,198

8/1989

Takenaka

4,870,562

9/1989

Kimoto

4,931,986

6/1990

Daniel

et al

5,036,460

7/1991

Takahira

5,070,451

12/1991

Moore et al

5,127,091

6/1992

Bonfarah

395/700

340/825.5

395/800

395/725

, 395/400

395/307

395/550

, 395/550

395/425

395/375

395/375

U.S. Patent

Jun. 25, 1996

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Sheet 9 of 19

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Jun. 25, 1996

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5,530,890

HIGH PERFORMANCE,

LOW COST

MICROPROCESSOR

CROSS REFERENCE TO RELATED

APPLICATIONS

5

It is

a further

object of the

performance

require

responses

use

microprocessor

of the

main

CPU

and

which

provides

invention

to provide

a high

in

which

DMA

does

not

and

during

very

DMA

rapid

requests

DMA response

with

predictable

response

times.

This application

is a division

of U.S. application

Ser. No.

07/389,334, filed Aug.

749.

3, 1989, now

U.S. Pat. No. 5,440,

BACKGROUND

OF THE INVENTION

The

attainment

of

these

and

related

objects

may

be

achieved

through

use

of the

novel

high

performance,

low

10

cost microprocessor

herein

disclosed.

In accordance

with

one

aspect

of the

invention,

a microprocessor

system

in

accordance

with

this invention

has a central

processing

unit,

a dynamic random access memory

and a bus connecting

the

1. Field of the Invention

The

present

invention

central

memory. There is a multiplexing means on the bus between

the central processing unit and the dynamic random access

memory. The multiplexing means is connected and config-

ured to provide row addresses, column

the bus.

the

addresses and data on

processing

unit

to

the

dynamic

random

access

relates

generally

to a simplified,

reduced instruction set computer (RISC) microprocessor.

it relates to such a microprocessor which

is capable of performance levels of, for example, 20 million

More particularly,

instructions

per second (MIPS) at a price of, for example,

20

dollars.

2. Description

of the Prior Art

 

since the invention

of the microprocessor,

improvements

in its design

approach, a brute force gain in performance has been achieved through the provision of greater numbers of faster transistors in the microprocessor integrated circuit and an instruction set of increased complexity. This approach is exemplified by the Motorola 68000 and Intel 80X86 micro-

have taken two different

approaches.

In the first

15

In accordance

microprocessor

The

means

multiple

with

system

another

has a means

aspect

of the

connected

invention, to the bus

for

to

20

fetching instructions for the central processing unit on the

bus.

fetch

for fetching

sequential

instructions

in

is configured

a single

instructions

memory

cycle. In a variation of this aspect of the invention,

programmable read only memory containing instructions for

the central processing unit is connected to the bus. The means for fetching instructions includes means for assem-

a

25

bling a plurality of instructions from the programmable read only memory and storing the plurality of instructions in the

dynamic random access memory.

processor families. The trend in this approach sizes and packages, with hundreds of pinouts.

is to larger die

30

More

recently,

it has

been

perceived

that

performance

gains can be achieved through comparative

in the microprocessor integrated circuit itself and in its

instruction set. This second approach provides RISC micro- processors, and is exemplified by the Sun SPARC and the Intel 8960 microprocessors. However, even with this approach as conventionally practiced, the packages for the

microprocessor

are large, in order to accommodate the large

simplicity,

both

number

of pinouts

that

continue

to be employed.

A need

therefore

remains

for further

simplification

of high

perfor-

mance

microprocessors.

 

With

conventional

high

performance

microprocessors,

fast static memories are required for direct connection t.o the

microprocessors in order to allow memory accesses that are fast enough to keep up with the microprocessors. Slower

dynamic

such

random

access memories

only

in

microprocessors

(DRAMs)

are used

with

a

hierarchical

memory

a buffer

between the microprocessors and the DRAMs. The neces- sity to use static memories increases cost of the resulting

systems.

arrangement,

with

the

static

memories

acting

as

Conventional microprocessors provide direct memory

DMA

controllers, which may be located on the microprocessor

integrated circuit, or provided separately. Such DMA con- trollers can provide routine handling of DMA requests and

responses,

accesses

(DMA) for system

but some processing

peripheral

units

through

by the main central process-

ing unit

(CPU) of the microprocessor

is required.

In another aspect of the invention, the microprocessor

a direct memory

system

access processing unit and a memory

The direct memory access processing unit includes means

includes

a central

processing

unit,

connected

by

a bus.

35 for fetching instructions for the central processing unit and

for fetching instructions for the direct memory access pro-

cessing

unit

on the bus.

aspect

for fetching

for receiving

In a further

of