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  • Lab 3

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    biswarup80
    37 vizualizări7 pagini
    For this lab, we used a simple program that helps us lay out silicon and metal layers, to draw basic transistors. We first laid out an NMOS transistor and then a PMOS transistor. Then combining these (CMOS) we constructed an inverter gate, a nand gate and a nor gate. We then extracted out layout and simulated our gates in SPICE(r)

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    For this lab, we used a simple program that helps us lay out silicon and metal layers, to draw basic transistors. We first laid out an NMOS transistor and then a PMOS transistor. Then combining these (CMOS) we constructed an inverter gate, a nand gate and a nor gate. We then extracted out layout and simulated our gates in SPICE(r)

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    37 vizualizări7 pagini

    Lab 3

    Încărcat de

    biswarup80
    For this lab, we used a simple program that helps us lay out silicon and metal layers, to draw basic transistors. We first laid out an NMOS transistor and then a PMOS transistor. Then combining these (CMOS) we constructed an inverter gate, a nand gate and a nor gate. We then extracted out layout and simulated our gates in SPICE(r)

    Drepturi de autor:

    Attribution Non-Commercial (BY-NC)
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    din 7

    e77 .

    lab 3 : laying out simple circuits

    Page 1 of 7

    adem kader . david luong . mark piper


    10.17.2005

    E77 VLSI Design: Lab 3 laying out simple circuits

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    Metal Gate

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    IC Layout

    Circuit Layout

    abstract.
    For this lab, we used L-edit, a simple program that helps us lay out silicon and metal layers, to draw basic transistors. We first laid out an NMOS transistor and then a PMOS transistor. Then combining these (CMOS) we constructed an inverter gate, a nand gate and a nor gate. We then extracted out layout and simulated our gates in SPICE. Finally, we created a 4-input nand gate in two ways; first using CMOS to build one from ground up, and second by combining the NAND, NOR and the inverter gates.

    task 1 : inverter (NOT)

    Figure 1. the inverter (not gate)

    Figure 2. the inverter layout (click on image for larger version)

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

    24-07-2012

    e77 . lab 3 : laying out simple circuits

    Page 2 of 7

    Figure 3. SPICE output for the NOT gate. SPICE circuit file for the inverter. NOT gate input 0 1 output 1 0

    Table 1. NOT gate (inverter) output

    task 2 : NAND gate

    Figure 4. the NAND gate

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

    24-07-2012

    e77 . lab 3 : laying out simple circuits

    Page 3 of 7

    Figure 5. the NAND gate layout (click on image for larger version)

    Figure 6. SPICE output for the NAND gate. SPICE circuit file for the NAND gate. NAND gate A 0 0 1 1 B 0 1 0 1 output 1 1 1 0

    Table 2. NAND gate output

    task 3 : NOR gate

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

    24-07-2012

    e77 . lab 3 : laying out simple circuits

    Page 4 of 7

    Figure 7. the NOR gate

    Figure 8. the NOR gate layout (click on image for larger version)

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

    24-07-2012

    e77 . lab 3 : laying out simple circuits

    Page 5 of 7

    Figure 9. SPICE output for the NOR gate. SPICE circuit file for the NOR gate. NOR gate A 0 0 1 1 B 0 1 0 1 output 1 0 0 0

    Table 3. NOR gate output

    All gates are seen together in Figure 10.

    Figure 10. all gates seen together (click on image for larger version)

    task 4 : 4-input NAND gate


    We can create a 4-input NAND gate in two ways. The first way is to layout the circuit in CMOS. Figure 11 shows the layout and Figure 12 shows the layout using L-edit.

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

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    e77 . lab 3 : laying out simple circuits

    Page 6 of 7

    Figure 11. the 4-input NAND gate (CMOS)

    Figure 12. the 4-input NAND gate layout (click on image for larger version) Another way to create a 4-input NAND gate is to use the NAND, NOR and NOT gates we've already created. Figure 13 shows how 2 NAND gates, a NOR gate and a NOT gate can be put together to implement the 4-input NAND gate.

    Figure 13. implementation of a 4-input NAND gate using 2 NAND one NOR and a NOT gate. As an extension, we laid out the gates in L-edit (see Figure 14). A comparison of Figure 14 and Figure 12 shows how much more compact the gate would be if it were built from scratch (and not using other gates).

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

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    e77 . lab 3 : laying out simple circuits

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    Figure 14. the 4-input NAND gate layout using 2 NAND one NOR and a NOT gate. (click on image for larger version)

    no copyright; all of the above work was done for the sake of science and engineering

    http://www.sccs.swarthmore.edu/users/06/adem/engin/e77vlsi/lab3/

    24-07-2012

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