Fully Digital Hysteretic Modulator for DC-DC Switching Converters

Luca Corradini, Aleksandar Bjeleti, Regan Zane, Dragan Maksimovi

Colorado Power Electronics Center ECEE Department University of Colorado at Boulder {corradin, bjeletic, zane, maksimov}@colorado.edu

Abstract This paper presents an alternative modulation approach for digitally controlled DC-DC switching converters, which exploits the natural jittering activity of a digital hysteretic feedback loop in order to provide an effective increase in resolution. The proposed structure replaces conventional highresolution digital pulse-width modulators (DPWM) or sigmadelta based (-DPWM) solutions with a single, fully-digital block featuring reduced complexity, high resolution, and improved noise performance and small-signal dynamic characteristics, enabling the design of accurate, high-bandwidth digital feedback loops with minimum hardware resources. A stochastic modeling approach is developed for the proposed structure, which allows the derivation of a simple and effective switching frequency control criterion. Analysis, simulation and experimental tests are shown to validate the properties of the proposed digital hysteretic modulator. Index Terms digital control, hysteretic modulator, sigmadelta digital pulse width modulator.

exponential function of the desired resolution n, to hybrid structures which limit the required clock frequency at the expense of an increased hardware complexity by combining a low-resolution, counter-based module with a fine-resolution delay-line [4]. Sigma-delta digital pulse-width modulation (-DPWM) is another well known technique, successfully adapted from the field of digital signal processing, employed to maintain a high effective resolution without the need for high clock frequencies [5], [6]. In this case the concept consists of increasing the effective resolution by dithering the input command to a low-resolution DPWM using a loop. This paper proposes an alternative modulation strategy based on the digital hysteretic feedback loop illustrated in Fig. 1(b). A single, low-complexity digital block replaces the typical -DPWM arrangement while still achieving a significant increase in the effective resolution similar to multibit structures.

I.

INTRODUCTION.

As digital control techniques for DC-DC switching converters are gaining popularity due to advantages such as programmability, robustness and options for more advanced controls [1]-[3], there are still challenges in digital design that are not present in analog designs. An important issue is related to the timing resolution of the digital modulator, i.e. the portion of the digital controller that modulates the command signal (e.g. duty cycle command d[k]) calculated by the compensator into a logic on/off switching signal S suitable for driving the power stage at a desired switching frequency fs. It is well known how time quantization effects induced by the digital nature of the modulator limit the set of duty cycles that can be represented, making the implementation of highresolution digital pulse-width modulators a nontrivial task. The block diagram in Fig. 1(a) illustrates a standard digital voltage-mode control for a buck converter. Given the duty cycle command signal d[k] with a resolution of n bits, the problem consists of implementing a modulator capable of transmitting that resolution to the power converter, i.e. capable of generating the signal S without resolution loss. Proposed approaches and designs range from the simple counter-based DPWM structure, in which the clock frequency fclk = 2nfs is an

d[k]

S
Digital Modulator

Vin Buck Converter L C vo(t)

fclk
Digital Compensator

A/D

Vref

fsmp
(a)
Proposed Hysteretic Modulator r + 1
-

d
n

1 z 1
fclk

S 0

z-1

-/2

0 +/2

(b) (c) Fig. 1. Digitally-controlled DC-DC buck converter (a), proposed hysteretic modulator (b), and transfer characteristic of the hysteretic comparator (c).

978-1-4244-2893-9/09/$25.00 2009 IEEE

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Furthermore, the modulator has better noise performance in terms of generated low-frequency tones compared to a conventional first-order structure having the same core DPWM resolution. Finally unlike -DPWM, the proposed digital hysteretic modulator can be operated in a multi-sample fashion [7], [8] with reduced small-signal delay [9], thus enabling high-bandwidth closed-loop voltage regulation. This paper discusses the structure of the hysteretic modulator along with its operation in open-loop and closedloop converter configurations. Section II describes the principle of operation of the proposed hysteretic modulator; a stochastic analysis is presented that predicts the switching rate of the modulator as a function of the hysteresis window and of the operating duty ratio D. A simple and effective criterion to control the modulator switching rate is derived from the proposed model and experimentally verified. Section III discusses the effective increase in resolution and the noise performance of the modulator, comparing the hysteretic structure to a conventional -DPWM arrangement through both simulation and experimental tests. Section IV addresses the converter closed-loop operation using a complete digital controller with the proposed modulator, experimentally verifying the advantages of the multi-sampled operation. II. DIGITAL HYSTERETIC MODULATOR A. Description of Operation Fig. 1(b) illustrates the block diagram of the proposed digital hysteretic modulator. It consists of an entirely digital system clocked at a fixed clock frequency fclk, typically in the range of tens of megahertz. A digital integrator clocked at fclk processes the error between the n-bit input duty-cycle command d[k] and the binary output S. The output r[nTclk] of the integrator is processed by a hysteretic digital comparator, whose transfer characteristic is sketched in Fig. 1(c). The variable is a programmable digital word that sets the hysteresis window and facilitates a controllable switching rate. Operation of the hysteretic modulator can be described with reference to Fig. 2, assuming a constant input duty cycle command d = D and with the output state initially at S = 0. Given a constant input signal and the output state at S = 0, the digital accumulator integrates the difference D 0 = D, therefore producing an increasing digital ramp. The output bit remains at S = 0 as long as r < +/2. As soon as the ramp exceeds the positive threshold +/2, the hysteretic comparator switches to S = 1. This event marks the end of the turn-on interval and the beginning of the turn-off interval. After the output has switched to S = 1 the digital accumulator integrates the negative error D 1, thus generating a decreasing ramp. The switch signal remains at S = 1 as long as r > /2. When r < /2 the switch signal changes back to S = 0 and a new switching cycle begins. It is important to realize that the switch turn-on and turn-off events are synchronous with the clock frequency fclk due to the

8 6 4 2 0 -2 -4 -6 -8 0 1.25 1 0.75 0.5 0.25 0 -0.25 0 0.5 1 1.5 2 2.5 3 3.5

/2

r[nTclk]

tON

0.5

1.5

2.5

3.5

tON and tOFF jittering

tOFF Switching Interval Ts

Time (s)
Fig. 2. Steady-state waveforms: of r and (top) and switching signal S (bottom).

entirely digital nature of the system. Therefore, the on-state and off-state intervals tON and tOFF are always integer multiples of the clock period:

t ON = nON Tclk , t OFF = nOFF Tclk

(1)

Similar to loops, the presence of the digital integrator within the modulator digital loop forces the output average value to be equal to D:

S =

nON nON + nOFF

= D.

(2)

Given (1), it is clear that (2) may not be true when averaged over a single switching period Ts. In this case, both nON and nOFF will vary cycle-by-cycle, and the steady-state operation of the modulator will exhibit jittering of both the turn-on and turn-off intervals. This jittering activity is exemplified in Fig. 2 by the shaded areas around the switching transitions, and will be referred to as the jittered-tON/jittered tOFF mode of operation of the hysteretic modulator. Therefore, although the cycle-by-cycle duty ratio is produced only with a time resolution given by Tclk, its value over time is reproduced with higher resolution. In other words, the jittering activity allows the modulator to reproduce duty cycles with an effective time resolution finer than Tclk. Experimental evidence of this increase in effective resolution is presented in Section III. An immediate side-effect of this behavior is a corresponding jittering of the switching period Ts. In fact, the very notion of switching frequency may appear ill-defined in the context of the hysteretic modulator. However, the average switching period Ts and average switching frequency fs can be rigorously defined as the expected values assumed by the per-cycle quantities:

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Ts t ON + t OFF = nON + nOFF Tclk fs 1 Ts . (3)

r

5.12

Tclk
5.02

+/2
4.92

In the next subsection, a stochastic model is presented to better analyze the switching behavior of the modulator. The main purpose of the model is to express quantities (3) as functions of the hysteresis window and of the operating duty cycle D. B. Analysis of the switching behavior

Tclk
3.34 3.35 3.36 3.37

4.82 3.33 1.25

1 0.75 0.5 0.25 0 -0.25 3.33 3.34 3.35 3.36 3.37

In this section a stochastic analysis is presented in order to predict the average switching rate fs. In particular, the average switching cycle Ts will be derived as the expected value of the quantity tON + tOFF. Note that steady-state operation of the modulator is assumed in the following analysis, i.e. d = D = constant. A primary consideration in the stochastic model presented here is the assumption that in its steady-state operation the modulator randomly spans all the possible switching configurations compatible with the input duty cycle D. In order to formalize the concept, consider the switch turn-on event detailed in Fig. 3, and assume D < 0.5. The quantity identifies one particular position of the ramp with respect to the hysteresis window for a given input duty cycle D. As spans between 0 and 1, all possible switching configurations for a given input duty cycle D are found. This assumption can be formalized by letting be a random variable uniformly distributed between 0 and 1:

Time (s)
Fig. 3. Expanded view of the switch turn-on event.

In a similar way it is possible to express nOFF as:

n (1 D ) (1 ) D nOFF = ceil ON . D (6)

U ([0,1])

(4)

The situation presented holds when D < 0.5. Whenever D > 0.5, a symmetric scenario must be considered with associated with the switch turn-off event. As the problem is symmetrical, the analysis is given here for the case of D < 0.5 to show that the assumption (4) explains the modulator average switching rate as well as its dependence on the hysteresis window and duty cycle D with good accuracy. It should be noted, however, that the system under consideration is entirely deterministic, and that the assumption (4) is introduced just to simplify the treatment using stochastic analysis. From Fig. 2 and based on simple geometrical considerations, the number nON of clock cycles during the turn-on interval is given by the total variation of the digital ramp divided by its slope 1D, the result rounded to the next integer:

Equations (5) and (6) express nON and nOFF as discrete random variables which are functions of . Stochastic analysis can now be used to derive the turn-on and turn-off statistics, and ultimately the expected switching rate (3). The results for D < 0.5 can be summarized as follows: 1. The average switching rate fs depends on both D and . 2. In general, nON jitters between at most two distinct, consecutive values, while nOFF may jitter among two to four distinct values. As already mentioned, the mode of operation in which both the turn-on and turn-off intervals are jittered during the modulator steady-state operation is denoted as jittered-tON/jittered-tOFF. 3. A discrete set of switching rates exists for which nON assumes a single value with probability one; correspondingly, nOFF jitters between at most two consecutive values. This particular mode of operation of the modulator will be denoted as constant-tON/jittered-tOFF. Examples of theoretical and experimental fs() characteristics are shown in Fig. 4 for different values of D. The clock frequency was set at fclk = 50 MHz. It can be seen how the proposed stochastic analysis reproduces the fs() behavior with a fairly good accuracy over a wide range of operating points and hysteresis windows.

+ (1 ) D nON = ceil . 1 D

(5)

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kHz

600 550 500

600

fs()
D = 10%

50%

kHz
550 500 450
25

Theoretical o Experimental

40% 20% 30%

20

450 400 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5

Theor. o Exp.
5 10 15

fs(), D = 20%
13.5 14 14.5 15 15.5 16 16.5 17

Relative error

400 13

(a)
1.25 1 0.75

p(nON)

Theoretical x Experimental

10

15

20

25

Fig. 4. Theoretical and experimental switching rate as a function of the hysteresis window and for different operating points

0.5 0.25 0 14
1.25 1 0.75 0.5 0.25 0 73 74 75 76 77 78 79 80 81 82 83 84

15

16

17

18

19

The latter point, i.e. the existence of a discrete set of frequencies for which the modulator only jitters the turn-off interval with a constant turn-on time, deserves a more detailed discussion. Equation (5) predicts the existence of particular values of for which nON assumes a single value with probability one. This situation occurs when the argument of the ceil() operator in (5) spans an interval strictly comprised within two consecutive integers n and n+1 or, in other words, when:
n (1 D ) < n (1 D) + (1 2 D ) ,

nON

20

21

22

23

24

25

p(nOFF)

Theoretical x Experimental

nOFF

(7)

where n is a natural number. Equation (7) identifies intervals of for which the constant-tON/jittered-tOFF operation occurs. It is easy to realize that n = nON1, and therefore each possible value of tON generates an interval of the type (7) for . When the switching rate fs is evaluated over intervals (7), a very simple relationship is obtained: fs = D f clk . nON (8)

(b) Fig. 5. Detail of the fs characteristic for D = 0.2 (a) and turn-on and turn-off probabilities for = 15.35 (b)

C.

Control of the Average Switching Rate

In other words, when the modulator operates in constanttON/jittered-tOFF mode, the average rate, which is given by (8), does not depend on . Intervals (7) therefore identify a discrete set of frequencies associated with this particular mode of operation. Fig. 5(a) shows a detail of the fs() characteristic for D = 0.2; intervals (7) are clearly visible, as well as the corresponding discrete sets of frequencies. Fig. 5(b) reports theoretical and experimental turn-on and turn-off probabilities for a point inside the fs = 500 kHz interval, confirming that the modulator is jittering only the turn-off period.

One concern associated with the switching behavior of the hysteretic modulator is the variation in the average switching frequency over converter operating duty cycles D. This section shows how the hysteresis window can be used to control the average switching frequency to a nominal desired value over a range of D. The particularly simple expression (8), valid when the modulator operates in the constant-tON/jittered-tOFF mode, lends itself to a straightforward switching frequency control method. Consider such that fs is set as close as possible to a nominal desired value fs. In this case:

D f nON = round ~ clk f s

(9)

From (7) a unique interval is selected by (9). Within this interval, any choice of would produce the same average switching rate. Taking arbitrarily the midpoint of this interval as the choice for yields:
D f = round ~ clk f s 1 (1 D ) + 1 2 D 2 (10)

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Choice (10) allows selection of as a function of the converter operating duty cycle command D, which is a quantity readily available in the digital controller. As the ratio fclk/fs is a constant design parameter, evaluation of (10) requires only simple arithmetic operations. With choice (10), the average switching frequency is given by: D f clk ~ ~ fs = fs D f round ~ clk f s

D.

Constant-tON/jitterered-tOFF mode

The constant-tON/jittered-tOFF option appears particularly appealing especially at small duty cycles due to the higher resolution compared to conventional constant-frequency modulation techniques. To illustrate this point, consider first the smallest duty cycle variation achievable through a constant-frequency counter-based DPWM technique:
D min =

fs

(11)

1 , Ns

(12)

It is important to note that an immediate drawback in using (8) to control the switching frequency is a quantization effect expressed by that very same equation. As a consequence, exact tracking of an arbitrary fs cannot be achieved. This is expressed, in (11), as the resulting average switching rate being equal to the nominal value fs to within a factor of the type x/round(x). However, the simple criterion expressed by (10) justifies small residual variations in the average switching rates. One may further observe that the higher the clock frequency with respect to the nominal switching rate, the closer fs is to the nominal desired value fs. Fig. 6 illustrates the theoretical and experimental plots of (10) for fs = 390.625 kHz, fclk = 50 MHz and for different values of the steady-state duty ratio D. As seen, the measured switching rate matches the predicted value (11); as expected, the x/round(x) factor generates residual variations of the switching rate around fs. in spite of this slight non-ideality, the criterion (10) limits the switching frequency deviation to within few percentage points with respect to fs.
410 400

where Ns = fclk/fs represents the number of modulator clock cycles per switching period. A sigma-delta modulation increases the resolution beyond (12) by dithering the duty ratio command over several switching cycles. On the other hand, if we consider a constant-tON modulation scheme i.e. a control where the duty cycle is varied by modulating the turn-off interval with a constant turn-on time one has:
D min = D , Ns

(13)

Nominal fs

Theoretical fs

(kHz)
390 380 370 0.09

0.12

0.15

D (a)

0.18

0.21

0.24

410 400

Nominal fs

Theoretical fs

(kHz)
390 380 370 0.09

4%
0.1

Experimental fs
0.11

0.12 D (b) Fig. 6. Modulator nominal and average switching rate vs. operating point with the proposed switching frequency control approach (a); expanded view and experimental comparison (b)

with a better resolution compared to (12), especially at small duty cycles. It is important to note that the proposed hysteretic modulator does not implement a constant-tON modulation, since two different duty cycles are generally represented by two different turn-on times. However, when operated in constant-tON/jittered-tOFF mode, each duty cycle is reproduced in such a way that the turn-on interval does not change over time. Therefore, through jittering of the turn-off interval between two consecutive LSBs, resolution (13) or higher is achieved. Similar arguments regarding the modulator resolution have been presented in [10] where it was recognized that a digital constant-tON modulation inherently has a higher resolution than a constant-frequency modulation, with the main disadvantage of having an extremely variable switching rate. To address this issue, [10] proposes a modulation scheme in which constant-tON modulation and constant-frequency modulation are combined. In this context, the control criterion (10) can be thought of as having a similar purpose: given a specific switching rate given by (8), criterion (10) determines a particular nON. Once nON has been selected to limit the switching rate variation, the turn-off time is naturally jittered by the hysteretic modulator in order to reproduce the duty cycle with high resolution. It is interesting to observe that both of these goals switching rate control and constant-tON operation are simultaneously achieved by a very simple control of the modulator hysteresis window. III. OPEN-LOOP PERFORMANCE In this section the open-loop behavior of the proposed hysteretic modulator is evaluated through computer

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simulations and experimental tests. In particular, it is of interest to carry out a systematic comparison between the proposed structure and a conventional first-order, multi-bit -DPWM that would be slightly more complex in hardware resources compared to the hysteretic modulator. The configuration considered for this comparison consists of the modulator under test hysteretic or -DPWM followed by a power converter. The power stage taken as a test case is a synchronous buck converter having Vin = 12 V, 1.2 V nominal output voltage, L = 4.8 H, C = 377 F, ESR = 1 m. The hysteretic modulator is clocked at fclk = 50 MHz, with a nominal switching rate set to fs = 390.625 kHz, corresponding to an average of 128 clock cycles per switching period. The switching frequency control criterion (10) is employed to limit the variations of fs over the operating range. For the -DPWM, the switching rate is set to fs in order to provide a similar switching frequency as the hysteretic modulator. The resolution of the core DPWM quantizer of the -DPWM is set to 7 bits, corresponding to an LSB of 1/128 of the switching period. This choice allows a fair comparison between the two modulators, as both operate with the same core time resolution Tclk. Furthermore, the digital input duty cycle command for both the hysteretic and the -DPWM structure is assumed to be 13 bits wide. The open-loop comparison was first simulated by slowly sweeping the input duty cycle command and observing the output voltage ramp waveform. The sweep was performed in the range Vo = 1V100 mV, spanning about 137 LSB of the 13-bit input command. The comparison is shown in Fig. 7(a). The output voltage of the -DPWM based system exhibits at least three distinct spots where a significant perturbation is observed. This well-known phenomenon is due to the generation of low-frequency idle tones from the first-order modulator [5], [6]. Interestingly, the voltage ramp generated by means of the hysteretic modulator exhibits a different behavior. From the expanded view shown in Fig. 7(b), the hysteretic modulator is clearly able to transmit the 13-bit resolution to the output voltage: the LSB step of the ramp is in fact Vin/213 = 1.5 mV. On the other hand, the resolution of the -DPWM is clearly compromised by the idle tones triggering rather large amplitude oscillations. A similar test has been performed experimentally, with the hysteretic modulator and the -DPWM coded in hardware description language (HDL) and implemented on a Xilinx Virtex-2 FPGA board. Fig. 8 and Fig. 9 illustrate the resulting output voltage ramp as the 13-bit input command is slowly swept. The input sweep was performed at about 0.75 Hz and spanned 64 LSB of the duty cycle command. The result of this experiment is fully coherent with the foregoing simulation test: though a 13-bit resolution is achieved in both cases, in the -DPWM case regions are found in which the output voltage is heavily corrupted by idle tones. No such phenomena are observed with the hysteretic modulator.

1.1 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 0.92 0.9 0 1.1 1.08 1.06 1.04 1.02 1 0.98 0.96 0.94 0.92 0.9 0

vo (V) -DPWM

Idle tones
2 4 6 8 10 12 14 16 18 20

vo (V) Hysteretic Modulator

time (ms)
(a)

10

12

14

16

18

20

0.95

vo (V)
0.94

-DPWM

LSB = 1.5mV Hysteretic Modulator

0.93 3

3.5

time (ms)

4.5

(b) Fig. 7. Simulated open-loop response to a duty cycle ramp; comparison between the hysteretic modulator and a conventional first-order -DPWM (a) and close-up comparison around a specific operating point (b)

vo

10 mV/div 40 ms/div

LSB = 1.5mV

Channel offset: 1.19V

Fig. 8. Experimental open-loop response to an input duty cycle ramp; proposed hysteretic modulator

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IV. CLOSED-LOOP PERFORMANCE

10 mV/div 40 ms/div Idle Tones

vo

LSB = 1.5mV

Channel offset: 1.19V

Fig. 9. Experimental open-loop response to an input duty cycle ramp; conventional first-order -DPWM

To further investigate the open-loop noise performance, the power spectral density (PSD) of the converter output voltage was measured with the converter in open-loop, steady-state operation i.e. at a constant input duty-cycle command D. A comparison between the two systems under consideration is exemplified in Fig. 10, which illustrates the two PSD measured at D 8%, a particular operating point where the -DPWM was recognized to generate particularly large idletone oscillations. The most striking difference between the two lies in the low-frequency range, where the tone-generation activity of the hysteretic modulator is almost absent. Note, however, that the hysteretic structure does generate lowfrequency tones one is visible around 12 kHz. More extensive experimental tests have shown that the smaller the steady-state duty cycle, the less prone the hysteretic modulator is to generating low-frequency tones. When the hysteretic modulator is operated at small D e.g. around 10% or less its low-noise properties outperform those of a first-order -DPWM having the same core hardware resolution. At higher duty cycles, spots were found where the tone generation of the hysteretic structure was slightly higher than the -DPWM. Nevertheless, the hysteretic modulator manifests a generally much less severe tone generation activity compared with first-order -DPWM.
0

(dB)
-10 -20 -30 -40 10

-DPWM Hysteretic

Switching Harmonics

100

1k

10k

100k

1M

10M

62.5M

Frequency (Hz)
Fig. 10. Experimental power spectral density; comparison between proposed hysteretic modulator and a conventional -DPWM; D=0.08

Compared with a conventional -DPWM, an important advantage of the proposed structure is its ability to operate in a multi-sampled fashion. Referring back to Fig. 1(a), this means that the controller samples and processes the voltage error with a sampling rate higher than the converter switching rate, i.e. fsmp = Nfs, N > 1. Similar to conventional DPWM structures, the multi-sampling operation significantly decreases the modulator small-signal phase lag [9], thus enabling high-bandwidth designs [7], [8]. An important point to be stressed is that conventional -DPWM structures cannot be operated at fsmp > fs because of the re-sampling action of the PWM block following the modulator. This represents a strong advantage of the proposed structure over the entire class of -based PWM realizations. The closed loop operation was tested through simulation and experimental tests on the same setup described in Section III. A simple digital PID structure was used as the voltage loop compensator, with the output voltage regulated at Vref = 1.2 V and sampled by a 12 bit, 4 V full-scale range pipeline A/D converter clocked at 12.5 MHz. The output stream of the A/D was then downsampled to the desired sampling rate fsmp. As far as the switching rate control is concerned, criterion (10) was employed. In order to avoid abrupt variations of the modulator hysteresis window during transients, the value of D in (10) was substituted with the integral term of the PID control command. An important aspect to be considered when employing the hysteretic modulator in a feedback loop is represented by its inherent tendency of varying the switching rate with the operating point, as exemplified in Fig. 4. Whenever a fixed sampling rate fsmp is adopted, any slight difference between fsmp and fs or between fsmp and Nfs in multi-sampled designs will result in a sampling instant not synchronized with the switching period. This situation can be detrimental, since a sampling instant falling too close to a switching transition could catch excessive noise and compromise the regulation. In the experimental setup, a low-noise differential sensing of the output voltage was implemented to mitigate the switching noise effects. A first single-sampled controller was designed for a bandwidth fc = 20 kHz with 70 phase margin. A second, highbandwidth 4-sampled compensator was designed for a fc 66 kHz and 62 phase margin. The target switching frequency, the same in both cases, was fs = 50 MHz/128 = 390.625 kHz. In the single-sampled design, the output voltage sampling rate was set equal to fs and the A/D resolution to qAD 8 mV by ignoring a number of LSBs from the A/D output; this choice resulted in limit cycle-free steady state operation. On the other hand, in the high bandwidth multi-sampled design with the sampling rate equal to 4fs a small amount of steady-state limit cycling was tolerated; the limit cycling amplitude was reduced to

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1.3 1.25

Multi-sampled design

vo 50mV/div

vo (V)
1.2 1.15 1.1 -20

Single-sampled design
0 20 40

time (s)

60

80

100

120

140

160

180

20s/div

Fig. 11. Simulated closed-loop transient response to a 0-4.6 A load step; comparison between single-sampled and multi-sampled design using the proposed hysteretic modulator.

iL

5A/div

negligible values by reducing A/D LSB down to ~2 mV. The simulated transient responses of the two foregoing controllers to a 0-4.6 A load step are compared in Fig. 11. Corresponding experimental tests are shown in Fig. 12 and Fig. 13 for the single-sampled and multi-sampled design respectively. The multi-sampled design allowed by the proposed modulator fully recovers the output voltage deviation in less than seven switching cycles. On the other hand, no -based design employing a conventional PID compensator could achieve similar performances, due to the aforementioned limitation of the sampling frequency. V. CONCLUSIONS An alternative modulation approach for digitally controlled DC-DC converters is proposed. By exploiting the inherent jittering activity of a digital hysteretic loop, the proposed modulator increases effective resolution without the need for a high frequency clock. Control of the switching rate is achieved through adjustment of the hysteresis window. When operated at relatively small duty cycles, the proposed modulator exhibits much better noise performance compared to conventional first-order -DPWM of similar hardware complexity and core resolution. Furthermore, in contrast to -based solutions, the proposed hysteretic modulator can be employed in a multi-sampled feedback control loop, thus enabling high bandwidth designs. Simulation and experimental results were presented for a 12V-to-1V, 5A synchronous buck converter, validating the open-loop and closed-loop characteristics of the proposed structure. REFERENCES
[1] [2] [3] [4] [5] D. Maksimovic, R. Zane, R. Erickson, Impact of Digital Control in Power Electronics, in Proc. 2004 ISPSD Conf., pp. 13-22 B. J. Patella, A. Prodic, A. Zirger, D. Maksimovic, High-Frequency Digital PWM Controller IC for DCDC Converters, IEEE Trans. on Power Electronics, vol. 18, no 1, pp. 438-446, Jan. 2003. J. Xiao, A. V. Peterchev, S. R. Sanders, Architecture and IC implementation of a digital VRM controller, IEEE Trans. on Power Electronics, vol 18, no. 1, pp. 356-364, Jan. 2003. A. Syed, E. Ahmed, D. Maksimovic, Digital Pulse-Width Modulator Architectures, in 2004 IEEE Power Electronics Specialists Conf., pp. 4689-4695 M. Norris, L. Marco Platon, E. Alarcon, D. Maksimovic, Quantization Noise Shaping in Digital PWM Converters, in 2008 IEEE Power Electronics Specialists Conf., pp. 127-133

pwm

load enable
Fig. 12. Experimental closed-loop transient response to a 0-4.6 A load step, single-sampled design; vo: 50mV/div, iL: 5A/div, time scale 20 s/div

vo 50mV/div

20s/div

iL

5A/div

pwm

load enable
Fig. 13. Experimental closed-loop transient response to a 0-4.6 A load step, multi-sampled design; vo: 50mV/div, iL: 5A/div, time scale 20 s/div [6] Z. Lukic, N. Rahman, A. Prodic, Multibit --PWM Digital Controller IC for DC-DC Converters Operating at Switching Frequencies Beyond 10 MHz, IEEE Trans. on Power Electronics, vol. 22, no. 5, pp. 16931707, Sept. 2007 [7] L. Corradini, P. Mattavelli, Modeling of Multisampled Pulse Width Modulators for Digitally Controlled DC-DC Converters, IEEE Trans. on Power Electronics, vol. 23, no. 4, pp. 1839-1847, Jul. 2008 [8] L. Corradini, P. Mattavelli, E. Tedeschi, D. Trevisan, High- Bandwidth Multisampled Digitally Controlled DC-DC Converters Using Ripple Compensation, IEEE Trans. on Power Electronics, vol. 55, no. 4, pp. 1501-1508, Apr. 2008 [9] D. M. Van de Sype, K. De Gussem, F. M. L. L. De Belie, A. P. Van den Bossche, J. A. Melkebeek, Small-signal z-Domain Analysis of Digitally Controlled Converters, IEEE Trans. on Power Electronics, vol. 21, no. 2, March 2006, pp. 470-478 [10] J. Li, Y, Qium Y. Sun, B. Huang, M. Xu, D. S. Ha, F. C. Lee, High Resolution Digital Duty Cycle Modulation Schemes for Voltage Regulators, in Proc.2007 APEC, Feb. 25-Mar 1 2007, pp. 871-876

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